pic24fj128ga010 family - Microchip

PIC24FJ128GA010 FAMILY3.2.2 DATA MEMORY ORGANIZATIONAND ALIGNMENTTo maintain backward compatibility with PIC ® devicesand improve data space memory usage efficiency, thePIC24F instruction set supports both word and byteoperations. As a consequence of byte accessibility, alleffective address calculations are internally scaled tostep through word-aligned memory. For example, thecore recognizes that Post-Modified Register IndirectAddressing mode [Ws++] will result in a value ofWs + 1 for byte operations and Ws + 2 for wordoperations.Data byte reads will read the complete word which containsthe byte, using the LSb of any EA to determinewhich byte to select. The selected byte is placed ontothe LSB of the data path. That is, data memory and registersare organized as two parallel byte-wide entitieswith shared (word) address decode but separate writelines. Data byte writes only write to the correspondingside of the array or register which matches the byteaddress.All word accesses must be aligned to an even address.Misaligned word data fetches are not supported, socare must be taken when mixing byte and word operations,or translating from 8-bit MCU code. If amisaligned read or write is attempted, an address errortrap will be generated. If the error occurred on a read,the instruction underway is completed; if it occurred ona write, the instruction will be executed but the write willnot occur. In either case, a trap is then executed, allowingthe system and/or user to examine the machinestate prior to execution of the address Fault.All byte loads into any W register are loaded into theLeast Significant Byte. The Most Significant Byte is notmodified.A sign-extend instruction (SE) is provided to allowusers to translate 8-bit signed data to 16-bit signedvalues. Alternatively, for 16-bit unsigned data, userscan clear the MSB of any W register by executing azero-extend (ZE) instruction on the appropriateaddress.Although most instructions are capable of operating onword or byte data sizes, it should be noted that someinstructions operate only on words.3.2.3 NEAR DATA SPACEThe 8-Kbyte area between 0000h and 1FFFh isreferred to as the near data space. Locations in thisspace are directly addressable via a 13-bit absoluteaddress field within all memory direct instructions. Theremainder of the data space is addressable indirectly.Additionally, the whole data space is addressable usingMOV instructions, which support Memory DirectAddressing with a 16-bit address field.3.2.4 SFR SPACEThe first 2 Kbytes of the near data space, from 0000hto 07FFh, are primarily occupied with Special FunctionRegisters (SFRs). These are used by the PIC24F coreand peripheral modules for controlling the operation ofthe device.SFRs are distributed among the modules that they control,and are generally grouped together by module.Much of the SFR space contains unused addresses;these are read as ‘0’. A diagram of the SFR space,showing where SFRs are actually implemented, isshown in Table 3-2. Each implemented area indicatesa 32-byte region where at least one address is implementedas an SFR. A complete listing of implementedSFRs, including their addresses, is shown in Tables 3-3through 3-30.TABLE 3-2:IMPLEMENTED REGIONS OF SFR DATA SPACESFR Space Addressxx00 xx20 xx40 xx60 xx80 xxA0 xxC0 xxE0000h Core ICN Interrupts —100h Timers Capture — Compare — — —200h I 2 C UART SPI — — I/O300h A/D — — — — — —400h — — — — — — — —500h — — — — — — — —600h PMP RTC/Comp CRC — — — I/O700h — — System NVM/PMD — — — —Legend: — = No implemented SFRs in this blockDS39747E-page 30© 2009 Microchip Technology Inc.