pic24fj128ga010 family - Microchip

PIC24FJ128GA010 FAMILY3.1.1 PROGRAM MEMORYORGANIZATIONThe program memory space is organized inword-addressable blocks. Although it is treated as24 bits wide, it is more appropriate to think of eachaddress of the program memory as a lower and upperword, with the upper byte of the upper word beingunimplemented. The lower word always has an evenaddress, while the upper word has an odd address(Figure 3-2).Program memory addresses are always word-alignedon the lower word, and addresses are incremented ordecremented by two during code execution. Thisarrangement also provides compatibility with datamemory space addressing and makes it possible toaccess data in the program memory space.3.1.2 HARD MEMORY VECTORSAll PIC24F devices reserve the addresses between00000h and 000200h for hard coded program executionvectors. A hardware Reset vector is provided toredirect code execution from the default value of thePC on device Reset to the actual start of code. A GOTOinstruction is programmed by the user at 000000h, withthe actual address for the start of code at 000002h.PIC24F devices also have two interrupt vector tables,located from 000004h to 0000FFh and 000100h to0001FFh. These vector tables allow each of the manydevice interrupt sources to be handled by separateISRs. A more detailed discussion of the interrupt vectortables is provided in Section 6.1 “Interrupt VectorTable”.3.1.3 FLASH CONFIGURATION WORDSIn PIC24FJ128GA010 family devices, the top twowords of on-chip program memory are reserved forconfiguration information. On device Reset, the configurationinformation is copied into the appropriateConfiguration registers. The addresses of the FlashConfiguration Word for devices in thePIC24FJ128GA010 family are shown in Table 3-1.Their location in the memory map is shown with theother memory vectors in Figure 3-1.The Configuration Words in program memory are acompact format. The actual Configuration bits aremapped in several different registers in the configurationmemory space. Their order in the Flash ConfigurationWords do not reflect a corresponding arrangement in theconfiguration space. Additional details on the deviceConfiguration Words are provided in Section 23.1“Configuration Bits”.TABLE 3-1:DeviceFLASH CONFIGURATIONWORDS FORPIC24FJ128GA010 FAMILYDEVICESProgramMemory(Words)ConfigurationWordAddressesPIC24FJ64GA 22,016 00ABFCh:00ABFEhPIC24FJ96GA 32,768 00FFFCh:00FFFEhPIC24FJ128GA 44,032 0157FCh:0157FEhFIGURE 3-2:PROGRAM MEMORY ORGANIZATIONmswAddressmost significant wordleast significant wordPC Address(lsw Address)000001h000003h000005h000007h00000000000000000000000000000000231680000000h000002h000004h000006hProgram Memory‘Phantom’ Byte(read as ‘0’)Instruction WidthDS39747E-page 28© 2009 Microchip Technology Inc.