pic24fj128ga010 family - Microchip

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PIC24FJ128GA010 FAMILY2.2 CPU Control RegistersREGISTER 2-1:SR: CPU STATUS REGISTERU-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0— — — — — — — DCbit 15 bit 8R/W-0 (1) R/W-0 (1) R/W-0 (1) R-0 R/W-0 R/W-0 R/W-0 R/W-0IPL2 (2) IPL1 (2) IPL0 (2) RA N OV Z Cbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-9 Unimplemented: Read as ‘0’bit 8DC: ALU Half Carry/Borrow bit1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)of the result occurred0 = No carry-out from the 4th or 8th low-order bit of the result has occurredbit 7-5 IPL2:IPL0: CPU Interrupt Priority Level Status bits (2)bit 4bit 3bit 2bit 1bit 0111 = CPU interrupt priority level is 7 (15). User interrupts disabled.110 = CPU interrupt priority level is 6 (14)101 = CPU interrupt priority level is 5 (13)100 = CPU interrupt priority level is 4 (12)011 = CPU interrupt priority level is 3 (11)010 = CPU interrupt priority level is 2 (10)001 = CPU interrupt priority level is 1 (9)000 = CPU interrupt priority level is 0 (8)RA: REPEAT Loop Active bit1 = REPEAT loop in progress0 = REPEAT loop not in progressN: ALU Negative bit1 = Result was negative0 = Result was non-negative (zero or positive)OV: ALU Overflow bit1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation0 = No overflow has occurredZ: ALU Zero bit1 = An operation which effects the Z bit has set it at some time in the past0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result)C: ALU Carry/Borrow bit1 = A carry-out from the Most Significant bit of the result occurred0 = No carry-out from the Most Significant bit of the result occurredNote 1: The IPL Status bits are read-only when NSTDIS (INTCON1) = 1.2: The IPL bits are concatenated with the IPL3 bit (CORCON) to form the CPU interrupt priority level.The value in parentheses indicates the IPL when IPL3 = 1.DS39747E-page 24© 2009 <strong>Microchip</strong> Technology Inc.
PIC24FJ128GA010 FAMILYREGISTER 2-2:CORCON: CORE CONTROL REGISTERU-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —bit 15 bit 8U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0— — — — IPL3 (1) PSV — —bit 7 bit 0Legend:C = Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-4 Unimplemented: Read as ‘0’bit 3 IPL3: CPU Interrupt Priority Level Status bit (1)1 = CPU interrupt priority level is greater than 70 = CPU interrupt priority level is 7 or lessbit 2PSV: Program Space Visibility in Data Space Enable bit1 = Program space visible in data space0 = Program space not visible in data spacebit 1-0 Unimplemented: Read as ‘0’Note 1: User interrupts are disabled when IPL3 = 1.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 25
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Page 8 and 9: PIC24FJ128GA010 FAMILYTO OUR VALUED
Page 10 and 11: PIC24FJ128GA010 FAMILY1.1.4 EASY MI
Page 12 and 13: PIC24FJ128GA010 FAMILYFIGURE 1-1:PI
Page 14 and 15: PIC24FJ128GA010 FAMILYTABLE 1-2:Fun
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Page 20 and 21: PIC24FJ128GA010 FAMILYNOTES:DS39747
Page 26 and 27: PIC24FJ128GA010 FAMILY2.3 Arithmeti
Page 28 and 29: PIC24FJ128GA010 FAMILY3.1.1 PROGRAM
Page 30 and 31: PIC24FJ128GA010 FAMILY3.2.2 DATA ME
Page 32 and 33: DS39747E-page 32 © 2009 Microchip
Page 42 and 43: PIC24FJ128GA010 FAMILY3.2.5 SOFTWAR
Page 44 and 45: PIC24FJ128GA010 FAMILY3.3.2 DATA AC
Page 48 and 49: PIC24FJ128GA010 FAMILY4.2 RTSP Oper
Page 54 and 55: PIC24FJ128GA010 FAMILYREGISTER 5-1:
Page 56 and 57: PIC24FJ128GA010 FAMILYTABLE 5-3:RES
Page 62 and 63: PIC24FJ128GA010 FAMILY6.3 Interrupt
Page 72 and 73: PIC24FJ128GA010 FAMILYREGISTER 6-11
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PIC24FJ128GA010 FAMILYREGISTER 6-13
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PIC24FJ128GA010 FAMILYNOTES:DS39747
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PIC24FJ128GA010 FAMILY7.1 CPU Clock
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PIC24FJ128GA010 FAMILYREGISTER 7-1:
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PIC24FJ128GA010 FAMILYREGISTER 7-3:
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PIC24FJ128GA010 FAMILYA recommended
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PIC24FJ128GA010 FAMILY8.2.2 IDLE MO
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PIC24FJ128GA010 FAMILY9.1.1 OPEN-DR
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PIC24FJ128GA010 FAMILYFIGURE 11-1:T
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PIC24FJ128GA010 FAMILY12.1 Input Ca
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PIC24FJ128GA010 FAMILYTo generate a
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PIC24FJ128GA010 FAMILYEXAMPLE 13-1:
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PIC24FJ128GA010 FAMILYTo set up the
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PIC24FJ128GA010 FAMILYFIGURE 14-3:S
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PIC24FJ128GA010 FAMILYEQUATION 14-1
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PIC24FJ128GA010 FAMILYFIGURE 15-1:I
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PIC24FJ128GA010 FAMILY16.1 UART Bau
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PIC24FJ128GA010 FAMILYFIGURE 17-2:
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PIC24FJ128GA010 FAMILYFIGURE 17-9:E
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PIC24FJ128GA010 FAMILY18.1 RTCC Mod
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PIC24FJ128GA010 FAMILY18.1.4 RTCVAL
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PIC24FJ128GA010 FAMILY18.1.5 ALRMVA
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PIC24FJ128GA010 FAMILY18.2 Calibrat
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PIC24FJ128GA010 FAMILYFIGURE 19-2:
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PIC24FJ128GA010 FAMILYFigure 20-1:1
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PIC24FJ128GA010 FAMILYEQUATION 20-1
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PIC24FJ128GA010 FAMILY23.3 Watchdog
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PIC24FJ128GA010 FAMILYTABLE 24-1:Fi
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PIC24FJ128GA010 FAMILYTABLE 24-2:IN
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PIC24FJ128GA010 FAMILYTABLE 24-2:As
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PIC24FJ128GA010 FAMILY25.2 MPLAB C
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PIC24FJ128GA010 FAMILY25.11 PICkit
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PIC24FJ128GA010 FAMILY26.1 DC Chara
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PIC24FJ128GA010 FAMILYTABLE 26-6:DC
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PIC24FJ128GA010 FAMILYTABLE 26-8:DC
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PIC24FJ128GA010 FAMILYTABLE 26-11:I
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PIC24FJ128GA010 FAMILYFIGURE 26-3:E
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PIC24FJ128GA010 FAMILYFIGURE 26-4:C
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PIC24FJ128GA010 FAMILYTABLE 26-20:
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PIC24FJ128GA010 FAMILY27.2 Package
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PIC24FJ128GA010 FAMILY100-Lead Plas
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PIC24FJ128GA010 FAMILYEElectrical C
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PIC24FJ128GA010 FAMILYSSelective Pe
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PIC24FJ128GA010 FAMILYREADER RESPON
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WORLDWIDE SALES AND SERVICEAMERICAS
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