pic24fj128ga010 family - Microchip
pic24fj128ga010 family - Microchip
pic24fj128ga010 family - Microchip
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PIC24FJ128GA010 FAMILY23.2 On-Chip Voltage RegulatorAll of the PIC24FJ128GA010 <strong>family</strong> devices powertheir core digital logic at a nominal 2.5V. This maycreate an issue for designs that are required to operateat a higher typical voltage, such as 3.3V. To simplifysystem design, all devices in the PIC24FJ128GA010incorporate an on-chip regulator that allows the deviceto run its core logic from VDD.The regulator is controlled by the ENVREG pin. TyingVDD to the pin enables the regulator, which in turn,provides power to the core from the other VDD pins.When the regulator is enabled, a low ESR capacitor(such as tantalum) must be connected to theVDDCORE/VCAP pin (Figure 23-1). This helps to maintainthe stability of the regulator. The recommendedvalue for the filer capacitor, CEFC, is provided inSection 26.1 “DC Characteristics”.If ENVREG is tied to VSS, the regulator is disabled. Inthis case, separate power for the core logic at a nominal2.5V must be supplied to the device on theVDDCORE/VCAP pin to run the I/O pins at higher voltagelevels, typically 3.3V. Alternatively, the VDDCORE/VCAPand VDD pins can be tied together to operate at a lowernominal voltage. Refer to Figure 23-1 for possibleconfigurations.23.2.1 ON-CHIP REGULATOR AND PORWhen the voltage regulator is enabled, it takes approximately20 μs for it to generate output. During this time,designated as TSTARTUP, code execution is disabled.TSTARTUP is applied every time the device resumesoperation after any power-down, including Sleep mode.If the regulator is disabled, a separate Power-up Timer(PWRT) is automatically enabled. The PWRT adds afixed delay of 64 ms nominal delay at device start-up.23.2.2 ON-CHIP REGULATOR AND BORWhen the on-chip regulator is enabled,PIC24FJ128GA010 devices also have a simplebrown-out capability. If the voltage supplied to the regulatoris inadequate to maintain a regulated level, theregulator Reset circuitry will generate a Brown-outReset. This event is captured by the BOR flag bit(RCON). The brown-out voltage specifications canbe found in the PIC24F Family Reference ManualReset chapter (DS39712).FIGURE 23-1:CONNECTIONS FOR THEON-CHIP REGULATORRegulator Enabled (ENVREG tied to VDD):3.3VPIC24FJ128GA010VDDENVREGVDDCORE/VCAPCEFCVSS(10 μF typ)Regulator Disabled (ENVREG tied to ground):2.5V (1) 3.3V (1)PIC24FJ128GA010VDDENVREGVDDCORE/VCAPVSSRegulator Disabled (VDD tied to VDDCORE):2.5V (1)PIC24FJ128GA010VDDENVREGVDDCORE/VCAPVSSNote 1: These are typical operating voltages. Referto Section 26.1 “DC Characteristics” forthe full operating ranges of VDD andVDDCORE.23.2.3 POWER-UP REQUIREMENTSThe on-chip regulator is designed to meet the power-uprequirements for the device. If the application does notuse the regulator, then strict power-up conditions mustbe adhered to. While powering up, VDDCORE mustnever exceed VDD by 0.3 volts.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 195