pic24fj128ga010 family - Microchip

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PIC24FJ128GA010 FAMILY18.2 CalibrationThe real-time crystal input can be calibrated using theperiodic auto-adjust feature. When properly calibrated,the RTCC can provide an error of less than 3 secondsper month. This is accomplished by finding the numberof error clock pulses and storing the value into thelower half of the RCFGCAL register. The 8-bit signedvalue loaded into the lower half of RCFGCAL is multipliedby four and will be either added or subtracted fromthe RTCC timer, once every minute. Refer to the stepsbelow for RTCC calibration:1. Using another timer resource on the device, theuser must find the error of the 32.768 kHzcrystal.2. Once the error is known, it must be converted tothe number of error clock pulses per minute.EQUATION 18-1:(Ideal Frequency † – Measured Frequency) * 60 = Clocks per Minute3. a) If the oscillator is faster then ideal (negativeresult form step 2), the RCFGCAL register valueneeds to be negative. This causes the specifiednumber of clock pulses to be subtracted fromthe timer counter once every minute.b) If the oscillator is slower then ideal (positiveresult from step 2), the RCFGCAL register valueneeds to be positive. This causes the specifiednumber of clock pulses to be subtracted fromthe timer counter once every minute.4. Divide the number of error clocks per minute by4 to get the correct CAL value and load theRCFGCAL register with the correct value. (Each1-bit increment in CAL adds or subtracts4 pulses). Load the RCFGCAL register with thecorrect value.Writes to the lower half of the RCFGCAL registershould only occur when the timer is turnedoff, or immediately after the rising edge of theseconds pulse.Note:† Ideal Frequency = 32,768 HzIt is up to the user to include in the errorvalue the initial error of the crystal, driftdue to temperature and drift due to crystalaging.18.3 Alarm• Configurable from half second to one year• Enabled using the ALRMEN bit(ALCFGRPT, Register 18-3)• One-time alarm and repeat alarm options available18.3.1 CONFIGURING THE ALARMThe alarm feature is enabled using the ALRMEN bit.This bit is cleared when an alarm is issued. Writes toALRMVALH:ALRMVALL should only take place whenALRMEN = 0.As shown in Figure 18-2, the interval selection of thealarm is configured through the AMASK bits(ALCFGRPT). These bits determine which andhow many digits of the alarm must match the clockvalue for the alarm to occur. The alarm can also be configuredto repeat based on a preconfigured interval.The amount of times this occurs once the alarm isenabled is stored in the lower half of the ALCFGRPTregister.When ALCFGRPT = 00 and the CHIME bit = 0(ALCFGRPT), the repeat function is disabled andonly a single alarm will occur. The alarm can berepeated up to 255 times by loading the lower half ofthe ALCFGRPT register with FFh.After each alarm is issued, the ALCFGRPT register isdecremented by one. Once the register has reached‘00’, the alarm will be issued one last time, after which,the ALRMEN bit will be cleared automatically and thealarm will turn off. Indefinite repetition of the alarm canoccur if the CHIME bit = 1. Instead of the alarm beingdisabled when the ALCFGRPT register reaches ‘00’, itwill roll over to FF and continue counting indefinitelywhen CHIME = 1.18.3.2 ALARM INTERRUPTAt every alarm event an interrupt is generated. In addition,an alarm pulse output is provided that operates athalf the frequency of the alarm. This output iscompletely synchronous to the RTCC clock and can beused as a trigger clock to other peripherals.Note:Changing any of the registers, other thenthe RCFGCAL and ALCFGRPT registersand the CHIME bit while the alarm isenabled (ALRMEN = 1), can result in afalse alarm event leading to a false alarminterrupt. To avoid a false alarm event, thetimer and alarm values should only bechanged while the alarm is disabled(ALRMEN = 0). It is recommended that theALCFGRPT register and CHIME bit bechanged when RTCSYNC = 0.DS39747E-page 166© 2009 <strong>Microchip</strong> Technology Inc.
PIC24FJ128GA010 FAMILYFIGURE 18-2:ALARM MASK SETTINGSAlarm Mask Setting(AMASK3:AMASK0)0000 – Every half second0001 – Every second0010 – Every 10 secondsDay oftheWeek Month Day Hours Minutes Secondss0011 – Every minutess0100 – Every 10 minutesm s s0101 – Every hourm m s s0110 – Every dayh h m m s s0111 – Every weekd h h m m s s1000 – Every monthd d h h m m s s1001 – Every year (1)m m d d h h m m s sNote 1: Annually, except when configured for February 29.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 167
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PIC24FJ128GA010 FAMILYDS39747E-page
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PIC24FJ128GA010 FAMILYDS39747E-page
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PIC24FJ128GA010 FAMILYTO OUR VALUED
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PIC24FJ128GA010 FAMILY1.1.4 EASY MI
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PIC24FJ128GA010 FAMILYFIGURE 1-1:PI
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PIC24FJ128GA010 FAMILYTABLE 1-2:Fun
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PIC24FJ128GA010 FAMILYTABLE 1-2:Fun
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PIC24FJ128GA010 FAMILYNOTES:DS39747
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PIC24FJ128GA010 FAMILY2.2 CPU Contr
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PIC24FJ128GA010 FAMILY2.3 Arithmeti
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PIC24FJ128GA010 FAMILY3.1.1 PROGRAM
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PIC24FJ128GA010 FAMILY3.2.2 DATA ME
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DS39747E-page 32 © 2009 Microchip
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PIC24FJ128GA010 FAMILY3.2.5 SOFTWAR
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PIC24FJ128GA010 FAMILY3.3.2 DATA AC
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PIC24FJ128GA010 FAMILY4.2 RTSP Oper
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PIC24FJ128GA010 FAMILYREGISTER 5-1:
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PIC24FJ128GA010 FAMILYTABLE 5-3:RES
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PIC24FJ128GA010 FAMILY6.3 Interrupt
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PIC24FJ128GA010 FAMILYREGISTER 6-11
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PIC24FJ128GA010 FAMILY7.1 CPU Clock
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PIC24FJ128GA010 FAMILYA recommended
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PIC24FJ128GA010 FAMILY8.2.2 IDLE MO
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PIC24FJ128GA010 FAMILY9.1.1 OPEN-DR
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PIC24FJ128GA010 FAMILYFIGURE 11-1:T
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PIC24FJ128GA010 FAMILY12.1 Input Ca
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Page 124 and 125: PIC24FJ128GA010 FAMILYREGISTER 14-1
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Page 130 and 131: PIC24FJ128GA010 FAMILYEQUATION 14-1
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Page 158 and 159: PIC24FJ128GA010 FAMILY18.1 RTCC Mod
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PIC24FJ128GA010 FAMILYTABLE 26-8:DC
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PIC24FJ128GA010 FAMILYTABLE 26-11:I
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PIC24FJ128GA010 FAMILYFIGURE 26-3:E
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PIC24FJ128GA010 FAMILYFIGURE 26-4:C
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PIC24FJ128GA010 FAMILYTABLE 26-20:
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PIC24FJ128GA010 FAMILY27.2 Package
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PIC24FJ128GA010 FAMILY100-Lead Plas
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PIC24FJ128GA010 FAMILYEElectrical C
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PIC24FJ128GA010 FAMILYSSelective Pe
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PIC24FJ128GA010 FAMILYREADER RESPON
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