pic24fj128ga010 family - Microchip

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PIC24FJ128GA010 FAMILYREGISTER 16-1:UxMODE: UARTx MODE REGISTERR/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0UARTEN — USIDL IREN (1) RTSMD — UEN1 UEN0bit 15 bit 8R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSELbit 7 bit 0Legend:HC = Hardware Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 UARTEN: UARTx Enable bit1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption minimalbit 14 Unimplemented: Read as ‘0’bit 13 USIDL: Stop in Idle Mode bit1 = Discontinue module operation when device enters Idle mode0 = Continue module operation in Idle modebit 12 IREN: IrDA Encoder and Decoder Enable bit (1)1 = IrDA encoder and decoder enabled0 = IrDA encoder and decoder disabledbit 11 RTSMD: Mode Selection for UxRTS Pin bit1 = UxRTS pin in Simplex mode0 = UxRTS pin in Flow Control modebit 10 Unimplemented: Read as ‘0’bit 9-8bit 7bit 6bit 5bit 4bit 3UEN1:UEN0: UARTx Enable bits11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin controlled by PORT latches10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by PORT latches00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins controlled by PORT latchesWAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge, bit cleared inhardware on following rising edge0 = No wake-up enabledLPBACK: UARTx Loopback Mode Select bit1 = Enable Loopback mode0 = Loopback mode is disabledABAUD: Auto-Baud Enable bit1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h);cleared in hardware upon completion0 = Baud rate measurement disabled or completedRXINV: Receive Polarity Inversion bit1 = UxRX Idle state is ‘0’0 = UxRX Idle state is ‘1’BRGH: High Baud Rate Enable bit1 = BRG generates 4 clocks per bit period (4x Baud Clock, High-Speed mode)0 = BRG generates 16 clocks per bit period (16x Baud Clock, Standard mode)Note 1: This feature is only available for the 16x BRG mode (BRGH = 0).DS39747E-page 142© 2009 <strong>Microchip</strong> Technology Inc.
PIC24FJ128GA010 FAMILYREGISTER 16-1:UxMODE: UARTx MODE REGISTER (CONTINUED)bit 2-1bit 0PDSEL1:PDSEL0: Parity and Data Selection bits11 = 9-bit data, no parity10 = 8-bit data, odd parity01 = 8-bit data, even parity00 = 8-bit data, no paritySTSEL: Stop Bit Selection bit1 = Two Stop bits0 = One Stop bitNote 1: This feature is only available for the 16x BRG mode (BRGH = 0).© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 143
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PIC24FJ128GA010 FAMILYDS39747E-page
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PIC24FJ128GA010 FAMILYDS39747E-page
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PIC24FJ128GA010 FAMILYTO OUR VALUED
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PIC24FJ128GA010 FAMILY1.1.4 EASY MI
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PIC24FJ128GA010 FAMILYFIGURE 1-1:PI
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PIC24FJ128GA010 FAMILYTABLE 1-2:Fun
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PIC24FJ128GA010 FAMILYTABLE 1-2:Fun
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PIC24FJ128GA010 FAMILYNOTES:DS39747
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PIC24FJ128GA010 FAMILY2.2 CPU Contr
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PIC24FJ128GA010 FAMILY2.3 Arithmeti
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PIC24FJ128GA010 FAMILY3.1.1 PROGRAM
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PIC24FJ128GA010 FAMILY3.2.2 DATA ME
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DS39747E-page 32 © 2009 Microchip
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PIC24FJ128GA010 FAMILY3.2.5 SOFTWAR
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PIC24FJ128GA010 FAMILY3.3.2 DATA AC
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PIC24FJ128GA010 FAMILY4.2 RTSP Oper
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PIC24FJ128GA010 FAMILYREGISTER 5-1:
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PIC24FJ128GA010 FAMILYTABLE 5-3:RES
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PIC24FJ128GA010 FAMILY6.3 Interrupt
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PIC24FJ128GA010 FAMILYREGISTER 6-11
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Page 92 and 93: PIC24FJ128GA010 FAMILYNOTES:DS39747
Page 94 and 95: PIC24FJ128GA010 FAMILY7.1 CPU Clock
Page 96 and 97: PIC24FJ128GA010 FAMILYREGISTER 7-1:
Page 98 and 99: PIC24FJ128GA010 FAMILYREGISTER 7-3:
Page 100 and 101: PIC24FJ128GA010 FAMILYA recommended
Page 102 and 103: PIC24FJ128GA010 FAMILY8.2.2 IDLE MO
Page 104 and 105: PIC24FJ128GA010 FAMILY9.1.1 OPEN-DR
Page 106 and 107: PIC24FJ128GA010 FAMILYREGISTER 10-1
Page 108 and 109: PIC24FJ128GA010 FAMILYFIGURE 11-1:T
Page 114 and 115: PIC24FJ128GA010 FAMILY12.1 Input Ca
Page 116 and 117: PIC24FJ128GA010 FAMILYTo generate a
Page 118 and 119: PIC24FJ128GA010 FAMILYEXAMPLE 13-1:
Page 122 and 123: PIC24FJ128GA010 FAMILYTo set up the
Page 128 and 129: PIC24FJ128GA010 FAMILYFIGURE 14-3:S
Page 130 and 131: PIC24FJ128GA010 FAMILYEQUATION 14-1
Page 132 and 133: PIC24FJ128GA010 FAMILYFIGURE 15-1:I
Page 140 and 141: PIC24FJ128GA010 FAMILY16.1 UART Bau
Page 154 and 155: PIC24FJ128GA010 FAMILYFIGURE 17-2:
Page 156 and 157: PIC24FJ128GA010 FAMILYFIGURE 17-9:E
Page 158 and 159: PIC24FJ128GA010 FAMILY18.1 RTCC Mod
Page 162 and 163: PIC24FJ128GA010 FAMILY18.1.4 RTCVAL
Page 164 and 165: PIC24FJ128GA010 FAMILY18.1.5 ALRMVA
Page 166 and 167: PIC24FJ128GA010 FAMILY18.2 Calibrat
Page 170 and 171: PIC24FJ128GA010 FAMILYFIGURE 19-2:
Page 174 and 175: PIC24FJ128GA010 FAMILYFigure 20-1:1
Page 180 and 181: PIC24FJ128GA010 FAMILYEQUATION 20-1
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PIC24FJ128GA010 FAMILY23.3 Watchdog
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PIC24FJ128GA010 FAMILYTABLE 24-1:Fi
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PIC24FJ128GA010 FAMILYTABLE 24-2:IN
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PIC24FJ128GA010 FAMILYTABLE 24-2:As
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PIC24FJ128GA010 FAMILY25.2 MPLAB C
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PIC24FJ128GA010 FAMILY25.11 PICkit
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PIC24FJ128GA010 FAMILY26.1 DC Chara
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PIC24FJ128GA010 FAMILYTABLE 26-6:DC
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PIC24FJ128GA010 FAMILYTABLE 26-8:DC
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PIC24FJ128GA010 FAMILYTABLE 26-11:I
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PIC24FJ128GA010 FAMILYFIGURE 26-3:E
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PIC24FJ128GA010 FAMILYFIGURE 26-4:C
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PIC24FJ128GA010 FAMILYTABLE 26-20:
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PIC24FJ128GA010 FAMILY27.2 Package
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PIC24FJ128GA010 FAMILY100-Lead Plas
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PIC24FJ128GA010 FAMILYEElectrical C
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PIC24FJ128GA010 FAMILYSSelective Pe
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PIC24FJ128GA010 FAMILYREADER RESPON
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WORLDWIDE SALES AND SERVICEAMERICAS
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