pic24fj128ga010 family - Microchip

PIC24FJ128GA010 FAMILYREGISTER 16-1:UxMODE: UARTx MODE REGISTERR/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0UARTEN — USIDL IREN (1) RTSMD — UEN1 UEN0bit 15 bit 8R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSELbit 7 bit 0Legend:HC = Hardware Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 UARTEN: UARTx Enable bit1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption minimalbit 14 Unimplemented: Read as ‘0’bit 13 USIDL: Stop in Idle Mode bit1 = Discontinue module operation when device enters Idle mode0 = Continue module operation in Idle modebit 12 IREN: IrDA Encoder and Decoder Enable bit (1)1 = IrDA encoder and decoder enabled0 = IrDA encoder and decoder disabledbit 11 RTSMD: Mode Selection for UxRTS Pin bit1 = UxRTS pin in Simplex mode0 = UxRTS pin in Flow Control modebit 10 Unimplemented: Read as ‘0’bit 9-8bit 7bit 6bit 5bit 4bit 3UEN1:UEN0: UARTx Enable bits11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin controlled by PORT latches10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by PORT latches00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins controlled by PORT latchesWAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge, bit cleared inhardware on following rising edge0 = No wake-up enabledLPBACK: UARTx Loopback Mode Select bit1 = Enable Loopback mode0 = Loopback mode is disabledABAUD: Auto-Baud Enable bit1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h);cleared in hardware upon completion0 = Baud rate measurement disabled or completedRXINV: Receive Polarity Inversion bit1 = UxRX Idle state is ‘0’0 = UxRX Idle state is ‘1’BRGH: High Baud Rate Enable bit1 = BRG generates 4 clocks per bit period (4x Baud Clock, High-Speed mode)0 = BRG generates 16 clocks per bit period (16x Baud Clock, Standard mode)Note 1: This feature is only available for the 16x BRG mode (BRGH = 0).DS39747E-page 142© 2009 Microchip Technology Inc.