pic24fj128ga010 family - Microchip

PIC24FJ128GA010 FAMILYREGISTER 15-1:I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)bit 5bit 4bit 3bit 2bit 1bit 0ACKDT: Acknowledge Data bit (When operating as I 2 C master. Applicable during master receive.)Value that will be transmitted when the software initiates an Acknowledge sequence.1 = Send NACK during Acknowledge0 = Send ACK during AcknowledgeACKEN: Acknowledge Sequence Enable bit(When operating as I 2 C master. Applicable during master receive.)1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardwareclear at end of master Acknowledge sequence.0 = Acknowledge sequence not in progressRCEN: Receive Enable bit (when operating as I 2 C master)1 = Enables Receive mode for I 2 C. Hardware clear at end of eighth bit of master receive data byte.0 = Receive sequence not in progressPEN: Stop Condition Enable bit (when operating as I 2 C master)1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.0 = Stop condition not in progressRSEN: Repeated Start Condition Enabled bit (when operating as I 2 C master)1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of masterRepeated Start sequence.0 = Repeated Start condition not in progressSEN: Start Condition Enabled bit (when operating as I 2 C master)1 = Initiate Start condition on SDA and SCL pins. Hardware clear at end of master Start sequence.0 = Start condition not in progress© 2009 Microchip Technology Inc. DS39747E-page 135