pic24fj128ga010 family - Microchip

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PIC24FJ128GA010 FAMILYEQUATION 14-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED (1)FSCK =FCYPrimary Prescaler * Secondary PrescalerNote 1:Based on FCY = FOSC/2, Doze mode and PLL are disabled.TABLE 14-1: SAMPLE SCK FREQUENCIES (1,2)FCY = 16 MHzSecondary Prescaler Settings1:1 2:1 4:1 6:1 8:1Primary Prescaler Settings 1:1 Invalid 8000 4000 2667 20004:1 4000 2000 1000 667 50016:1 1000 500 250 167 12564:1 250 125 63 42 31FCY = 5 MHzPrimary Prescaler Settings 1:1 5000 2500 1250 833 6254:1 1250 625 313 208 15616:1 313 156 78 52 3964:1 78 39 20 13 10Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.2: SCKx frequencies shown in kHz.DS39747E-page 130© 2009 <strong>Microchip</strong> Technology Inc.
PIC24FJ128GA010 FAMILY15.0 INTER-INTEGRATED CIRCUIT(I 2 C)Note:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 24. “Inter-Integrated Circuit (I 2 C)” (DS39702)in the “PIC24F Family Reference Manual”for more information.The Inter-Integrated Circuit (I 2 C) module is a serialinterface useful for communicating with other peripheralor microcontroller devices. These peripheraldevices may be serial EEPROMs, display drivers, A/DConverters, etc.The I 2 C module supports these features:• Independent master and slave logic• 7-bit and 10-bit device addresses• General call address, as defined in the I 2 C protocol• Clock stretching to provide delays for theprocessor to respond to a slave data request• Both 100 kHz and 400 kHz bus specifications.• Configurable address masking• Multi-Master modes to prevent loss of messagesin arbitration• Bus Repeater mode, allowing the acceptance ofall messages as a slave regardless of the address• Automatic SCLA block diagram of the module is shown in Figure 15-1.15.1 Communicating as a Master in aSingle Master EnvironmentThe details of sending a message in Master modedepends on the communications protocol for the devicebeing communicated with. Typically, the sequence ofevents is as follows:1. Assert a Start condition on SDAx and SCLx.2. Send the I 2 C device address byte to the slavewith a write indication.3. Wait for and verify an Acknowledge from theslave.4. Send the first data byte (sometimes known asthe command) to the slave.5. Wait for and verify an Acknowledge from theslave.6. Send the serial memory address low byte to theslave.7. Repeat steps 4 and 5 until all data bytes aresent.8. Assert a Repeated Start condition on SDAx andSCLx.9. Send the device address byte to the slave witha read indication.10. Wait for and verify an Acknowledge from theslave.11. Enable master reception to receive serialmemory data.12. Generate an ACK or NACK condition at the endof a received byte of data.13. Generate a Stop condition on SDAx and SCLx.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 131
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PIC24FJ128GA010 FAMILYDS39747E-page
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PIC24FJ128GA010 FAMILYDS39747E-page
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PIC24FJ128GA010 FAMILYTO OUR VALUED
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PIC24FJ128GA010 FAMILY1.1.4 EASY MI
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PIC24FJ128GA010 FAMILYFIGURE 1-1:PI
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PIC24FJ128GA010 FAMILYTABLE 1-2:Fun
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PIC24FJ128GA010 FAMILYTABLE 1-2:Fun
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PIC24FJ128GA010 FAMILYNOTES:DS39747
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PIC24FJ128GA010 FAMILY2.2 CPU Contr
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PIC24FJ128GA010 FAMILY2.3 Arithmeti
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PIC24FJ128GA010 FAMILY3.1.1 PROGRAM
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PIC24FJ128GA010 FAMILY3.2.2 DATA ME
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DS39747E-page 32 © 2009 Microchip
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PIC24FJ128GA010 FAMILY3.2.5 SOFTWAR
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PIC24FJ128GA010 FAMILY3.3.2 DATA AC
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PIC24FJ128GA010 FAMILY4.2 RTSP Oper
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PIC24FJ128GA010 FAMILYREGISTER 5-1:
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PIC24FJ128GA010 FAMILYTABLE 5-3:RES
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PIC24FJ128GA010 FAMILY6.3 Interrupt
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PIC24FJ128GA010 FAMILYREGISTER 6-11
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Page 80 and 81: PIC24FJ128GA010 FAMILYREGISTER 6-19
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Page 102 and 103: PIC24FJ128GA010 FAMILY8.2.2 IDLE MO
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Page 108 and 109: PIC24FJ128GA010 FAMILYFIGURE 11-1:T
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Page 116 and 117: PIC24FJ128GA010 FAMILYTo generate a
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Page 122 and 123: PIC24FJ128GA010 FAMILYTo set up the
Page 128 and 129: PIC24FJ128GA010 FAMILYFIGURE 14-3:S
Page 132 and 133: PIC24FJ128GA010 FAMILYFIGURE 15-1:I
Page 140 and 141: PIC24FJ128GA010 FAMILY16.1 UART Bau
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Page 156 and 157: PIC24FJ128GA010 FAMILYFIGURE 17-9:E
Page 158 and 159: PIC24FJ128GA010 FAMILY18.1 RTCC Mod
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Page 164 and 165: PIC24FJ128GA010 FAMILY18.1.5 ALRMVA
Page 166 and 167: PIC24FJ128GA010 FAMILY18.2 Calibrat
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Page 174 and 175: PIC24FJ128GA010 FAMILYFigure 20-1:1
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PIC24FJ128GA010 FAMILYEQUATION 20-1
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PIC24FJ128GA010 FAMILY23.3 Watchdog
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PIC24FJ128GA010 FAMILYTABLE 24-1:Fi
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PIC24FJ128GA010 FAMILYTABLE 24-2:IN
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PIC24FJ128GA010 FAMILYTABLE 24-2:As
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PIC24FJ128GA010 FAMILY25.2 MPLAB C
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PIC24FJ128GA010 FAMILY25.11 PICkit
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PIC24FJ128GA010 FAMILY26.1 DC Chara
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PIC24FJ128GA010 FAMILYTABLE 26-6:DC
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PIC24FJ128GA010 FAMILYTABLE 26-8:DC
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PIC24FJ128GA010 FAMILYTABLE 26-11:I
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PIC24FJ128GA010 FAMILYFIGURE 26-3:E
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PIC24FJ128GA010 FAMILYFIGURE 26-4:C
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PIC24FJ128GA010 FAMILYTABLE 26-20:
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PIC24FJ128GA010 FAMILY27.2 Package
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PIC24FJ128GA010 FAMILY100-Lead Plas
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PIC24FJ128GA010 FAMILYEElectrical C
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PIC24FJ128GA010 FAMILYSSelective Pe
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PIC24FJ128GA010 FAMILYREADER RESPON
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WORLDWIDE SALES AND SERVICEAMERICAS
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