pic24fj128ga010 family - Microchip

PIC24FJ128GA010 FAMILYFIGURE 14-3:SPI MASTER/SLAVE CONNECTION (STANDARD MODE)PROCESSOR 1 (SPI Master)PROCESSOR 2 (SPI Slave)SDOxSDIxSerial Receive Buffer(SPIxRXB)Serial Receive Buffer(SPIxRXB)Shift Register(SPIxSR)MSbLSbSDIxSDOxMSbShift Register(SPIxSR)LSbSerial Transmit Buffer(SPIxTXB)Serial Transmit Buffer(SPIxTXB)SPIx Buffer(SPIxBUF)SCKxSerial ClockSCKxSPIx Buffer(SPIxBUF)SSx(MSTEN (SPIxCON1 = 1))(SSEN (SPIxCON1) = 1 and MSTEN (SPIxCON1) = 0)Note 1: Using the SSx pin in the Slave mode of operation is optional.2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memorymapped to SPIxBUF.FIGURE 14-4:SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)PROCESSOR 1 (SPI Enhanced Buffer Master)SDOxPROCESSOR 2 (SPI Enhanced Buffer Slave)SDIxShift Register(SPIxSR)SDIxSDOxShift Register(SPIxSR)MSbLSbMSbLSb8-Level FIFO Buffer8-Level FIFO BufferSPIx Buffer(SPIxBUF)SCKxSerial ClockSCKxSPIx Buffer(SPIxBUF)SSxSSxMSTEN (SPIxCON1 = 1 andSPIBEN (SPIxCON2) = 1SSEN (SPIxCON1) = 1 andMSTEN (SPIxCON1) = 0 andSPIBEN (SPIxCON2) = 1Note 1: Using the SSx pin in Slave mode of operation is optional.2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memorymapped to SPIxBUF.DS39747E-page 128© 2009 Microchip Technology Inc.