pic24fj128ga010 family - Microchip

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PIC24FJ128GA010 FAMILYTo set up the SPI module for the Enhanced BufferMaster mode of operation:1. If using interrupts:a) Clear the SPIxIF bit in the respective IFSxregister.b) Set the SPIxIE bit in the respective IECxregister.c) Write the SPIxIP bits in the respective IPCxregister.2. Write the desired settings to the SPIxCON1 andSPIxCON2 registers with MSTEN(SPIxCON1) = 1.3. Clear the SPIROV bit (SPIxSTAT).4. Select Enhanced Buffer mode by setting theSPIBEN bit (SPIxCON2).5. Enable SPI operation by setting the SPIEN bit(SPIxSTAT).6. Write the data to be transmitted to the SPIxBUFregister. Transmission (and reception) will startas soon as data is written to the SPIxBUFregister.To set up the SPI module for the Enhanced BufferSlave mode of operation:1. Clear the SPIxBUF register.2. If using interrupts:• Clear the SPIxIF bit in the respective IFSxregister.• Set the SPIxIE bit in the respective IECxregister.• Write the SPIxIP bits in the respective IPCxregister to set the interrupt priority.3. Write the desired settings to the SPIxCON1 andSPIxCON2 registers with MSTEN(SPIxCON1) = 0.4. Clear the SMP bit.5. If the CKE bit is set, then the SSEN bit must beset, thus enabling the SSx pin.6. Clear the SPIROV bit (SPIxSTAT).7. Select Enhanced Buffer mode by setting theSPIBEN bit (SPIxCON2).8. Enable SPI operation by setting the SPIEN bit(SPIxSTAT).FIGURE 14-1:SPIx MODULE BLOCK DIAGRAM (STANDARD MODE)SCKx1:1 to 1:8SecondaryPrescaler1:1/4/16/64PrimaryPrescalerFCYSSx/FSYNCxSyncControlControlClockSelectEdgeSPIxCON1SDOxShift ControlSPIxCON1SDIxbit 0SPIxSREnableMaster ClockTransferTransferSPIxBUFRead SPIxBUFWrite SPIxBUF16Internal Data BusDS39747E-page 122© 2009 <strong>Microchip</strong> Technology Inc.
PIC24FJ128GA010 FAMILYFIGURE 14-2:SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)SCKxSSx/FSYNCxSyncControlControlClockSelectEdge1:1 to 1:8SecondaryPrescaler1:1/4/16/64PrimaryPrescalerFCYSPIxCON1SDOxShift ControlSPIxCON1SDIxbit0SPIxSREnableMaster ClockTransferTransfer8-Level FIFOReceive Buffer8-Level FIFOTransmit BufferSPIxBUFRead SPIxBUFWrite SPIxBUF16Internal Data Bus© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 123
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PIC24FJ128GA010 FAMILYDS39747E-page
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PIC24FJ128GA010 FAMILYDS39747E-page
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PIC24FJ128GA010 FAMILYTO OUR VALUED
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PIC24FJ128GA010 FAMILY1.1.4 EASY MI
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PIC24FJ128GA010 FAMILYFIGURE 1-1:PI
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PIC24FJ128GA010 FAMILYTABLE 1-2:Fun
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PIC24FJ128GA010 FAMILYTABLE 1-2:Fun
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PIC24FJ128GA010 FAMILYNOTES:DS39747
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PIC24FJ128GA010 FAMILY2.2 CPU Contr
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PIC24FJ128GA010 FAMILY2.3 Arithmeti
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PIC24FJ128GA010 FAMILY3.1.1 PROGRAM
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PIC24FJ128GA010 FAMILY3.2.2 DATA ME
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DS39747E-page 32 © 2009 Microchip
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PIC24FJ128GA010 FAMILY3.2.5 SOFTWAR
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PIC24FJ128GA010 FAMILY3.3.2 DATA AC
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PIC24FJ128GA010 FAMILY4.2 RTSP Oper
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PIC24FJ128GA010 FAMILYREGISTER 5-1:
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PIC24FJ128GA010 FAMILYTABLE 5-3:RES
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PIC24FJ128GA010 FAMILY6.3 Interrupt
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PIC24FJ128GA010 FAMILYFigure 20-1:1
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PIC24FJ128GA010 FAMILYREGISTER 20-2
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PIC24FJ128GA010 FAMILYEQUATION 20-1
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PIC24FJ128GA010 FAMILY23.3 Watchdog
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PIC24FJ128GA010 FAMILYTABLE 24-1:Fi
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PIC24FJ128GA010 FAMILYTABLE 24-2:IN
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PIC24FJ128GA010 FAMILYTABLE 24-2:As
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PIC24FJ128GA010 FAMILY25.2 MPLAB C
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PIC24FJ128GA010 FAMILY25.11 PICkit
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PIC24FJ128GA010 FAMILY26.1 DC Chara
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PIC24FJ128GA010 FAMILYTABLE 26-6:DC
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PIC24FJ128GA010 FAMILYTABLE 26-8:DC
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PIC24FJ128GA010 FAMILYTABLE 26-11:I
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PIC24FJ128GA010 FAMILYFIGURE 26-3:E
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PIC24FJ128GA010 FAMILYFIGURE 26-4:C
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PIC24FJ128GA010 FAMILYTABLE 26-20:
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PIC24FJ128GA010 FAMILY27.2 Package
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PIC24FJ128GA010 FAMILY100-Lead Plas
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PIC24FJ128GA010 FAMILYEElectrical C
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PIC24FJ128GA010 FAMILYSSelective Pe
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PIC24FJ128GA010 FAMILYREADER RESPON
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WORLDWIDE SALES AND SERVICEAMERICAS
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pic24fj128ga010 family - Microchip

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