pic24fj128ga010 family - Microchip

PIC24FJ128GA010 FAMILY12.0 INPUT CAPTURENote:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 15. “Input Capture”(DS39701) in the “PIC24F FamilyReference Manual” for more information.The input capture module has multiple operatingmodes which are selected via the ICxCON register.The operating modes include:• Capture timer value on every falling edge of inputapplied at the ICx pin• Capture timer value on every rising edge of inputapplied at the ICx pin• Capture timer value on every fourth rising edge ofinput applied at the ICx pin• Capture timer value on every 16th rising edge ofinput applied at the ICx pin• Capture timer value on every rising and everyfalling edge of input applied at the ICx pin• Device wake-up from capture pin during CPUSleep and Idle modesThe input capture module has a four-level FIFO buffer.The number of capture events required to generate aCPU interrupt can be selected by the user.FIGURE 12-1:INPUT CAPTURE BLOCK DIAGRAMFrom 16-Bit TimersTMRyTMRx16 16ICx pinPrescalerCounter(1, 4, 16)3ICM (ICxCON)Mode SelectICxCONEdge Detection LogicandClock SynchronizerICOV, ICBNE (ICxCON)ICIInterruptLogicFIFOR/WLogic1 0ICxBUFICTMR(ICxCON)FIFOSystem BusSet Flag ICxIF(in IFSx Register)Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.© 2009 Microchip Technology Inc. DS39747E-page 113