pic24fj128ga010 family - Microchip

PIC24FJ128GA010 FAMILY9.0 I/O PORTSNote:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 12. “I/O Portswith Peripheral Pin Select (PPS)”(DS39711) in the “PIC24F FamilyReference Manual” for more information.All of the device pins (except VDD, VSS, MCLR andOSC1/CLKI) are shared between the peripherals andthe parallel I/O ports. All I/O input ports feature SchmittTrigger inputs for improved noise immunity.9.1 Parallel I/O (PIO) PortsA parallel I/O port that shares a pin with a peripheral is,in general, subservient to the peripheral. The peripheral’soutput buffer data and control signals areprovided to a pair of multiplexers. The multiplexersselect whether the peripheral or the associated porthas ownership of the output data and control signals ofthe I/O pin. The logic also prevents “loop through”, inwhich a port’s digital output can drive the input of aperipheral that shares the same pin. Figure 9-1 showshow ports are shared with other peripherals and theassociated I/O pin to which they are connected.When a peripheral is enabled and the peripheral isactively driving an associated pin, the use of the pin asa general purpose output pin is disabled. The I/O pinmay be read, but the output driver for the parallel portbit will be disabled. If a peripheral is enabled, but theperipheral is not actively driving a pin, that pin may bedriven by a port.All port pins have three registers directly associatedwith their operation as digital I/O. The data directionregister (TRISx) determines whether the pin is an inputor an output. If the data direction bit is a ‘1’, then the pinis an input. All port pins are defined as inputs after aReset. Reads from the latch (LATx), read the latch.Writes to the latch, write the latch. Reads from the port(PORTx), read the port pins, while writes to the portpins, write the latch.Any bit and its associated data and control registersthat are not valid for a particular device will bedisabled. That means the corresponding LATx andTRISx registers and the port pin will read as zeros.When a pin is shared with another peripheral or functionthat is defined as an input only, it is neverthelessregarded as a dedicated port because there is noother competing source of outputs. An example is theINT4 pin.FIGURE 9-1:BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTUREPeripheral ModulePeripheral Input DataOutput MultiplexersPeripheral Module EnablePeripheral Output EnablePeripheral Output Data10Output EnableI/ORead TRISPIO Module10Output DataData BusDQI/O PinWR TRISCKTRIS LatchDQWR LAT +WR PORTCKData LatchRead LATInput DataRead PORT© 2009 Microchip Technology Inc. DS39747E-page 103