Pulse Width Modulator (PWM) - Cadence - Cadence Design Systems

Pulse Width Modulator (PWM)Technical Data SheetTechnical Data SheetPart Number:T-CS-PE-0006-100Document Number: I-IPA01-0048-USR Rev 08February 2008i

PWM Technical Data SheetPulse Width Modulator (PWM)1. Features• Uses AMBA APB protocol, version 2.0• Programmable module• Programmable interrupt• Generic design suitable for any technology• Parameterizable address and module ID• Single clock domain, single edge design• Operates at a nominal speed of 133 MHz• Generates a regular rectangular wave of definable period and duty cycle• Limits of programmability:• PWM signal cycle period:- 2 to 4294967294 system clock cycles• PWM signal high period:- 1 to 4294967293 system clock cycles2. DescriptionThe Pulse Width Modulator (PWM) is a substantially generic design that can be targeted tovirtually any technology. The generic nature of its design enables the processor to programthe PWM to produce a signal whose period and duty cycle can vary during operation.The Period register controls the period, and a high output loaded into the Hightime registercontrols the number of cycles. The Control register is loaded with a one bit start/stop value,while the Interrupt Control register enables and disables interrupts. This enables the PWM torun indefinitely until the Control register is loaded with a stop value. The processorcommunicates this information to the PWM through the AMBA APB interface.The Module ID register is read-only.3. Operationpwm_logicPWM DesignControlPeriodPeriodCounterAPBInterfacePWMInterfaceHightimeHightimeCounterLogicPWM Outputpwm_outputInterruptControlInterrupt OutPWM Registersinterrupt_out(pwm_int)Document No: I-IPA01-0048-USR Rev 08, February 2008© 2001 Cadence Design Systems, Inc. Page 1

PWM Technical Data SheetThe Period register is loaded with the desired PWM period, expressed in terms of systemclock cycles. The Hightime register is loaded with the number of system clock cycles forwhich the PWM cycle is to be high. The Control register has a start/stop bit which must beloaded to generate the PWM cycle. All registers are accessed through the AMBA APBinterface. To stop the PWM cycle, the Control register must be loaded with a stop value.Subsequent writes to the Period and Hightime registers take place at the end of the currentperiod.Interrupts are enabled by writing to the Interrupt Enable address, and disabled by writing tothe Interrupt Disable address. Bit [0] of the data bus should be set high to enable or disableinterrupts. All other bits are reserved and should be set low.The PWM asserts the pwm_int signal at the end of the desired period if the interrupts areenabled. The output remains high until the Interrupt Status register is read and cleared, atwhich point the output is de-asserted. Writing to the Interrupt Disable register prevents thegeneration of new interrupts without affecting any interrupts that have already beenasserted.4. Signal Interfacespclkn_p_resetpenablepselpwritepwdata[31:00]paddr[03:00]PWMprdata[31:00]pwm_outputpwm_intThe PWM incorporates a specific timing and control signal interfaces, and an AMBAAdvanced Peripheral Bus (APB) slave interface.4.1. PWM InterfaceSignal Name I/O Functionpwm_output O PWM output signalpwm_int O PWM interrupt signal4.2. AMBA APB Slave InterfaceSignal Name I/O Functionpclk I APB clock optionally may be derived from AHB hclkn_p_reset I APB reset (active low)psel I APB selectpenable I APB enableDocument No: I-IPA01-0048-USR Rev 08, February 2008© 2001 Cadence Design Systems, Inc. Page 2

PWM Technical Data Sheetpwrite I APB read/write strobepaddr [03:00] I APB address bus (only some LSBs used)pwdata [31:00] I APB write dataprdata [31:00] OAPB read data4.3. APB Timing CharacteristicsThe following characteristic have been set as the default values for the synthesis of themodule.Parameter Description Min Max UnitTclk Clock period 7.5 DC nsTclkh Clock high 40% - pclkTclkl Clock low 40% - pclkTih Input hold after pclk 0.1 - nsTis Input setup before pclk 30% - pclkToh Output hold after pclk 0.1 - nsTos Output setup before pclk - 30% pclkThese APB timings are specified relative to the target clock period, Tclk, and are coded intothe synthesis script provided. These timings have been achieved with a typical technology,but are for guidance only. There is a practical maximum clock period, which depends onsystem usage requirements and would be the required increment in PWM Period andHightime.5. Programming InterfaceThe following control and status registers are present in the PWM module.5.1. Register MapOffsetMnemonicAccessResetValueDescription0x0000 CR RW 0x0 Control Register0x0004 PR RW 0x0 Period Register0x0008 HR RW 0x0 Hightime Register0x000C ID RO — Module ID Register0x0010 EI WO 0x0 Enable InterruptDocument No: I-IPA01-0048-USR Rev 08, February 2008© 2001 Cadence Design Systems, Inc. Page 3

PWM Technical Data Sheet0x0014 DI WO 0x0 Disable Interrupt0x0018 RI RO 0x0 Read Interrupt Enable Value0x001C IS RC — Read Interrupt Status6. Physical EstimatesGate count 2000FF count 142SOC-Internal pins (in) 44SOC-Internal pins (out) 34SOC-External pins (in) 0SOC-External pins (out) 17. VerificationAll our IP modules are verified to one of the following levels:• Gold IP has been to target silicon.• Silver P has been to silicon in FPGA.• Bronze IP has been verified in simulation with logical timing closure.• In development IP has not yet been verified.Please contact the IPGallery (ipgallery@cadence.com) for the latest verificationinformation.8. DeliverablesThe full IP package comes complete with:• Verilog HDL• Cadence RC synthesis scripts• Verilog testbench• PWM User’s Guide with full programming interface, parameterization instructionsand synthesis instructions.Document No: I-IPA01-0048-USR Rev 08, February 2008© 2001 Cadence Design Systems, Inc. Page 4