Intel talk on Interconnect power - UCSD VLSI CAD Laboratory

14/2/2004 1Interconnect-Power Dissipationin a MicroprocessorN. Magen, A. Kolodny, U. Weiser, N. Shamir<strong>Intel</strong> corporation®Technion - Israel Institute of Technology

14/2/2004 2Interconnect-Power Definition• Interconnect-Power is dynamic power consumptiondue to interconnect capacitance switching– How much power is consumed by Interconnections ?– Future generations trends ?– How to reduce the interconnect power ?0.13 µm cross-section, source - <strong>Intel</strong>

14/2/2004 4Outline• Research methodology• Interconnect Power Analysis• Power-Aware Router Experiment• Interconnect Power Prediction• Summary

14/2/2004 5Case study• Low-power, state-of-the-art µ-processor• Dynamic switching power analysis• Interconnect attributes:‣ Length‣ Capacitance‣ Fan Out (FO)‣ Hierarchy data‣ Net type‣ Activity factors (AF)‣ Miscellaneous.

14/2/2004 6Interconnect Length Model1• Total wire length• Stitched across hierarchies• Summed over repeaters864 41377• Net modelCdiff.CwireCgate

14/2/2004 7Activity Factors GenerationPower test vectors generation(worst case for high power, unit stressing)RTL full-chip simulation(results in blocks primary inputs: Activity,Probability)Monte-Carlo based block inputs generation(based on the RTL statistics)Transistor level simulation - per block(Unit delay, tuning for glitches)Per node activity factorSource -”<strong>Intel</strong>® Pentium® M Processor Power Estimation, Budgeting, Optimization, and Validation”, ITJ 2003

14/2/2004 8Outline• Research methodology• Interconnect Power Analysis• Power-Aware Router Experiment• Interconnect Power Prediction• Summary

14/2/2004 9Interconnect Length Distribution100001000100Number of nets1010.10.01Pentium® 0.5 [um]Pentium® MMX 0.35 [um]Pentium® Pro 0.5 [um]Pentium® II 0.35 [um]Pentium® II 0.25 [um]Pentium® III 0.18 [um]Low Power Processor 0.13 [um]0.0011 10 100 1000 10000 100000Net Length [um]Source: Shekhar Y. Borkar, CRL - <strong>Intel</strong>

14/2/2004 10Interconnect Length DistributionNets vs. Net Length• Log – Logscale• Exponentialdecrease withlength• Global clock –not includedNumber of Nets10001001010.1LocalGlobal TotalTotal0.010.0011 10 100 1000 10000 100000Length [um]

14/2/2004 11Total Dynamic Power• Total DynamicPower• Global clock –not included• Localnets = 66%• Globalnets = 34%Normalized Dynamic Power1009080706050403020Nets: 390kCap: 10[nF]FO: 2AF: 0.0485Total Power vs. Net LengthPeak 1Peak 2InterconnectLocalGlobal TotalTotal TotalNets: 75kCap: 20[nF]FO: 20AF: 0.0551001 10 100 1000 10000 100000Length [um]

14/2/2004 12Total Dynamic Power BreakdownGlobal clock includedInterconnect51%Gate34%Diffusion15%

14/2/2004 13Power Breakdown by Net TypesGlobal clock includedglobalsignals34%global clock19%local signals27%local clock20%globalsignals21%global clock13%local clock29%local signals37%Interconnect power(Interconnect only)Total power(Gate, Diffusion and Interconnect)

14/2/2004 14Interconnect Power Breakdown• Interconnect consumes 50% of dynamic power• Clock power ~40% (of Interconnect and total)• 90% of power consumed by 10% of nets• Interconnect design is NOT power-aware !• Predictive model can project the interconnect power.Interconnect power Total power100 %global signals90 %80 %34 %global clockLocal signalslocal clock70 %60 %50 %40 %30 %19 %27 %Interconnect51%Gate34%Local local signals clock20 %10 %20 %Diffusion15%0%

14/2/2004 15Outline• Research methodology• Interconnect Power Analysis• Power-Aware Router Experiment• Interconnect Power Prediction• Summary

14/2/2004 16Experiment - Power-Aware Router• Routing Experiment optimizing processor’s blocks• Local nodes (clock and signals) consume 66% of dynamic power• 10% of nets consume 90% of power• Min. spanning trees can save over 20% Interconnect power• Routing with spacing can save up to 40% Interconnect powerSmall block’s local clock network

14/2/2004 17Power-Aware Router FlowPower grid routingClock tree:high FO, long lines, very activeClock tree routingWith spacingAvoiding congestionTop n% power consumingsignal nets routingGlobal and Detailed Routing -of the un-routed nets(timing and congestion driven)Rip-up: not high power netsAll netsrouted?NoPower-aware Rip upand re-routeYesFollowed by downsizingFinish

14/2/2004 18Results - Power SavingAverageDynamic power saving60%Driver Downsizing50%Router Power Saving40%30%Downsize20%saving10%Router0%savingBlock A Block B Block C Block D Block EAverage saving results: 14.3% for ASIC blocks 11 - Estimated based on clock interconnect power

14/2/2004 19Outline• Research methodology• Interconnect Power Analysis• Power-Aware Router Experiment• Interconnect Power Prediction• Summary

14/2/2004 20Future of Interconnect Power100%Dynamic Power breakdownGate90%80%Diffusion70%60%50%Interconnect40%30%20%10%% G POW% D POW% IC POWSource - ITRS 2001 Edition adapted data0%0.15 0.13 0.1 0.09 0.08 0.07 0.065 0.045 0.032 0.022GenerationTechnology generation [µm]Interconnect power grows to 65%-80% within 5 years !(using optimistic interconnect scaling)

14/2/2004 21Interconnect Power Prediction• The number of netsvs. unit length –Modified Davis modelNumber of Number Nets of (normalized)1001010.10.010.10 .0010 .0000110.010 .00010.001 0100 %Interconnect length projectionUpper local boundLower global boundPowerMeasured1 10 100 1000 10000 100000Length [ um ]Dynamic power breakdownmodel• The dynamic poweraverage breakdownPowerPower90 %80 %70 %60 %50 %40 %30 %InterconnectDiffusionInterconnectDiffGate20 %10 %Gate0%Local Intermediate Global

14/2/2004 22Interconnect Power Model• Multiplication of the number of interconnects with powerbreakdowns gives:6Projected dynamic power vs. net lengthPower (normalized)Power54321Measured powerProjection01 10 100 1000 10000 100000Length [µm][ um ]The power model matches processor power distribution !

14/2/2004 23Outline• Research methodology• Interconnect Power Analysis• Power-Aware Router Experiment• Interconnect Power Prediction• Summary

14/2/2004 24Summary• Interconnect is 50% of the dynamic power of processors, andgetting worse.► Interconnect power-aware design is recommended• Clock consumes 40% of interconnect power.► Clock interconnect spacing is suggested• Interconnect power is sum of nearly all net lengths and types.► Router level Interconnect power reduction addresses all• Interconnect power has strong dependency on the hierarchy►Per Hierarchy analysis and optimization algorithms

14/2/2004 25Future Research1. Interconnect Power characterization and prediction2. Investigate Interconnect power reduction techniques:• Interconnect-Spacing for power• Interconnect Power-Aware physical design• Aspect Ratio optimization for power• Architectural communication reduction

14/2/2004 26Questions ?

14/2/2004 27BACKUP-Slides

14/2/2004 28Processor Case Study• Analysis subject: Processor, 0.13 [µm]• 77 million transistors, die size of 88 [mm 2 ]• Data sources (AF, Capacitance, Length)• Excluded: L2 cache, global clock, analog units

14/2/2004 29Global Communication• Global power isimportant• Global power ismostly IC• For higher powerbenchmarks –Global power ishigher• G-clock excludedGlobal Power Percent35%30%25%20%15%10%%GlobalGlobal Power % vs. Test PowerPoly. (%Global )5%0%Total Power [uW]

14/2/2004 30Benchmark Selection• High power test benchmarks• Worst case design• Suitable for: thermal design, power grid design• Average power is a fraction of peak power• Unit stressing benchmarks• Averaging of all high power benchmarks• High node coverageITC logo

14/2/2004 31Interconnect Power Implications• Interconnect power can be reduced byminimizing switched capacitance:• Fabrication process (wire parameters)• Power-driven physical design• Logic optimization for power• Architectural interconnect optimization

14/2/2004 32Interconnect Capacitance• Side-cap is increasing:70% to 80%self-cap.Layer 3100%90%80%70%60%Global Capacitance breakdownV-cap50%H-capH-capV-capLayer 2Side-cap.40%30%20%V-capH-capSource - ITRS 2001 Edition adapted dataLayer 110%0%0.15 0.13 0.1 0.09 0.08 0.07 0.065 0.045 0.032 0.022GenerationTechnology generation [µm]The majority of interconnect capacitance is side-capacitance !

14/2/2004 33Fabrication Process –Aspect Ratio (AR)• Interconnect AR =ThicknessWidthThickness• Low AR = Low Interconnect power• Low AR = High resistance• Frequency Modeling• Local: average gate, average IC• Global: optimally buffered global ICWidthLocalR intR intR intR int R intR intR int...C intC intC intC int C intC intC intGlobalL critR intC intL critR intC intL critL critR intR int. . .C intC int

14/2/2004 34Aspect Ratio – Trade offs• Power – depends on cap.• Frequency:• Local – gates and IC cap.• Global – mostly IC – RC120%110%100%Freq. And Power vs. Relative ARLocal path speed• Per layer AR optimization !• Scaling ⇒ more power save,less frequency loss90%80%PowerFrequency - LocalFrequency - Global70%Global path speedDynamic Power60%50.0% 62.5% 75.0% 87.5% 100.0% 112.5% 125.0% 137.5% 150.0%ARRelative ARAspect Ratio optimization can save over 10% of dynamic power !

14/2/2004 35Physical Design - Spacing• Spacing can save up to 40%120%0.13 [µm] global IC cap. vs. spacing• About 30% is with double space• Spacing advantages: scaling,frequency, reliability, noise,easy to modifymin. spaceCapacitanceRelative capacitance100%80%60%40%20%2X 3X 4XGlobal capacitanc0%1 1.5 2 2.5 3 3.5 4 4.5 5SpacingSpacingWire spacing can save up to 20% of the dynamic power !

14/2/2004 36Spacing calculationBack of an envelope estimation:• 10% of Interconnect ⇒ 90% power• X2 spacing = extra 20% wiring• Global clock – not spaced (inductance)• Global clock is 20% of interconnect power• Save: 30% of (90%-20%) = 20%• Interconnect is 50% ⇒ 10% power saveExpected 20% with downsizing• Minor losses - congestion

14/2/2004 37µ-Architecture - CMP• Comparing two scalingmethods, by IC power.Gen. 1 Gen. 2UniprocessorP`• IC - predicted by Rent• L2 - identical, minor• Clock - Identical !• Same average AF.PL2`L2CMPP” P”• Result ~5% less dynamic power for CMPL2`

14/2/2004 38Power criticalvs.Timing critical100%90%80%acummulated power70%Accumulated Power60%50%40%30%20%10%0%Timing criticalSlack [ps]

14/2/2004 39Outline• Research methodology• Interconnect Power Analysis• Future Trends Analysis• Interconnect Power Implications• Summary

14/2/2004 40Interconnect Length Prediction• Technology projections - ITRS• Interconnect length predictions:• ITRS model: 1/3 of the routing space- most optimistic• Davis model:o Rent’s rule basedo Predicts number of nets as function of:the number of gates and complexity factors• Models calibrated based on the case studyTime?

14/2/2004 41Rent’s parametersRent’s rule: T = k N rTNKr= # of I/O terminals (pins)= # of gates= avg. I/O’s per gate= Rent’s exponentcan be: 0 < r < 1 , but common -(simple) 0.5 < r < 0.75 (complex)N gatesT terminals

14/2/2004 42Donath’s length estimation modelFor the i-th level:There are4 iblocksFor each block there are:⎛k ⋅⎜⎝Assuming two terminal nets :Ni4k2r⎞⎟⎠⎛⋅⎜⎝terminalsNi4r⎞⎟⎠netsThe nets of the i-1 level must be substracted.Nets for level i : ni= 4i⋅k ⎛⋅⎜2 ⎝Ni4r⎞⎟⎠- 4i−1⋅k ⎛ N⋅⎜2 ⎝ 4i−1r⎞⎟⎠= 4i⋅k ⎛⋅⎜2 ⎝Ni4r⎞⎟⎠⋅(r−11−4 )

14/2/2004 43Average interconnection lengthThe wires can be of two types A and D.LA =LD =λ λ λ λ∑∑∑∑[ λ + iA−iB+ jB− jA]i = 1j = 1i = 1j= 1A A B Bλ λ λ λ∑∑∑∑i = 1j = 1i = 1j= 1A A B BThe average: ri=Overall :RI∑i=1=I∑i=14λ2λ+ i[ + j −i− ]niAAB4λ14⋅λ2−9 9⋅λ⋅ rniiequals4 1= ⋅λ−3 3λjB= 2⋅λ29⎛⋅⎜7⋅⎝N4r−0.5Taken from a SLIP 2001 tutorial by Dirk Stroobandtr−0.5−11−N−−11−4r−1.5r−1.5⎞ ⎛ −⋅ 1 4⎟⎜⎠ ⎝1−Nr−1r−1⎞⎟⎠

14/2/2004 44• From Rent’s rule:•IDF:()i l• Where:FOα = ,Davis ModelTr= r⋅N3⎧ α ⋅r⎛l2 ⎞ 2⋅ p−4⋅Γ⋅ 2 N l 2 N l l1 l N : ⎜ − ⋅ ⋅ + ⋅ ⋅ ⎟⋅⎪ ≤ ≤2 3= ⎝ ⎠⎨N l 2 N : α r3⎪ ≤ ≤ ⋅ ⋅2⋅p−4⋅Γ⋅( 2⋅ N ⋅l)⋅l⎪⎩6P−1( )Γ= 2⋅N⋅ 1−N2 1FO + 1 ⎛ ⋅p−p 1+ 2⋅ p−2 1 2⋅N N ⎞⎜−N ⋅ − + − ⎟⎝ p ⋅( 2⋅ p −1) ⋅( p −1) ⋅( 2⋅ p −3)6⋅ p 2⋅ p −1 p −1⎠P• Interconnect total number and length:2⋅N2⋅NNets: I i ζ dζLength:total1• Multipoint Length:= ∫ ( )total ∫ ( )multi_terminalL = i ζ ⋅ζ ⋅dζL = L ⋅χwhere χ=1total4FO+3

14/2/2004 45Davis Model - extension• Constant factor favors shorter nets.• Short P2P net has higher chance to be a partof a multipoint net.• Correction factor:• Length:number of point to point nets shorter than lmulti-terminal factor( l) =total point to point netsl1Imulti-terminal() l = i( ζ ) multi-terminal factor( ζ)dζFO∫1110000000.1ExtractedDavis Model100000MeasuredExtended Davis Model10000Nets0.010 .001Number of Nets10001000 .0001100.000011 10 100 1000 10000 100000Length [um ]11 10 100 1000 10000 100000Length |um|

14/2/2004 46RMST - Example

14/2/2004 47Total Dynamic Power• Total DynamicPower• Global clock –not included• Localnets = 66%Globalnets = 34%Power (normalized)Power654321Total Power vs. Net LengthTOTALTotal_IC0Interconnect1 10 100 1000 10000 100000Length [um]Length [µm]

14/2/2004 48Local and Global IC• Local and GlobalIC are different:• Number byLengthbreakdown• IC breakdown –cap and power• Fan out• Metal usage• AF is similarPowerPower100 %80 %60 %40 %20 %0%100 %80 %60 %40 %20 %Local Power breakdown vs. Net Length4 .16 8 . 32 16 .64 32 .864 65 .728 131 . 456 262 .496 523 .744 1044 . 99 2084 .99 4160 8300 . 45 16561 .4 33930 83850Length [ um ]Global Power breakdown vs. Net LengthICDiffGateICDiffGate0%4 . 16 8 . 32 16 . 64 32 . 864 65 . 728 131 . 456 262 . 496 523 . 744 1044 . 99 2084 . 99 4160 8300 . 45 16561 . 4 33930 83850Length [ um ]

14/2/2004 4945Benchmarks ComparisonGlobal Dynamic power vs. Length40High Power TestsBenchmarks3530Power25201510501 10 100 1000 10000 100000 1000000Length [um ]High power tests show similar behavior to average SPEC !

14/2/2004 50Interconnect PeaksTotal wire length vs. Length4MeasuredDavis ModelTotal wire length32120101 0 10 100 Length [ um ] 1000 10000 100000Length [µm]Average gate sizing vs. Length1 . 8Average gate sizing1 . 61 . 4Relative sizing1 . 210 . 80 . 60 . 40 . 201 10 100 1000 10000 100000010 100 1000 10000 100000[ um ]Length [µm]

14/2/2004 51ITRS Power Trends• The ITRS power projection interconnect powerreduction that happens in 2006-2007 is based on:1. Aggressive voltage reduction2. Low-k dielectric improvements• The devices capacitance increase by +30% (trend -15%)• The combined effect:• Interconnect power reduction (relative to voltage)• Device power remains constant

[ W]14/2/2004 52Dynamic power - ITRS trend600 .00Dynamic power projection500 .00ICPower (normalized)400 .00300 .00200 .00DiffGate100 .000.000 .15 0 .13 0 .1 0 .09 0 .08 0 .07 0 .065 0 .045 0 .032 0 .02Generation 1 /2 min pitchTechnology generation [µm]The Black curve is the ITRS maximum heat removal capabilities

14/2/2004 53Power-Aware FlowPlacement• The reduced IC cap allows fordriver downsizing• On average it reduced thedynamic power by 1.4 of the ICpower saving• Downsizing is timing verified• Cells downsizing reduced thetotal area and leakage by 0.4%• No signal spacing was appliedover 30% unused metal• Post-layout optimization arepossibleYesPower-aware RoutingRC ExtractionTiming Analysis,Power AnalysisAll slackspositive?YesPower drivenTiming constraineddriver downsizingSizingmodified?NoTiming driven -driver upsizingNoFinish

14/2/2004 54FUBS – description• A – medium, randomly picked• B – small, highest clock power• C – small, good potential• D – medium, good potential• E – worse than averageBlock Name Block A Block B Block C Block D Block E AVERAGEArea [µm 2 ] 138801.6 101274.6 65816.1 164229.1 59766.3 209537.8Devices 14574 8644 7618 18194 6109 16675Inactive Nodes 63.66% 98.78% 82.36% 39.22% 35.38% 52.94%Power [uW] 17170.22 251.15 1786.76 11811.90 6757.11 15373.86RMST potentialpower saving14.3% 17% 22% 29% 4.1% 17%Clock cap. 11.25% 2.59% 12.75% 13.16% 3.27% 8.01%Clock power 72.10% 99.99% 96.46% 94.99% 33.84% 60.47%IC cap. 34.00% 27.70% 38.14% 36.05% 29.86% 34.67%IC power 28.89% 59.54% 46.74% 48.62% 40.65% 36.83%Clock IC power 20.19% 59.54% 45.48% 46.26% 16.87% 23.87%Clock IC length 1.71% 2.34% 2.05% 2.09% 0.74% 3.85%Relative -Capacitance perLength Unit.82.23% 113.15% 87.46% 83.74% 85.97% 88.46%

14/2/2004 55Miller Factor - PowerR1• Opposite direction switching-• The current:• Energy:• That is 4 times a single switching energy.V1CR2V2dQ dC ( ∆Vc)d∆VcIc= = = Cdt dt dtd∆VE I V dt C V dt C V dv C VT T Vddc2c= ∫ c⋅dd⋅ = ∫ ⋅ ⋅dd⋅ = ⋅dd c2dddt∫ = ⋅ ⋅0 0−VddDecoupling by Miller factor of ‘2’.• Same direction switching => no current.Decoupling by Miller factor of ‘0’.• Average case: Miller factor of ‘1’ suitable for poweraveragecase sum metric.

14/2/2004 56Routing Model• Via blockage:• Router efficiency: 0.6• Power grid: 20% of routing• Clock grid: 10% of top tier( ) Low layer pitch High layer pitchLayer multiplier = 1 - blocking fraction• More accurate than ITRS 2001.