Packet Processing to support 40 /100GE Line Rates - Ethernet ...

Agenda• Current Challenges• Application Requirements• Tabula Solutions for 100GE PacketProcessing• Tabula Technology & Tools• Summary• Next StepsSanta Clara, CA USA April2013 2

40GE / 100GE & Beyond....Packet Processing ChallengesSanta Clara, CA USA April2013 3

Ethernet Stack: ProcessingChallengeEthernet OSI ModelContext Layer FunctionDataDataDataSegmentsPacketsFramesBitsApplicationPresentationSessionTransportNetworkData LinkPhysicalDeep Packet InspectionApplication Aware Routing, SwitchingFlow ClassificationRoutingBridging, Switching1

Device Elements for PacketProcessingASIC / ASSPFunctionality

Device Elements for PacketProcessingFPGAFunctionalityDSP Block6-Input LUT Architecture

Packet Processing at 100GE• ~50% of Ethernet packets have a minimumpacket size ~64 bytes• Line rate packet processing requirements:1GE10GE40GE100GEEthernet Minimum Packet Size(64 bytes + 20-byte IFG)672ns67.2ns16.8ns6.72ns[K. Thompson, G. Miller, R. Wilder, Wide-area traffic patterns and characterization, IEEE Network, Dec. 1997]@100GE Line Rate, implementation = max 2-3 Packet operations + bufferingSanta Clara, CA USA April20137

Performance Bottlenecks areEVERYWHERE• Limited Application Performance• E.g. Network Security Appliance Implementation• Multiple ASICs, ASSPs, PLDs• Software• IO Bandwidth: Multiple 10G, typically• 4-8 10GE lanes• 10-20 1GE lanes• Application Performance:• Firewall Bandwidth: ~50%• IPS Throughput:

Application RequirementsSanta Clara, CA USA April2013 9

Application Requirements• Performance Matched Device Elements• High Bandwidth Memory Elements• Ability to Store Once, and Simultaneously ReadMultiple TimesSanta Clara, CA USA April2013 10

Application Requirements• Simple Design Flow• Design for Intent• Automatic Optimization for Higher Perfromance• Faster Design Cycle TimesSanta Clara, CA USA April2013 11

Tabula Solutions for 100GE PacketProcessingSanta Clara, CA USA April2013 12

100G L2-L4 Packet Parser Engine• Function• 9-tuple Header extraction at wirelinespeed• Features• Multiple Ethernet packet formats• Rapid adaptation of additionalpacket formats• Microcode compiler• Performance• < 0.05% Device Resources• < 20ns Latency• 256b @ 500MHzMulti-portMem[Pattern Match]Multi-portMem[App Logic]BitProcessingPL RegPL RegSanta Clara, CA USA April2013 13

100GE – 12x10GE Layer2 BridgeSanta Clara, CA USA April2013 14

4 x 100G Crossbar• Function• 4-port 100GE Crossbar• Features• Support 288KB of per port buffering• 8 queues / port with 32kB / queue• Built in unicast / multicast support• Performance• < 0.05% LUTs• < 20% LRAMs• Port-to-port latency ~12ns• 256b @ 472 MHzPorts are made of3-ported RAMblocksSanta © 2013 Clara, Tabula CA USA Confidential April 2013 15

Ternary Search EngineSanta Clara, CA USA April2013 16

Tabula Technology & ToolsSanta Clara, CA USA April2013 17

Spacetime Addresses TheInterconnect BottleneckInterconnect2 GHzRAMLogicRAM2 GHz2 GHz2 GHzTransceiversTransceiversEverything can run at 2 GHz on Tabula DevicesSanta Clara, CA USA April2013 18

Spacetime Addresses The MemoryBottleneck• High bandwidth, multi-ported RAM blocks• Upto 24 ports• Includes ASYNC FIFO Controllers• High bandwidth, multi-ported RAM enable• Crossbars• State machines & Microcontrollers• Data structures• Hash tables• ROMsSanta Clara, CA USA April2013 19

Queuing and De-Queuing– This memory is dividedinto separate queueswith independent writeports– A single read port hasaccess to all queues• FPGA / ASIC: Multi-ported memory must beconstructed out of dual ported memories• Similar principle for a single write port to multipleread ports20© 2013 Tabula, Inc.

Broadcasting– A single write portprovides access to thebuffer for the input data– Independent ReadPorts have access to allof the data• FPGA / ASIC: Multi-ported memory must beconstructed out of dual ported memories© 2013 Tabula, Inc.21

Data Selection / IndexingMemoryLogic Block 1Logic Block 2Logic Block 3• IPv4 header aligned to 32bits• Logic can operate on 64-bits and smaller portions of 16-bit or8-bit using multiple ports from the memory• Data normally appearing on different clocks can be accessedwithin the same clock using multiple read ports22© 2013 Tabula, Inc.

Tabula ABAX2P1 –Designed for 100G System Implementation• User clock rate: up to 2 GHz• Memory Rich Architecture: high capacity at highperformance• IO Rich Architecture: designed for 4 x 100 GigEtraffic• Hard IP• Memory Controllers• Processing Rich Architecture• DSP: 2 GHz blocks• LCB:Santa Clara, CA USA April2013 23

Tabula Tools: Stylus®ASIC / ASSP / FPGA: Multiple Optimization StepsTiming ClosureSanta Clara, CA USA April2013 24

Tabula Tools: Stylus®ASIC / ASSP / FPGAMultiple Optimization StepsSTYLUSTiming Aware Design FlowSynthesisPlacementRouting- Accurate feedback- Short cycleSanta Clara, CA USA April2013 25

SummarySanta Clara, CA USA April2013 26

100GE Packet Processing &Beyond• Industry trends driving 40GE / 100GE adoption• Big Data will be here sooner than we anticipate• Cheaper Optics: Silicon Photonics• Simplified Network Programming Initiative: SDN• 40/100GE Packet Processing Solutions• Plan your architecture right• System Integration– Fixed Functions– Programmable Hardware– SoftwareSanta Clara, CA USA April2013 27

Want To Learn MoreSanta Clara, CA USA April2013 28

Tabula Solutions• Tabula Technology & Tools• http://customer.tabula.comSanta Clara, CA USA April2013 29

QuestionsSanta Clara, CA USA April2013 30