IC-910H Service manual.pdf - N3UJJ

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4-1-6 10 MHz IF CIRCUIT (MAIN UNIT)The 10 MHz IF signal from the mixer circuit is passedthrough a monolithic filter (Fl51 [Main], Fl651 [Sub]) to suppressout-of-band signals. The filtered signal is amplified atthe IF amplifier (Q51 [Main], Q651 [Sub]). The IF amplifierprovides 20 dB gain.The amplified signal is then applied to the different circuitsdepending on the selected mode.(1) FM modeThe signal is applied to an FM IF IC pin 16 (IC401 [Main] orIC951 [Sub]).(2) SSB and CW modeThe signal is passed through a 10 MHz IF filter (FI151/10.85MHz [Main] or Fl751/10.95 MHz [Sub]) or optional CW narrowfilters. The filtered signal is amplified at the IF amplifiers(Q350–Q352 [Main] or Q850–Q852 [Sub]) and then appliedto a demodulator circuit.4-1-7 DEMODULATOR CIRCUIT (MAIN UNIT)(1) FM modeThe 10 MHz IF signal from an IF amplifier (Q51 [Main] orQ651 [Sub]) is applied to the mixer section of the FM IF IC(IC401 [Main], IC951 [Sub], pin 16), and is mixed with a LOsignal (10.395 MHz [Main], 10.495 MHz [Sub]) to produce a455 kHz IF signal. The LO signal is generated by the BFOcircuit (PLL unit; IC601 [Main], IC701 [Sub]).The FM detector circuit employs the quadrature detectionmethod, which uses a ceramic discriminator (X401 [Main],X951 [Sub]) for phase delay to obtain a non-adjusting circuit.The detected signals are output from pin 9, and applied tothe squelch control and center indication detector circuits,etc.(2) SSB and CW modesThe amplified signal from the IF amplifier circuit (Q51 [Main],Q651 [Sub]) is applied to the balanced mixer circuit (IC351[Main], IC851 [Sub]) to demodulate into AF signals.Demodulated audio signals are output from pin 1, andapplied to the squelch control gate (IC452 [Main], IC1002[Sub]).BFO circuit (PLL unit; IC601 [Main] and IC701 [Sub]) generatesBFO signals for using in the balanced mixers.• BFO frequenciesMode for MAIN band for SUB bandUSBLSBCW10.8485 MHz10.8515 MHz10.8483 MHz10.9485 MHz10.9515 MHz10.9483 MHz4-1-8 SQUELCH CONTROL CIRCUIT (MAIN UNIT)The demodulated AF signals from the balanced mixer circuitor FM IF IC are applied to the squelch control gate (IC452[Main], IC1002 [Sub]). This consists of 4 analog switcheswhich are selected with a mode signal and squelch controlsignal from the CPU (DISPLAY board; IC1) via the expanderIC (IC1491). The switched AF signals are applied to the AFcircuit.4-1-9 SQUELCH CIRCUIT (MAIN UNIT)(1) FM modeA squelch circuit cuts out AF signals when no RF signal isreceived or the S-meter signal is lower than the [SQL] controlsetting level. By detecting noise components in the AFsignals, the CPU switches the squelch control gate.A portion of the AF signals from the FM IF IC pin 9 (IC401[Main], IC951 [Sub]) passes through the active filter sectionof FM IFIC (pin 8). The active filter section amplifies and filtersnoise components. The filtered signals are applied tothe noise detector section for conversion into DC voltageand output from pin 14 (IC401 [Main], IC951 [Sub]) as the“NSQM [Main]/NSQS [Sub]” signal. The “NSQM [Main]/NSQS [Sub]” signal is applied to the DISPLAY board.The DC voltages are passed through the analog multiplexer(DISPLAY board; IC5, pins 15 and 2) and then applied to theCPU (DISPLAY board; IC1, pins 93, 94) via the MP1Y andMP1X signal lines. The [SQL] level signal is also applied tothe CPU via the analog multiplexer (DISPLAY board; IC3,pins 14, 5) as a reference voltage for comparison with thenoise signals. Also, an S-meter signal is applied to the CPUfrom FM IF IC pin 12 (IC401 [Main], IC951 [Sub]) via themeter amplifier (IC1804c [Main], IC1804a [Sub]) and analogmultiplexer (DISPLAY board; IC4, pins 12 and 1). The CPUcompares these signals, then outputs a control signals tothe squelch control gate.(2) SSB and CW modesThe squelch circuit mutes audio output when the S-metersignal is lower than the [SQL] control setting level.A portion of the 10 MHz IF signal from the IF amplifier (Q352[Main], Q852 [Sub]) is converted into DC voltage at the AGCdetector (D303, Q305 [Main], D902 Q901 [Sub]) and amplifiedat the meter amplifier (IC1804d [Main] or IC1804b[Sub]). The amplified signal is passed through the analogmultiplexer (DISPLAY board; IC4, pins 12 and 1) via theSMLM [Main]/ SMLS [Sub] signals and then applied to theCPU (DISPLAY board; IC1). The CPU outputs control signalsto the squelch control gate when the S-meter signal islow level.4-1-10 AF AMPLIFIER CIRCUIT (MAIN UNIT)The AF amplifier circuit amplifiers the demodulated signalsto drive a speaker. For the separate speaker function, astereo power amplifier is used.AF signals from the squelch control gate are passed throughthe AF filter (IC451a [Main], IC1001a [Sub]) and AF preamplifier(IC451b [Main], IC1001b [Sub]) and then amplifiedat the voltage controlled amplifier (VCA: IC1808 [Main],IC1809 [Sub]) which functions as a volume control using the[AF] control signal. The amplified AF signals are applied tothe AF power amplifier circuit (IC1852, pin 2 [Main], pin 5[Sub]).The amplified audio signals of SUB band are output from pin7, and are applied to the external speaker jack for the SUBband (J1852) via the [PHONE] jack (JACK board; J1). Whenno plug is connected to the jack, the signals are fed back tothe MAIN band audio. The mixed audio is applied to theinternal speaker via the [PHONE] jack and external speakerjack for the MAIN band (J1851).4 - 2From The N3UJJ.COM Document Library
4-1-11 NOISE BLANKER CIRCUIT (MAIN UNIT)The noise blanker circuit detects pulse-type noises, andstops IF amplifier operation during detection.A portion of the 10 MHz IF signal from the bandpass filter(FI51 [Main], FI651 [Sub]) is amplified at the noise amplifiercircuit (Q102, IC101, Q101 [Main], Q702, IC701, Q701[Sub]). The amplified signal is rectified at the noise detector(D371 [Main], D701 [Sub]) for conversion into DC voltage.The DC voltage is amplified at the DC amplifier circuit (Q105[Main], Q705 [Sub]) and then applied to the noise blankercontrol circuit (Q52, Q107 [Main], Q652, Q707 [Sub]) to stopamplification of the IF amplifier circuit (Q51 [Main], Q651[Sub]).4-1-12 AGC CIRCUIT (MAIN UNIT)The AGC (Auto Gain Control) circuit reduces IF amplifiergain to keep the audio output at a constant level.A portion of the 10 MHz IF signal from the IF amplifier (Q352[Main], Q852 [Sub]) is applied to the AGC detector circuitD303 [Main], D902 [Sub]). The detected signal is then amplifiedat the DC amplifier circuit (Q305 [Main], Q901 [Sub])and then applied to the IF amplifiers (Q51, Q351, Q352[Main], Q651, Q851, Q852 [Sub]).When strong signals are received, the detected voltageincreases and the output level of the DC amplifier, as AGCvoltage, decreases. The AGC voltage is used for the biasvoltage for the IF amplifiers, therefore, the IF amplifier gainis decreased.AGC response time is controlled by changing the time constantat the AGC control line with a resistor and capacitor.While AGC is set to slow, the resistor (R312 [Main], R914[Sub]) and capacitor (C306 [Main], C911 [Sub]) are connectedto the AGC control line. While AGC is set to fast,R311 [Main], R913 [Sub] are connected to the AGC controlline. Due to Q304 and Q303 [Main]/Q905 and Q904 [Sub]being switched ON that controlled by the “AGSM”, “AGFM”[Main], “AGSS”, “AGFS” [Sub]. Also, R310 [Main]/R912[Sub] is connected to the AGC control line due to Q302[Main]/Q903 being switched ON while scanning for fasterresponse than AGC fast mode that controlled by the“AGRM” [Main], “AGRS” [Sub].4-1-13 S-METER CIRCUIT (MAIN UNIT)The S-meter circuit indicates the relative received signalstrength while receiving and changes depending on thereceived signal strength.(1) FM modeSome of the amplified IF signal is applied to the S-meterdetector section in the FM IF IC (IC401 [Main], IC951 [Sub])to be converted into DC voltage. The converted signal is outputfrom pin 12 and applied to the meter amplifier circuit(IC1804c [Main], IC1804a [Sub]). The amplified signal isthen applied to the CPU (DISPLAY board; IC1) passingthrough the analog multiplexer (DISPLAY board; IC4, pins12 and 1) via the “SMLM [Main]/SMLS [Sub]” line. The CPUthen outputs S-meter control signal.(2) SSB and CW modesA portion of the AGC control signal is applied to the meteramplifier (IC1804d [Main], IC1804b [Sub]). The amplifiedsignal is then applied to the CPU via the analog multiplexerto control the S-meter.4-2 TRANSMITTER CIRCUITS4-2-1 MICROPHONE AMPLIFIER CIRCUIT(MAIN UNIT)The microphone amplifier circuit amplifies audio signalsfrom the microphone or ACC connector and then appliesthem to the FM modulation or balanced modulator circuit.One microphone amplifier circuit is commonly used for bothFM/SSB and VHF/UHF.Audio signals from the [MIC] connector enter the microphoneamplifier IC (IC1701, pin 22) and are then amplifiedat the microphone amplifier or speech compressor section.Compression level is adjusted by the setting mode.The amplified or compressed signals are applied to the VCAsection of IC1701. The microphone gain setting from the D/Aconverter (IC1521, pin 8) is applied to the VCA control terminal(IC1701, pin 10). The resulting signals from pin 9 arethen applied to the buffer-amplifier (Q1651) via the analogswitch (IC1653a). External modulation input from the [ACC]socket (pin 4) is also applied to Q1651.• AGC CIRCUIT FOR MAIN BAND2nd IFsignalRFGM(RF/SQL control)C309–5 VAGC det.D303C310R315R316R317C311Q306C312D302R314SCANR310Q302R311Q303FASTSLOWC306 R312Q304C307 R313C308R303R302 IC1804d13+Meter 1412 amp.–R304AGC line“SMLM”S-meter signal9 V4 - 3From The N3UJJ.COM Document Library
Page 1 and 2: SERVICEMANUALVHF/UHF ALL MODE TRANS
Page 3 and 4: TABLE OF CONTENTSSECTION 1SPECIFICA
Page 5 and 6: ■ RECEIVER• Receive system :VHF
Page 7 and 8: • PA UNITTX/RX switching relay(RL
Page 9 and 10: SECTION 3DISASSEMBLY AND OPTION INS
Page 11 and 12: • UT-102 VOICE SYNTHESIZER UNITq
Page 16 and 17: While in SSB mode, the amplified si
Page 18 and 19: The passed signals are then applied
Page 20 and 21: 5-2 PLL ADJUSTMENTSADJUSTMENT30.2 M
Page 22 and 23: 5-4 RECEIVER ADJUSTMENTSReceiver ad
Page 24 and 25: RECEIVER ADJUSTMENTS (continued)ADJ
Page 26 and 27: 5-5 TRANSMITTER ADJUSTMENTSADJUSTME
Page 28 and 29: TRANSMITTER ADJUSTMENTS (continued)
Page 30 and 31: 5-6 SOFTWARE ADJUSTMENTADJUSTMENT A
Page 32 and 33: SOFTWARE ADJUSTMENT (continued)ADJU
Page 34 and 35: SOFTWARE ADJUSTMENT (continued)ADJU
Page 36 and 37: 5-7 UX-910 ADJUSTMENTSADJUSTMENT2ND
Page 38 and 39: UX-910 ADJUSTMENTS (continued)ADJUS
Page 40 and 41: SECTION 6PARTS LIST6-1 IC-910[FRONT
Page 42 and 43: [DISPLAY BOARD]REFNO.ORDERNO.DESCRI
Page 44 and 45: [PLL UNIT]REF ORDERNO. NO.DESCRIPTI
Page 46 and 47: [PLL UNIT]REF ORDERNO. NO.DESCRIPTI
Page 48 and 49: [MAIN UNIT]REF ORDERNO. NO.DESCRIPT
Page 56 and 57: [PA UNIT]REFNO.ORDERNO.DESCRIPTIONI
Page 58 and 59: [PA UNIT]REF ORDERNO. NO.DESCRIPTIO
Page 64 and 65:
6-2 UX-910[MAIN UNIT]REFNO.ORDERNO.
Page 66 and 67:
[MAIN UNIT] — UX-910REF ORDERNO.
Page 68 and 69:
[MAIN UNIT] — UX-910REF ORDERNO.
Page 70 and 71:
SECTION 7MECHANICAL PARTS[FRONT UNI
Page 72 and 73:
MP34 (CH)MP34 (CH)MP12 (CH)MP1851 (
Page 74 and 75:
SECTION 8SEMI-CONDUCTOR INFORMATION
Page 76 and 77:
• DIODES1SS301 1SS355 1SS375-TL 1
Page 78 and 79:
• BOTTOM VIEW (RIT BOARD)• BOTT
Page 80 and 81:
• BOTTOM VIEW (VARISTOR-A BOARD)
Page 82 and 83:
• BOTTOM VIEW (DISPLAY BOARD)J10
Page 84 and 85:
• BOTTOM VIEW (PA UNIT)64133 416F
Page 86 and 87:
• BOTTOM VIEW (PLL UNIT)R341MP11F
Page 88 and 89:
6105171• BOTTOM VIEW (MAIN UNIT)6
Page 90 and 91:
• BOTTOM VIEW (UX-910 MAIN UNIT)0
Page 92 and 93:
10-2 PA AND PLL UNITStoMAINUNITGHVR
Page 94 and 95:
11 - 1SECTION 11WIRING DIAGRAM1 2 J
Page 96 and 97:
12-2 PLL UNITto DISPLAYboard J9CP7L
Page 98 and 99:
12-4 PA UNIT (2)toUX-910W305P1to MA
Page 100 and 101:
12-6 MAIN UNIT (2)12-7 MAIN UNIT (3
Page 102 and 103:
12 - 812-9 UX-910 MAIN UNIT (2)CHAS
Page 104:
lcom Inc.1-1-32, Kamiminami, Hirano
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