Very Large Scale Integration (VLSI) - GUC - Faculty of Information ...

Very Large Scale Integration(VLSI)Lecture 1Dr. Ahmed H. MadianAh_madian@hotmail.comDr. Ahmed H. Madian-VLSI 1

Course ObjectiveYou’ll get a bottom-up tour of how integrated circuits are engineered.We’ll talk about• MOSFETs: how they work, how they’re built, effects of newtechnologies• Various design and layout techniques, from the ordinary to themost complex, for creating combinational and sequential circuits,datapaths, memories, buffers, regular logic structures, …etc.• how you tackle the problem of designing circuits with 1,000,000gates -- you’re not in Digital IC Technique anymore!• Give different testing techniques for VLSI circuits.Dr. Ahmed H. Madian-VLSI 2

Administrative Rules• Course schedule:• Lectures:• Saturday (3 rd slot), 12:30 - 13:45• Tuesday (4 th slot), 14:15- 15:45• Office hours: Saturday 14:30 - 16:30 (C3.221)• Teaching assistant: Eng. Mona Guindy• Grading• Quizzes & Assignments: 20%• Assignment of every lecture is due the following lecture• Final exam: 80%Dr. Ahmed H. Madian-VLSI 3

References• Anantha Chandrakasan, William J. Bowhill, Frank Fox,“Deign of high performance microprocessor circuits”• John P. Uyemura, “Introduction to VLSI circuits andsystems”• Or any VLSI referencesDr. Ahmed H. Madian-VLSI 4

Course outline• Overview of VLSI• Technologies for Micro- and Nanostructures• Low-Voltage and power design• Synchronous and Asynchronous Circuit Design• Architectures for VLSI Applications• Test and Measurement Techniques for VLSICircuitsDr. Ahmed H. Madian-VLSI 5

What is VLSI?• VLSI stands for (Very Large Scale Integratedcircuits)• Craver Mead of Caltech pioneered the filed of VLSIin the 1970’s.• Digital electronic integrated circuits could beviewed as a set of geometrical patterns on thesurface of a silicon chip.• Complexity could thus be dealt with using theconcept of repeated patterns that were fittedtogether in structured manner.Dr. Ahmed H. Madian-VLSI 6

VLSI History•Jack Kilby, working at Texas Instruments, first dreamed up the idea of amonolithic “integrated circuit” in July 1959. By the end of the year, he hadconstructed several examples, including the flip-flop shown in the patentdrawing above. Components are connected by hand-soldered wires andisolated by “shaping” and pn diodes used as resistors.Dr. Ahmed H. Madian-VLSI 7

VLSI History (cont.)• 1961: TI and Fairchild introduced the first logic IC’s (cost~$50 in quantity!). This is a dual flip-flop with 4 transistors.• 1963: Densities and yields are improving. This circuit hasfour flip flops.In 1970, making good on its promise to itsinvestors Intel starts selling a 1K bit RAM,the 1103.Dr. Ahmed H. Madian-VLSI 8

VLSI History (cont.)• Introduced in 1972, the 8008 had 3,500transistors supporting a byte-wide datapath. Despite its limitations, the 8008was the first microprocessor capable ofplaying the role of computer CPU asdemonstrated on the cover of the July‘74 issue of Radio-Electronics.Dr. Ahmed H. Madian-VLSI 9

Today• Many disciplines havecontributed to the currentVLSI designs:• solid-state physics• materials science• lithography and fab• device modeling• architecture• algorithms• CAD tools• circuit design & layoutDr. Ahmed H. Madian-VLSI 10

Chip ComplexityChip classification according to number of active elements and minimal feature size:Dr. Ahmed H. Madian-VLSI 11

VLSI Chip Types• Full customEvery circuit is custom designed• Application-specific integrated circuits(ASICS) Design is created using astandard CAD tools without the need tointeract with the silicon structure• Semi-customIn between of full-custom and ASIC-typecircuits. The majority of the chip is designedusing a primitive predefined cells (standardcells) from library as building blocks.Dr. Ahmed H. Madian-VLSI 12

Top design levelSystem specificationsInitial conceptAbstract High-level modelVHDL, Verilog, HDLSystem designand verificationDesignhierarchyoverviewLogic synthesisCircuit designLogic designand verificationCMOS designand verificationbottom design levelphysical designSilicon logic designand verificationManufacturingMass production,testing andpackagingFinished VLSI chipMarketingDr. Ahmed H. Madian-VLSI 13

Top design levelSystem specificationsInitial conceptAbstract High-level modelVHDL, Verilog, HDLSystem designand verificationVLSIDesignbottom design levelLogic synthesisCircuit designphysical designLogic designand verificationCMOS designand verificationSilicon logic designand verificationManufacturingMass production,testing andpackagingFinished VLSI chipMarketingDr. Ahmed H. Madian-VLSI 14

VLSI ChallengesThe Moore’s Law (Moore is one of the co-founder of Intel corp.)has been fundamental to the silicon industry, obeyed for the past30 years; however, technology scaling will become difficultbeyond 0.18 micron, threatening Moore’s Law.Dr. Ahmed H. Madian-VLSI 15

Scaled-down TransistorsThe principle of constant-filedscaling lies in scaling the devicevoltages and the device dimensions(both horizontal and vertical) by thesame factor , k (>1) , such that theelectric filed remains unchanged.Dr. Ahmed H. Madian-VLSI 16

VLSI Challenges (cont.)Design Challenges of TechnologyScaling• Technology models 0.5µm, 0.35µm, 0.25µm,0.18µm, 0.13µm, 90nm, 65nm, 45nm, 32nm,20nm, ???.• Scaling factor of 0.7 in the dimension exist fromgeneration to the next one.• Scaling in Area = 0.7 X 0.7 = 0.490.5. This meansthe transistor density doubles every generation.Dr. Ahmed H. Madian-VLSI 17

Challenges of VLSI (cont.)Every Two years:1. Capacitance per node reduces by 30% (usual scaling)2. Electrical nodes in a given area increase by 2X3. Die size grows by 14% every two years (Moore’s Law)4. Supply voltage reduces by 15% every two years5. And frequency increases by 2X.• This all adds up to 2.7X increase in active power of thelead microprocessor every two years.Dr. Ahmed H. Madian-VLSI 18

Revision on MOSFETFabrication procedureDr. Ahmed H. Madian-VLSI 19

Building MOSFET• bulk CMOS with a p-type substrate:P-typeslice of a silicon ingot that has beendoped with an acceptor (typicallyboron) to increase the concentration ofholesBack is metallized to providea good ground connection.Dr. Ahmed H. Madian-VLSI 20

Building MOSFET (cont.)• Next, a “thick” layer of silicon dioxide, called field oxide,is formed on the surface by oxidation in wet oxygen.This is then etched to expose surface where we want tomake a MOSFET:Dr. Ahmed H. Madian-VLSI 21

Building MOSFET (cont.)• Now grow a “thin” layer of silicon dioxide, calledgate oxide, on the surface by exposing the waferto dry oxygen.Dr. Ahmed H. Madian-VLSI 22

Building MOSFET (cont.)• On top of the thin oxide a thick layer of polycrystalline silicon,called polysilicon or poly for short, is deposited by CVD. Thepoly layer is patterned and plasma etched exposing thesurface where the source and drain junctions will be formedDr. Ahmed H. Madian-VLSI 23

Building MOSFET (cont.)• The entire surface is doped, either by diffusion or ionimplantation, with phosphorus (an electron donor) whichcreates two n-type regions in the substrate. The phosphorusalso penetrates the poly reducing its resistance and affectingthe nfet’s threshold.n+ n+Dr. Ahmed H. Madian-VLSI 24

Building MOSFET (cont.)• Finally an intermediate oxide layer is grown andthen reflowed to flatten its surface. Holes areetched in the oxide (where contacts to poly/diffare wanted) and aluminum deposited, patternedand etched.n+ n+Dr. Ahmed H. Madian-VLSI 25

Threshold voltage• The gate voltage required to form the channel is called thethreshold voltage. Many factors affect the gate-source voltage atwhich the channel becomes conductive. Threshold voltage forsource-bulk voltage zero:VTo 2GCFQCboxQCAs V sb increases, the depth of the depletion region increases, exposing moreof the fixed acceptor (i.e. negative) ions in the substrate.VT Vtno VsB 2 2where FFoxox2qNWhere F is the Fermi potential, Q b is the depletion region charge, is thesubstrate coefficient and V SB is the substrate bias voltageDr. Ahmed H. Madian-VLSI 26siCoxA

Channel-Length modulationDr. Ahmed H. Madian-VLSI 27

SPICE Models• There are different models used in circuitsimulators:• level 1 is our simple model including the mostimportant second order effects described• level 2 model is based on device physics• level 3 is a semi-empirical model allowing tomatch equations to the real circuit: exampleBSIM model from Berkeley modelssubthreshold characteristics.Dr. Ahmed H. Madian-VLSI 28

Physical design• CMOS ICs are electronic switchingnetworks that are created on small area ofsilicon wafer using complex set of physicaland chemical processes.• A primary task for VLSI designer is totranslate circuit schematics into siliconform (this process is called physical design)Dr. Ahmed H. Madian-VLSI 29

Integrated Circuit Layers• ICs are made bystacking different layersof materials in a specificorder to form threedimensional structuresthat act as an electronicswitching network.Layer M1InsulatorSubstrateSubstrateM1M1Side viewTop viewDr. Ahmed H. Madian-VLSI 30

Integrated Circuit Layers (cont.)Layer M2Layer M1insulatorLayer M1SubstrateLayer M2Side viewTop viewDr. Ahmed H. Madian-VLSI 31

Designing NFET Arrays layout• Devices can sharepatterned regions,which may reducethe layout area orcomplexityA B Cn+ n+ n+ n+ n+ n+n+ n+ n+ n+A B CDr. Ahmed H. Madian-VLSI 32

Designing PFET Arrays layout• Devices can sharepatterned regions,which may reducethe layout area orcomplexityA B Cp+ p+ p+ p+ p+ p+N-wellp+ p+ p+ p+A B CDr. Ahmed H. Madian-VLSI 33

Design Examples VLSI• Draw the CMOS realization and thelayout of NAND and NOR gates• Colors of layerspolysilicon (gates): RedDoped n+/p+ (active) : GreenN-Well : YellowMetal 1: BLUEMetal 2 : GreyContacts: Black X’sDr. Ahmed H. Madian-VLSI 34

CMOS RealizationV DDV DDaF a.bbaF a bbNAND gate CMOS realizationNOR gate CMOS realizationDr. Ahmed H. Madian-VLSI 35

NAND FET LayoutPFETN-WELLP+ Gate P+Gate P+aV DDbNFETN+ Gate N+ Gate N+Dr. Ahmed H. Madian-VLSI 36

NAND FET Layout (cont.)V DDX XV DDPFETabNFETXGNDDr. Ahmed H. Madian-VLSI 37

NAND FET Layout (cont.)V DDV DDPFETXXXOUTabNFETGNDXabXDr. Ahmed H. Madian-VLSI 38

NOR FET layoutV DDV DDPFETXXOUTabNFETGNDXaXbXDr. Ahmed H. Madian-VLSI 39

Design Examples VLSI• Draw the pass transistor realizationand the layout of MUX 4:1• Colors of layerspolysilicon (gates): RedDoped n+/p+ (active) : GreenN-Well : YellowMetal 1: BLUEMetal 2 : GreyContacts: Black X’sDr. Ahmed H. Madian-VLSI 40

CMOS realization of MUX 4:1S1 S1 S0 S0P0P0P1P2P3MUX4:1FP1FS0S1P2P3Dr. Ahmed H. Madian-VLSI 41

MUX layoutS1S1S0S0S1 S1 S0 S0P0XXXXP0P1XXXFP1FP2XXXXP2P3XXXP3Dr. Ahmed H. Madian-VLSI 42

Design Examples VLSI• Draw the CMOS realization and the layout oflogic function• Colors of layerspolysilicon (gates): RedDoped n+/p+ (active) : GreenN-Well : YellowMetal 1: BLUEMetal 2 : GreyContactsf a b.c: Black X’sDr. Ahmed H. Madian-VLSI 43

CMOS RealizationV DDbcafbacDr. Ahmed H. Madian-VLSI 44

Logic function LayoutV DDN-WellPFETP+bcafbaNFETN+cDr. Ahmed H. Madian-VLSI 45

Logic function LayoutV DDPFETN-WellXcV DDXbXabcafNFETabcDr. Ahmed H. Madian-VLSI 46

Logic function LayoutV DDPFETN-WellXcV DDXbXaXbcaffbaNFETXXXcGNDDr. Ahmed H. Madian-VLSI 47

Layout Rules• Layout rules are the common language between design andprocess engineers• conservative rules absorb process disturbances and variations• layout rules must be respected by the designer• layout rules reflect the limits of a process, they describe:• minimal distance, overlap• minimal width (e.x. channel length, λ)• layout readability is improved using colors:• metal blue• polysilicium red• n-diffusion green• p-diffusion yellow• n-well brown• contact, via blackDr. Ahmed H. Madian-VLSI 48

LayoutDr. Ahmed H. Madian-VLSI 49

Stick Diagram• stick diagrams aretechnology independent• no layout rules need tobe known• mask layout may begenerated automaticallyDr. Ahmed H. Madian-VLSI 50

Digital Layout: horizontal or verticalgates?• Vertical gates• Good for circuits where fetssizes are similar and eachgate has limited fanout. Bestchoice for multiple input staticgates and for datapaths.• Horizontal gates• Good for circuits where long and shortfets are needed or where nodes mustcontrol many fets. Often used inmultiple-output complex gates (e.g,sum/carry circuits).Dr. Ahmed H. Madian-VLSI 51

Eliminating GapsDr. Ahmed H. Madian-VLSI 52

Complex CMOS Gates compactlayout.• Euler Rule:• Generate an n-graph by replacing the nfet blockwith vertices for nodes and edges for fets• Generate a dual p-graph• Find a sequence containing all edges in the n-graph. This sequence is called Euler n-path.• Generate an Euler p-path with the same labelingas the Euler n-path. If not possible start again.• The labeling sequence of the 2 Euler paths are thegate sequence of the single row nfet/pfet CMOSgate.Dr. Ahmed H. Madian-VLSI 53

Example• Draw the most compact layout for thefollowing logic function using Euler’s rule.F= A.(B+C)Dr. Ahmed H. Madian-VLSI 54

SolutionV DDAFCAN1BAN2FV DDCN2N1BFCBGNDGNDA B CDr. Ahmed H. Madian-VLSI 55

Layout of ExampleA B CA B CDr. Ahmed H. Madian-VLSI 56

Thanks• Revision sheet will be soon available onthe web site• you must solve it• Download one of the layout tools andpractice on the lecture examplesDr. Ahmed H. Madian-VLSI 57