09.07.2015 Views

Understanding LTE Model Internals and Interfaces

Understanding LTE Model Internals and Interfaces

Understanding LTE Model Internals and Interfaces

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

1581 <strong>Underst<strong>and</strong>ing</strong> <strong>LTE</strong> <strong>Model</strong> <strong>Internals</strong> <strong>and</strong> <strong>Interfaces</strong>Agenda• <strong>LTE</strong> Network Architecture• <strong>LTE</strong> Node <strong>and</strong> Process <strong>Model</strong>s• UE Architecture• eNodeB Architecture• Lab 1: Admission Control Customization• EPC Architecture• Global Attribute Definer Object• Demo 1: <strong>LTE</strong> Channel Capacity• <strong>LTE</strong> Features• EPS, EMM, PDCP, RLC• MAC• eNodeB: Frame Generator, Scheduler <strong>and</strong> HARQ• Lab 2: Scheduler Customization• UE: Buffer Status Reporting <strong>and</strong> R<strong>and</strong>om Access• PHY• Architecture <strong>and</strong> MAC to PHY interface• PHY Features• Lab 3: Pathloss Customization• Documentation ReferencesCONFIDENTIAL ─ RESTRICTED ACCESS: This information may not be disclosed, copied, or transmitted in any format without the prior written consent of OPNET Technologies, Inc. © 2010 OPNET Technologies, Inc.60

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!