Rafal Wojtczuk and Joanna Rutkowska - Black Hat

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Intel told us they do have STM specification that answers some of our concerns (e.g. that STM is difficult to write), and the spec is available under NDA.
Intel offered us a chance to read the STM spec… ...but required signing an NDA. … We refused. (We’d rather not tie our hands with signing an NDA — we prefer to wait for some STM to be available and see if we can break it :)
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Attacking Intel ® Trusted Executio
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Intel ® Trusted Execution Technolo
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TPM 1.2 Passive I/O device (master-
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PCR “extend” operation PCRN+1 =
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TPM seal/unseal example # echo 'Sec
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Both seal/unseal and quote operatio
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BIOS ROM BIOS FLASH BOOT LOADER OS
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Example #1: Disk Encryption Disk en
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So, a malware can sniff it…
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Example #2: User’s Picture Test :
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Problems with SRTM
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Dynamic Root of Trust Measurement (
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A VMM we want to load (Currently un
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TXT bottom line TXT late launch can
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GRUB (1 st stage) GRUB (2 nd stage)
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First we start “trusted” Xen (b
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Thanks to tboot only when the trust
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Tboot Demo #1: sealing to a trusted
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SENTER is not obligatory!!! TXT and
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Why would a user or an attacker be
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AMD Presidio AMD’s technology sim
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SRTM/DRTM (launch-time protection)
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TXT: exciting new technology with g
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Q: What is more privileged than a k
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Introducing “Ring -2” SMM can a
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SMM vs. TXT?
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Q: Does TXT measure currently used
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Q:So, how does the SENTER deal with
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TXT attack sketch (using tboot+Xen
Page 64 and 65: Address of the shellcode (in the gu
Page 67: The final outcome...
Page 70 and 71: Stay tuned! SMM exploiting to be pr
Page 73 and 74: More on the Implementation Bugs
Page 75 and 76: SMM research quick history
Page 77 and 78: No SMM bugs known... ...cannot read
Page 79: De-soldering?
Page 84 and 85: De-soldered SPI-flash chip
Page 86 and 87: The BIOS image on the SPI-flash is
Page 88 and 89: Remember our Q35 bug from Vegas? (W
Page 90 and 91: Now, applying this to SMM...
Page 95 and 96: We see we can access SMM memory usi
Page 97 and 98: So, what now?
Page 99 and 100: December 2008: Intel We think TXT i
Page 101 and 102: Intel confirmed the problems in the
Page 103 and 104: Intel believes the issues might aff
Page 105 and 106: CERT has assigned the following tra
Page 107 and 108: Stay tuned! (and don’t trust your
Page 109 and 110: Intel Solution to the TXT attack is
Page 111 and 112: Potential issues with STM STM seems
Page 113: Intel Why should we trust BIOS vend
Page 117 and 118: There are some other issues with ST
Page 119 and 120: Still, allowing TXT to work without
Page 121 and 122: Intel TXT is a new exciting technol
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Rafal Wojtczuk and Joanna Rutkowska - Black Hat

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