A Full-Featured Wireless Interface for RS-232 Communications

Paul Sofianos
Motorola, Inc., WSSG RF/IF Applications Engineering
Freescale Semiconductor, Inc.
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INTRODUCTION
This application note describes a full–duplex, wireless
data communication link targeted for RS–232 applications.
An encoding technique has been designed which addresses
many of the problems incurred when attempting to implement
the RS–232 (EIA–232) standard, including but not limited to:
hardware flow control, the DC component of the transmitted
signal, automatic synchronization from host to slave and
error detection. The design emulates a RS–232 null modem
cable for computer–to–computer communications.
The actual design was realized with standard SSI logic
from the high speed CMOS family (MC74HCxxx), an HC05
based MCU, and Motorola’s ISM Band RF chipset. The
targeted data rate was 57,600 Baud, although both higher
and lower data rates are easily attainable. It is expected that
most applications would embed the logic functions (and
possibly the MCU functions) into a FPGA, CPLD, ASIC, or
other LSI logic building block.
Throughout this application note, it is assumed the user is
familiar with standard TTL–compatible CMOS devices and
the ISM Band RF chipset. Please refer to DL110/D and
DL129/D for additional details on individual device
specifications.
THE WIRELESS LINK
The actual implementation of the wireless link transceiver
was accomplished with the Motorola’s ISM Band RF chipset.
This consists of a MC13145 RF Receiver, MC13146 RF
Antenna
Figure 1. RF Transceiver
Block Diagram
RF In
Receiver
DETO
LO2
FRX
RXMC
RXPD
RSSI
Transmitter and MC33411 Baseband. Figure 1 depicts the
block diagram of the RF transceiver. Figures 2, 3, and 4 are
the actual schematics for the Receiver, Transmitter, and
Baseband, respectively.
The transceiver was designed to operate in the unlicensed
(i.e. FCC Part 15) 902–928 MHz Industrial, Scientific and
Medical (ISM) band with low–power transmission. Since
direct–conversion FSK modulation is used in conjunction
with a PLL synthesized carrier, the digital modulation source
must meet certain requirements:
1) The DC component should be as close to zero as
possible. This maintains the best noise immunity at the
receiver.
2) A minimum frequency component must be maintained at
all times. If this condition is not met, the transmitter’s
PLL and receiver’s coilless demodulator will tend to
“track–out” the modulating signal.
3) The maximum frequency component should be known.
This will help define the modulation index and total
bandwidth required for the transceiver.
4) The system should be able to tolerate reasonable
bit–errors.
The MC33411 baseband controls all of the synthesizer
functions via a MCU SPI compatible interface. None of the
audio processing capabilities of the device are used. Table 1
lists various MC33411 register values for both baseset and
handset for the 5 channels used for the prototype.
DETI
LO2
FRX
RXMC
RXPD
RSSI
Baseband
TXD
ENB
DATA
DCK
RCD
Transmitter
RF Out FTX
TXD TXMC
TXPD
FTX
TXMC
TXPD
ENB
DATA
DCK
RCD
© MOTOROLA Motorola, Inc. 1999 For More Information On This Product,
Rev
RF/IF APPLICATIONS INFORMATION
11
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Freescale Semiconductor, Inc.
Figure 2. RF Receiver
VCC
C7 100 p
C8 1.0 n
R2 300
nc...
Freescale Semiconductor, I
RF In
RXPD
LO2
RXMC
C37
100 p
R9
33 k
CF4
C10
CF3
C35 1.0 n
C34 100 p
C6 100 p L5
6.8 n
100 p
VCC
C11
4.7 p
D1
C12
L6
4.7 p
2.2 n
C36 100 p
C41
C30
0.01
1.0 n
C31 1.0 n
R4 100 k
R5 2.85 k
R6
C32
120 k
1.0
VCC
14
19
22
23
24
30
33
20
29
47
2
3
4
21
10
LNA In
Mix1 In
oscC
oscE
oscB
Mix2 In
LO2
Lin Adj1
Lin Adj2
BWadj
Fadj
AFT Out
AFT In
EN
MC
U1
LNA Out
IF1+
IF1–
IF2+
17
27
28
35
IF2–
36
IF Dec1
39
IF Dec2
IF In
IF Out
Lim Dec1
40
38
41
45
Lim Dec2
46
Lim In
44
Det G
5
Det Out
6
RSSI
7
PRES Out
9
C13
16 p
C45 +
1.0
C15 36 p
C28 0.1
C22 0.1
C9 100 p
C26 0.01
C39 100 p
C16
C18 1.0 n
C19 1.0 n
C20 1.0 n
C21 1.0 n
C46 1.0 n
C50 100 p
R3
C25
R11
39 p
27 k
47 p
L7 2.7
L8 2.7
33 k
CF2 CF1
R10
10
T1
C47 1.0 n
C51 100 p
C14
VCC
10 p
C48 1.0 n
C40
12 p
C52 100 p
VCC
VCC
C42 100 p
C27 0.01
C17 1.0 n
C29 0.1
C23 1.0 n
C24 0.1
C49 1.0 n
C53 100 p
VCC
VCC
DETO
RSSI
Default Units: Ohms, Microfarads and Microhenries
CF1,CF2 Toko Type CFSK Series
SK107MX–AE–XXX, 330 kHz BW
CF3,CF4 Handset: TDK CF6118702
Baseset: TDK CF6118902
D1 MMBV809LT1
T1 Toko A638AN–A099YWN
MC13145
C43 22 n
C44 0.01
FRX
2 For More Information On This
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Freescale Semiconductor, Inc.
TXPD
Figure 3. RF Transmitter
VCC
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Freescale Semiconductor, I
TXD
Appx.
1.5 VPP
TXMC
R20
10 k
C77
47 p
D3
C78
47 p
C75
0.5 p
R19
10 k
C74
15 p
C68
100 p
Default Units: Ohms, Microfarads and Microhenries
CF5 Handset: TDK CF 6118902
Baseset: TDK CF 6118702
D2,D3 MMBV809LT1
D2
C65
47 p
L10
1.8 n
C66
100 p
C67
1.0 n
VCC
R13
150
C54
1.0 n
L9
10 n
VCC
9
C63
2.7 p
11
C64
2.7 p
12
5
4
22
16
17
MC13146
OSCB
OSCE
OSCC
MIX/BUF_IN
LINADJ
PA_IN
MC
EN
U2
RF–
RF+
PA_OUT
PRSCOUT
R22
51
1
3
19
14
C56
1.0
VCC
R14
200
C70
0.01
+
C57
1.0 n
C72
C60
100 p
C71
100 p
100 p
C58
1.0 n
C61
100 p
CF5
C59
1.0 n
C62
100 p
C55
1.0 n
FTX
VCC
RF Out
For More Information On This Product,
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Freescale Semiconductor, Inc.
Figure 4. Baseband
C94
4.7
C114
100 p
VCCA
C95
0.1
VCC
R31
10
C97
1.0
VCCA
C96
1.0 n
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Freescale Semiconductor, I
RSSI
DETI
LO2
RXMC
FRX
RXPD
C93
L12
150 n
C104
R28
100 p
82 p
68 k
R35
18 k
C107 1.0
C92
27 p
R29
C105
C91
VCC
270 k
3.9 n
470 p
VCC
R30
51
Default Units: Ohms, Microfarads and Microhenries
37
38
39
40
41
42
43
44
45
46
47
48
RSSI In
Rx Audio In
DS In
Gnd Audio
LO2 Out
LO2 VCC
LO2+
LO2 Ctl
LO2–
LO2 Gnd
LO2 PD
LO2 Gnd
VCCR
R x
O ut
3
6
F
R x
M
C
C90 2.7 n
C89 0.01 R27
C88 200 p R26
E
I
n
3
5 3 4
E
c
a
p
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
3
E P G P P V V
O AI nd AO– AO+ CC B
ut
S S
A A
V AG
M CI
U3
MC33411
P P P LL LL LL F
R T Tx
F V x
G x D
V F C ata
R CC P nd P CC Tx M E LK x D D C N
2
5
1 2 3 4 5 6 7 8 9 1 0
1 1
1 2
180 k
51 k
R24
R25
MCO
VCC Audio
C In
Ccap
C Out
Lim In
Tx Out
DS Out
Fref Out
Fref In
Gnd Digital
MCU Clk Out
C85 0.33
20 k C86 1.0
2.0 k C87 0.1
24
23
22
21
20
19
18
17
16
15
14
13
VCCA
C113
100 p
C83
Y1
11.2 M
C84
5–40 p
20 p
R32
10
C111
1.0
C112
1.0
RCD
DATA
DCK
ENB
TXMC
FTX
TXPD
VCCR
C98
1.0 n
C99
1.0 n
4 For More Information On This
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DIGITAL ENCODING DESCRIPTION
As mentioned above, it is necessary to encode the raw
RS–232 data prior to RF transmission since the incoming
data stream can, and usually will, contain a DC component
Freescale Semiconductor, Inc.
and has no pre–defined minimum frequency component.
Figure 5 is a block diagram of the digital encoder/decoder
section, and Figure 6 shows a possible implementation of the
encoder.
Figure 5. Encoder/Decoder Block Diagram
(Baseset Shown)
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Freescale Semiconductor, I
DB25
P2
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
ETXD
ERXD
ERTS
ECTS
Translator
TXD
RXD
RTS
CTS
To RF
Transceiver
Baseband
TXD
RXD
RTS
CTS
DCK
ENB
DATA
MCU
D(0–7)
I
D/C
NTXA
TXR
CK
NRXA
RXR
FE
16XCK
D(0–7)
I
D/C
NTXA
TXR
CK
DETI
I
D/C
NRXA
RXR
FE
CK
Parallel–Serial/
Encoder
DOUT
Serial–Parallel/
Decoder
DIN
TXD
RCD
For More Information On This Product,
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Freescale Semiconductor, Inc.
Figure 6. Encoder
U1
D/C
9
U5D
8
74HC04A
V CC
D7
D6
14
15
1
2
3
4
5
6
7
SER
A
B
C
D
E
F
G
H
QH 9
CK
NTXA
CK
CK
11
13
10
12
SRCLK
SRLOAD
SRCLR
RCLK
74HC597A
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Freescale Semiconductor, I
D(0–7)
I
V CC
V CC
11
CK
U5E
10
74HC04A
3
4
5
6
7
10
2
9
1
A
B
C
D
ENP
ENT
CLK
LOAD
CLR
U3
D5
D4
D3
D2
D1
D0
QA
QB
QC
QD
RCO
14
13
12
11
15
14
15
1
2
3
4
5
6
7
11
13
10
12
U24C
8
74HC32A
SER
A
B
C
D
E
F
G
H
SRCLK
SRLOAD
SRCLR
RCLK
10
9
74HC04A
U2
74HC597A
U5F
13 12
QH 9
11
U15D
74HC86A
13
12
5 k
C17
C23
R13
U24D
11
74HC32A
2200 p
4700 p
13
12
V CC
U4B
74HC109 11
14 PR 10
J
Q
CK
12
CLK
13
9
K
Q
CL
15
DOUT
TXR
74HC163A
Figure 7 illustrates the encoding scheme which was
developed for this purpose. Four additional bits surround a
data byte: the I bit, I bit, D/C bit and D/C bit. The function of
these bits are:
I (Invert) Bit: A logic low on this bit indicates that the data
byte and D/C bit are in true form. A logic high on this bit
indicates that the data byte and D/C bit are complemented
from their original form.
I (Invert Bar) Bit: Just the complement of the I bit.
D/C (Data/Control) Bit: A logic low on this bit indicates
that the data byte should be interpreted as a control word. A
logic high on this bit indicates that the data byte contains real
data.
D/C (Data/Control): Just the complement of the D/C bit.
Figure 7.
D/C I I D0 D1 D2 D3 D4 D5 D6 D7 D/C D/C I
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This encoding scheme allows for the representation of 256
unique data words and 256 unique control words. The control
byte $h00 is reserved and referred to as the idle byte.
When the Parallel–Input/Serial–Output (PISO) register is
ready to transmit a data byte (TXR asserted), a check is
made to see if real data has been transferred into the Serial
Communications Interface (SCI) data register of the MCU. If
data has been received, the data byte will be read, and the
initial state of D/C will be set to 1. If data has not been
received, the data byte will be set to $h00 (the idle byte) and
the initial state of D/C will be set to 0.
Next, the data byte is examined for a DC component. Each
0 bit of the data byte represents –1 and each 1 bit of the data
byte represents +1. All of these values are summed together:
a negative result indicates a low DC component, zero
indicates no DC component, and a positive (non–zero) result
indicates a high DC component. This component is
compared to a cumulative sum (which may be negative, zero,
or positive) and the following actions are taken:
If the current DC component sum is negative, and the
cumulative sum is positive or zero
OR
if the current DC component sum is positive or zero and the
cumulative sum is negative
THEN
clear the I bit (I=0). The new cumulative sum is equal to the
old cumulative sum plus the current sum.
OTHERWISE
set the I bit (I=1). The new cumulative sum is equal to the old
cumulative sum minus the current sum.
If the I bit is set, the contents of the data byte and D/C bit
are complemented.
The updated value of the I bit, data byte, and D/C bit are
placed on the PISO, and a transmission acknowledge signal
(NTXA) is asserted. Please note, the net effect of the DC
component contributed by the I and I bits and D/C and D/C
bits will always equal zero.
An analysis of this encoding scheme brings to light a few
interesting observations:
1) The average DC component over time will approach zero.
2) The minimum frequency component which will be
observed in the data stream will equal 1/(2 x
transmitted bit period x 10).
Freescale Semiconductor, Inc.
3) The maximum (fundamental) frequency component which
will be observed in the data stream will equal 1/(2 x
transmitted bit period).
4) A sequence of ten consecutive zeros or ones indicates the
presence of an idle byte.
Item 4 is perhaps the most interesting observation, since it
will allow the receiver to synchronize the incoming data and
align the serial stream on a byte–wide basis.
TRANSMITTING FREQUENCY for ENCODED DATA
For RS–232 communications which take the form of one
start bit, eight data bits, no parity, and one stop bit, the SCI
will receive 10 bits of data to represent one actual data byte.
For our encoding scheme, 12 bits must be transmitted for
each data or control byte received. If the transmit pipeline is
set to a frequency of at least 1.2 times the SCI receive
pipeline, the receive bandwidth will not have to be reduced
(i.e. no stop or hold conditions would be required).
In actual practice, the transmit pipeline was set to a
frequency 25% greater than the receive pipeline. As a result,
at a minimum, there will be at least one idle byte transmitted
for every 24 real data bytes. This useful feature allows the
receiver to re–synchronize from time to time.
ADDITIONAL FEATURES
As mentioned above, the opportunity presents itself to
transmit a control word (the idle byte just being a special case
of a control word) from time to time. With 255 control words
remaining, various special features can be built into the link,
all transparent to the actual RS–232 data communications.
One of the more obvious features which can be
implemented is hardware (RTS/CTS) flow control. The RTS
signal (for the baseset) and CTS signal (for the handset) can
be monitored and transmitted/received and interpreted by the
link. The latency will mostly be a function of the overhead
bandwidth.
Other features which can be implemented include, but are
not limited to:
Remote channel changing
Adaptive channel selection
Acknowledgments
DCD/DSR, etc. commands
CRC or other error checking
Half duplex handshaking
Power conservation modes
For More Information On This Product,
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Freescale Semiconductor, Inc.
Figure 8. Decoder
V CC
U16
DIN
16XCK
16XCK
V CC
U14A
74HC109 5
2 PR 6
J
Q
4
CLK
3
7
K
Q
CL
1
16XCK
U14B
74HC109 11
14 PR 10
J
Q
12
CLK
13
9
K
Q
CL
15
1
U15A
2
74HC86A
16XCK
3
V CC
3
4
5
6
7
10
A
B
C
D
ENP
ENT
2
CLK
9
LOAD
1
CLR
74HC163A
QA
QB
QC
14
13
12
11
QD
15
RCO
RCLK
(Recovered CK)
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Freescale Semiconductor, I
1
RDAT
(Recovered Data)
RCLK
V CC
RCLK
V CC
3
4
5
6
7
10
2
9
1
A
B
C
D
ENP
ENT
CLK
LOAD
CLR
V CC
U17A
74HC109 5
2 PR 6
J
Q
4
CLK
3
7
K
Q
CL
1
U21
74HC163A
QA
QB
QC
14
13
12
11
QD
15
RCO
V CC
RCLK
9
1
10
2
16XCK
V CC
U24A
74HC32A
U15C
74HC86A
3
8
V CC
U17B
74HC109 11
14 PR 10
J
Q
12
CLK
13
9
K
Q
CL
15
V CC
U19A
74HC109 5
2 PR 6
J
Q
4
CLK
3
7
K
Q
CL
1
4
5
U15B
74HC86A
RCLK
6
14
RCLK 11
V 10 CC
12
13
V CC
V CC
SER
SRCLK
SRCLR
RCLK
G
U20
3
4
5
6
7
10
2
9
1
74HC595A
A
B
C
D
QA
QB
QC
QD
QE
QF
QG
QH
QH ′
1
4
ENP
ENT
CLK
LOAD
CLR
2
5
U18
74HC163A
15
1
2
3
4
5
6
7
9
74HC86A
U23B
74HC86A
QA
QB
QC
14
13
12
11
QD
15
RCO
6
D7
D6
D5
D4
D3
D2
V CC
U19B
74HC109 11
14 PR 10
J
Q
12
CLK
13
9
K
Q
CL
15
14
RCLK 11
10
V CC
12
13
U23A
9
U23C
V CC 8
3
10
74HC86A
12
13
U23D
74HC86A
SER
SRCLK
SRCLR
RCLK
G
11
U22
D(0–7)
74HC595A
QA
QB
QC
QD
QE
QF
QG
QH
QH ′
15
1
2
3
4
5
6
7
9
D1
D0
4
U24B
6
5
74HC32A
RXR
D/C
D(0–7)
I
NRXA
FE
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Figure 8 illustrates a possible implementation of the digital
decoder section of the design.
Received data is “squared up” by the data slicer of the
MC33411 baseband IC. The transmitted data is generally
frequency limited in order to preserve bandwidth (i.e.
low–pass filtered). Because of this limiting, as well as noise
components and hysteresis in the data slicer, the duty cycle
of the received data stream can vary substantially from that
of the transmitted data. For this reason, a data and clock
recovery block is utilized which oversamples the incoming
data (digital noise filtering) and captures the embedded
clock.
Once the clock and data have been recovered, they are
presented to the Serial–Input/Parallel–Output (SIPO)
register. Data is transferred into the register every 12 bits,
this representing the I, I, data byte, D/C and D/C bits. Another
circuit analyzes the serial data stream looking for ten
consecutive bits without a transition. If this condition is
observed, it indicates an idle byte has been received, and the
SIPO register clock can be synchronized.
When the SIPO register indicates that a byte has been
received (RXR asserted), the MCU asserts an
acknowledgement (NRXA), loads the data byte, the I bit and
D/C bit from the bus. At this time, a comparison is made
which verifies that the I bit is the complement of the I bit and
the D/C bit is the complement of the D/C bit. If either of these
conditions is not met, a framing error has occurred and the
received data is simply ignored.
If a valid byte has been received, the MCU checks the
status of the I bit. If the I bit is set, the byte, as well as the D/C
Freescale Semiconductor, Inc.
bit, is complemented. Next, the MCU checks the value of the
updated D/C bit; a logic zero indicates a control word, and the
MCU can take appropriate action.
If the D/C bit indicates real data has been received, the
data is placed on an internal First–In/First–Out (FIFO)
memory stack. The SCI transmitter is checked: if empty, the
next data byte is placed into the SCI transmitter and if full, the
data will be transferred at a later time.
As can be seen, the decoding of the data is a relatively
simple task. If desired, the MCU can consider the lack of an
idle byte, within a given period of time or reception of some
number of bytes, an indication that the RF link has failed.
Again, this condition can be used to re–initialize the RF link,
or other courses of action can be taken.
SUMMARY
This application note has described a robust, full featured
RS–232 wireless interface which can be implemented with
an inexpensive MCU. For slower data rates, it is possible to
eliminate all of the external “glue logic” shown in this note. A
plethora of additional features can be added by the use of
embedded control words which are transparent to the actual
data transceiver.
Motorola’s inexpensive and easy to use ISM Band RF
chipset is easily capable of accomplishing the wireless
portion of the task as long as the digital information presented
to the transmitter and receiver have been properly
preconditioned prior to modulation and demodulation.
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Freescale Semiconductor, Inc.
Table 1.
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Freescale Semiconductor, I
Baseband
Register
Address
Handset
Value
Transmit
Frequency
(MHz)
Receive
Frequency
(MHz)
Baseset
Value
Transmit
Frequency
(MHz)
Receive
Frequency
(MHz)
$h01 $h004822 925.0 – $h004686 903.0 – 0
$h02 $h004C27 – 903.0 $h004E03 – 925.0 0
$h01 $h004827 925.5 – $h00468B 903.5 – 1
$h02 $h004C2C – 903.5 $h004E08 – 925.5 1
$h01 $h00482C 926.0 – $h004690 904.0 – 2
$h02 $h004C31 – 904.0 $h004E0D – 926.0 2
$h01 $h004831 926.5 – $h004695 904.5 – 3
$h02 $h004C36 – 904.5 $h004E12 – 926.5 3
$h01 $h004836 927.0 – $h00469A 905.0 – 4
$h02 $h004C3B – 905.0 $h004E17 – 927.0 4
$h03 $h0E0276 – – $h0E0276 – – X
$h04 $h160070 – – $h160070 – – X
$h05 $h000010 – – $h000010 – – X
$h06 $h0000FF – – $h0000FF – – X
$h07 $h01C000 – – $h01C000 – – X
Channel
Number
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
Mfax is a trademark of Motorola, Inc.
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