PCM-2 Manual.pdf - Voss Associates

Circuit Description
Processor
An 80CS1, supported by 64K of program storage and 32K of working RAM
provides control and computational abilities. Three additional 32K banks of RAM
are installed to provide a large buffer for history data. By using RAM sockets
which contain lithium batteries, backup power may be supplied for data retention
during power outages.
The front panel board is based on an Intel 80CS1 microprocessor. This device
can support up to 64K of external RAM and 64K of ROM. All I/O devices are
also mapped into external memory space. A bi-directional data bus is present on
pins 32-39 of the processor. These pins are also used to output the eight
low-order address bits at the beginning of each external memory cycle; the
74HC373 at A18 is used to latch this portion of the address under control of the
ALE (Address Latch Enable) output on pin 30 of the processor chip. The eight
high-order address bits are sourced directly from pins 21-28.
Instruction and data fetches from the EPROM (A4) are performed when the
processor's PSEN output (pin 29) is active (low). A logic high on this pin
indicates that a RAM or I/O access is in process. RAM in the low 32K of
address space always corresponds to memory chip AS. Addresses from
8000-FFFF (hexadecimal) may be mapped to any of the three remaining RAM
chips (A6, A7 or A8) or to the I/O devices. This selection is made by parallel
output pins 14 and 15 of the microprocessor chip.
Serial Ports
Four serial ports are available. The first, which uses the CPU's internal UART,
is buffered to/from RS-48S levels on pins 1 and 2 of PI by A14. These pins are
connected to the PCM-2's main internal data bus and provide conununications
between the front panel and main computer. Three other serial ports are
implemented by A1S, A16 and A17, which are Intel 82510 conmmnications
controller chips. All baud rates are generated from the microprocessor's crystal
oscillator. By installing appropriate interface driverlreceiver chips or jumpers,
each may be configured for either TTL or RS-232 levels, and supports DSRIDTR
handshaking. One of the three may also be configured as a second RS-48S port.
A15 is buffered by A26 to RS-232 levels on connector P2. This port is used for
the badge reader options and, in addition to the serial data and handshaking lines,
includes two parallel inputs on pins 1 and 9 which may be jumpered low to
indicate the presence and type of badge reader in use. Power and ground for the
reader are also provided. By installing a set of jumpers in place of A26, this port
may optionally be configured for TTL levels rather than RS-232; this is required
by some readers.
11-2
PCM2.MAN/ Hev A/April 1~%