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2010
contents
Foreword .......................................................................................................................................................................... vii
Keynote address [abstract] .............................................................................................................................................. ix
PLATFORM TECHNICAL PRESENTATIONS
BTI
(Invited) On the universality of negative bias temperature degradation [abstract]
A. Alam, S. Mahapatra, A.E. Islam, and A. Jain ............................................................................................................ 1
On the ‘permanent’component of NBTI
T. Grasser, Th. Aichinger, H. Reisinger, J. Franco, P.-J. Wagner, M. Nelhiebel, C. Ortolland, and B. Kaczer ...... 2
Recovery of negative and positive bias temperature stress in pMOSFETs
Ph. Hehenberger, H. Reisinger, and T. Grasser ............................................................................................................. 8
The impact of recovery on BTI reliability assessments
H. Reisinger, T. Grasser, K. Hofmann, W. Gustin, and C. Schlünder..........................................................................12
Correlation between dielectric traps and BTI characteristics of high-k/ metal gate MOSFETs
J.Q. Yang, J.F. Yang, J.F. Kang, X.Y. Liu, R.Q. Han, P. Kirsch, H.-H. Tseng, and R. Jammy .................................17
Fabless & Foundry Interaction
(Invited) Requirement of effective fabless/foundry interactions for achieving robust
product reliability [abstract]
S. Kalpat ...........................................................................................................................................................................22
(Invited) Foundry reliability engineering requirements & challenges [abstract]
W.L. Ng ..............................................................................................................................................................................23
Photovoltaics
(Invited) Photovoltaic module reliability: Enduring a storm [abstract]
Glen Alers .........................................................................................................................................................................24
SER
(Invited) Soft errors – past history and recent discoveries
C. Slayman ........................................................................................................................................................................25
B10 Finding and correlation to thermal neutron soft error rate sensitivity for SRAMs in the sub-micron
technology
S.-J. Wen, S.Y. Pai, R. Wong, M. Romain, and N. Tam ..................................................................................................31
Alpha emission of fully processed silicon wafers
R. Wong, S.-J. Wen, P. Su, and B. Dwyer-McNally .......................................................................................................34
BEOL
Defects in low-k dielectrics and etch stop layers for use as interlayer dielectrics in ULSI
B.C. Bittel, T.A. Pomorski, P.M. Lenahan, and S. King ...............................................................................................37
Copper - top interconnect reliability for mixed signal applications
J. Kim, B. O’Connell, W. K. Teng, and M.W. Poulter ...................................................................................................42
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Effect of reservoir on electromigration of short interconnects
P. Lamontagne, D. Ney, and Y. Wouters ........................................................................................................................46
Investigation into the effect of a "Through silicon via" process on the MOS transistor reliability of
a standard 0.13�m CMOS technology
A. Martin, L. Borucki, H. Reisinger, and C. Schlunder ...............................................................................................51
Transistor
Impact of body tie and Source/Drain contact spacing on the hot carrier reliability of 45nm RF-CMOS
R. Arora, K. A. Moen, A. Madan, J.D. Cressler, E. Zhang, D.M. Fleetwood, R.D. Schrimpf,
A.K. Sutton, and H.M. Nayfeh .........................................................................................................................................56
Multiple microscopic defects characterization methods to improve macroscopic degradation
modeling of MOSFETs
Y.M. Randriamihaja, A. Bravaix, V. Huard, D. Rideau, M. Rafik, and D. Roy ..........................................................61
MOS transistor characteristics and its dependence of plasma charging degradation on the test
structure layout of a 0.13�m CMOS technology
A. Martin, R.-P. Vollertsen, and H. Reisinger..............................................................................................................67
Hot carrier impact on the small signal equivalent circuit
L. Negre, D. Roy, S. Boret, P. Scheer, N. Kauffmann, D. Gloria, and G. Ghibaudo .......................................................................................72
Reliability
‘Atomistic’ simulation of RTS amplitudes due to single and multiple charged defect states and
their interactions
M. F. Bukhori, T. Grasser, B. Kaczer, H. Reisinger, and A. Asenov ...........................................................................76
Stability and bias stressing of metal/insulator/metal diodes
N. Alimardani, J.F. Conley, Jr., E. W. Cowell III, J.F. Wager, M. Chin., S. Kilpatrick., and M. Dubey ................80
Product Reliability
(Invited) Qualifying reliable systems from unreliable components [abstract]
Amr Haggag .....................................................................................................................................................................85
Memory
Single bit read disturb failure mechanism and transistor size optimization for dual port SRAM
bitcell in embedded NVM process SOC applications
S.-R. Kim,K.J. Han, K.-S. Lee, T.-H. Kim, J. Wolfman, Y. Wang, B. Schmit, K. Hauch, H. Kim,
P.-Y. Lee, E. Minh, Y. Jia, F. Dhaoui, P. Liu, and H.-C. Tseng ....................................................................................86
Characterization of anomalous erase effects in 48 nm TANOS charge trapping memory cells
D.-A. Loehr, R. Hoffmann, A. Naumann, J. Paul, K. Seidel, M. Czernohorsky, and V. Beyer ..................................89
Cycling induced degradation of a 65nm FPGA flash memory switch
B.A. Schmid, J.Y. Jia, J. Wolfman, Y. Wang, F. Dhaoui, H.-C. Tseng, S.-R. Kim, K.-S. Lee, P. Liu,
K.J. Han, and C. Hu .........................................................................................................................................................92
Impact of the storage layer charging on random telegraph noise behavior of sub-50nm
charge-trap-based TANOS and floating-gate memory cells
K. Seidel, R. Hoffmann, A. Naumann, J. Paul, D.A. Löhr, M. Czernohorsky, and V. Beyer ......................................95
POSTER PRESENTATIONS—REFEREED
Evaluation of x-ray irradiation defect on 65nm multi-level cell NOR flash technologies
P. Navuduri, W. Melton, A. Oen, S. Eilert, C. Abraham, and S.-J. Wen ......................................................................98
A novel virtual age reliability model for time-to-failure prediction
Y. Wang and S.D. Cotofana.......................................................................................................................................... 102

2010
Downstream electromigration improvement in 45nm technology
Y. Zhao, X. Zeng, W. Liu, F. Zhang, and Y.K. Lim ...................................................................................................... 106
Evaluation on the reliable operation of a gate-level pipelined self synchronous system against PVT
and aging
B. Devlin, M. Ikeda, and K. Asada .............................................................................................................................. 110
Memory reliability model for accumulated and clustered soft errors
S.Y. Lee, S. Baeg, and P. Reviriego ............................................................................................................................. 114
An empirical model describing the MLC retention of charge trap flash memories
T. Melde, R. Hoffmann, E. Yurchuk, J. Paul, and T. Mikolajick .............................................................................. 118
TDDB chip reliability in copper interconnects
M. Bashir, D.H. Kim, S.K. Lim, and L. Milor .............................................................................................................. 121
Degradation of sub-micron gate AlGaN/GaN HEMTs due to reverse gate bias
E.A. Douglas, C.-Y. Chang, T. Anderson, J. Hite, L. Lu, C.-F. Lo, B.-H. Chu, D.J. Cheney, B.P. Gila,
F. Ren, G.D. Via, P. Whiting, R. Holzworth, K.S. Jones, S. Jang, and S.J. Pearton ............................................... 125
SRAM Cell reliability degradations due to cell crosstalk
J. Bae, S. Baeg, S.-J. Wen, and R. Wong ..................................................................................................................... 129
The effect of Radon on soft error rates for wire bonded memories
R. Wong, P. Su, S.-J. Wen, B. Dwyer-McNally, and S. Coleman ............................................................................... 133
Understanding the influence of antifuse bitcell dimensions on the programming time and energy using
an analytical model
M. Deloge, B. Allard, P. Chandelier, J. Damiens, E. Le-Roux, and M. Rafik ......................................................... 135
Insights about reliability of heterojunction bipolar transistor under DC stress
F. Cacho, S. Ighilahriz, M. Diop, D. Roy, and V. Huard ........................................................................................... 139
New DRAM HCI qualification method emphasizing on repeated memory access
P.C.-F. Chia, S.-J. Wen, and S.H. Baeg ....................................................................................................................... 142
Qualification of 128 Gb MLC NAND flash for space application
J. Heidecker, M. White, M. Cooper, D. Sheldon, F. Irom, and D. Nguyen .............................................................. 145
3D Simulation of charge collection and SEU of 0.13�m partially depleted SOI SRAM
X. Zhang, S. Yue, L. Wang, and J. Li ........................................................................................................................... 149
RAAPS: Reliability Aware ArchC based Processor Simulator
T. Gupta, C. Bertolini, O. Heron, N. Ventroux, T. Zimmer, and F. Marc ................................................................. 153
Design-in reliability for over drive applications in advanced technology
J.-G. Ahn, P.-C. Yeh, J. Sowards, N. Lo, and J. Chang ............................................................................................. 157
Improved evaluation of DRAM transistors and accurate resistance measurement for real chip contacts
by nano-probing technique
H. Park, K. Chae, S. Yamada, H.-S. Kuh, and B. Choi .............................................................................................. 161
Complexities of the non-volatile memory reliability testing caused by the test structure
A.A. Keshavarz, G.S. Spawn, N.D. Reyes, R. Mincitar, and L.F. Dion .................................................................... 164
Tutorial Abstracts
Reliability of III-V semiconductors/GaN
Michael Dammann ........................................................................................................................................................ 168
NBTI
Hans Reisinger .............................................................................................................................................................. 168
Radiation-induced soft errors: Status quo and key challenges
Norbert Seifert .............................................................................................................................................................. 169
BEOL
James R. Lloyd ............................................................................................................................................................... 169
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Hot carriers
Alain Bravaix ................................................................................................................................................................ 170
TDDB physics: Transitioning from silica to high-k gate dielectrics
Joe McPherson ............................................................................................................................................................... 170
Discussion Group (DG) and Special Interest Group (SIG) Summaries
DG: High-k ..................................................................................................................................................................... 171
DG: NBTI ........................................................................................................................................................................ 172
DG: BEOL ....................................................................................................................................................................... 172
DG: Product reliability ................................................................................................................................................... 173
DG: fast Wafer Level Reliability (fWLR) monitoring .................................................................................................. 174
SIG: fast Wafer Level Reliability (fWLR) monitoring ................................................................................................. 176
BIOGRAPHIES.................................................................................................................................................................... 177
PICTURES .......................................................................................................................................................................... 180

2009
2009
2009
contents
Foreword ...................................................................................................................................................................................... vii
Keynote address abstract ............................................................................................................................................................. ix
PLATFORM TECHNICAL PRESENTATIONS
Reliability
Investigation of SILC via energy resolved spin dependent tunneling spectroscopy
J.T. Ryan, P.M. Lenahan, A.T. Krishnan, and S. Krishnan ...................................................................................................... 1
New failure mechanism during high temperature storage testing and its application on SIV risk evaluation
O. Aubel, W. Yao, M.A. Meyer, H.J. Engelmann, J. Poppe, F. Feustel, and C. Witt............................................................. 5
Memory
Electric field dependent switching and degradation of resistance random access memory
K. Hosotani, S.-G. Park, and Y. Nishi ...................................................................................................................................... 11
Threshold voltage (V t ) instability in high bit-count-per-cell floating-gate non-volatile memories
G. Tao and J. Yang ..................................................................................................................................................................... 15
A fast WLR test for the evaluation of EEPROM endurance
A. Uhlemann, A. Aal, and H. Vogt ............................................................................................................................................ 20
NBTI-1
(Invited) Reassessing NBTI mechanisms by ultrafast charge pumping measurement
D.S. Ang, Z.Q. Teo, and C.M. Ng .............................................................................................................................................. 25
A study of NBTI by the statistical analysis of the properties of individual defects in pMOSFETS
H. Reisinger, T. Grasser, and C. Schlünder............................................................................................................................. 30
On the thermal activation of negative bias temperature instability
R.G. Southwick III, W.B. Knowlton, B. Kaczer, and T. Grasser ............................................................................................ 36
What triggers NBTI? An “On The Fly” electron spin resonance approach
J.T. Ryan, P.M. Lenahan, T. Grasser,and H. Enichlmair ..................................................................................................... 42
Future Technology–1
(Invited) Interfacial engineering of InGaAs/high-k metal-oxide-semiconductor field effect
transistors (MOSFETs)
A.M. Sonnet, R.V. Galatage, M.N. Jivani, M. Milojevic, R A. Chapman, C.L. Hinkle, R. M. Wallace and E.M. Vogel ............46
(Invited) Instabilities in oxide semiconductor transparent thin film transistors
J.F. Conley, Jr............................................................................................................................................................................. 50
Back-end Reliability
Cu interconnect immortality criterion based on electromigration void growth saturation
P. Lamontagne, L. Doyen, E. Petitprez, D. Ney, L. Arnaud, P. Waltz, and Y. Wouters ..........................................................56
Comprehensive characterization of BEOL-TDDB performance using very fast voltage ramp dielectric
breakdown tests
O. Aubel, F. Feustel, T. Hoffmann, M. Majer, and K.Yiang......................................................................................................60
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Transistor
Application of fast wafer-level reliability PBTI tests for screening of high-k / metal gate process splits
G. Krause, R. Geilenkeuser, M. Trentzsch, F. Graetsch, and L. Herrmann ............................................................................66
Impact of instrumental current scatter on fast Bias Temperature Instability testing
A. Kerber, K. Zhao, B.P. Linder, and E. Cartier .......................................................................................................................70
A fast, simple wafer-level Hall-mobility measurement technique
L.C. Yu, K.P. Cheung, V. Tilak, G. Dunne, K. Matocha, J.P. Campbell, J.S. Suehle, and K. Sheng ...................................73
Comprehensive analysis of the degradation of a lateral DMOS due to hot carrier stress
E. Riedlberger, C. Jungemann, A. Spitzer, M. Stecher, and W. Gustin................................................................................. 77
Simulation of statistical aspects of reliability in nano CMOS
M.F. Bukhori, A.R. Brown, S. Roy, and A. Asenov ....................................................................................................................82
Bias stability of zinc-tin-oxide thin film transistors with Al O gate dielectrics
2 3
J. Triska, J.F. Conley, Jr., R. Presley, and J.F. Wager ............................................................................................................86
NBTI-2
A radically different model for NBTI in nitrided oxide MOSFETs
P.M. Lenahan .............................................................................................................................................................................. 90
Analytical solution of the switching trap model for negative bias temperature stress
B. Bindu, W. Goes, B. Kaczer, and T. Grasser ........................................................................................................................ 93
Future Technology-2
Self-compensating the effect of defect generation for advanced CMOS substrates
A.E. Islam and M.A. Alam.......................................................................................................................................................... 97
The critical role of the defect structural relaxation for interpretation of noise measurements in MOSFETs
D. Veksler, G. Bersuker, H. Park, C. Young, K. Y. Lim, W. Taylor, S. Lee, and H. Shin ..................................................... 102
Back-end Reliability-2
Capacitance variation under electrical stress of SiOCH low-k dielectrics for the advanced 45nm technology
node and beyond
M.Vilmay, D. Roy, S.Blonkowski, F. Volpi, and J-M. Chaix ................................................................................................ 106
POSTER PRESENTATIONS—REFEREED
The effect of Cu contamination on device reliability in DRAM
J.W. Pyun, M.S. Jung, H.W. Kim, N.H. Cha, S.J. Hwang, J.S. Kang, and B.S. So ............................................................ 111
Gate oxide integrity by initial gate current
S. Park, S. Hwang, J. Kang, B. So, and D. Baek ................................................................................................................... 113
Methodology for 3-dimensional high-density capacitor reliability evaluation
G. Fiannaca, P. Gardes, L. Berneux, E. Bouyssou, and C. Anceau .................................................................................... 117
Stress voltage dependence HCI induced traps distribution in 60V LDNMOS
S.K. Samanta, N. Patel, K.N. ManjulaRani, and K. Jang ..................................................................................................... 120
Hot-carrier reliability study and simulation methodology development for 65nm technology
K.N. ManjulaRani, R.M. Mooraka, N. Patel, S. Samanta, G. Narasimhan, N. Lakshminarayanan, R. Kapre,
and H. Puchner .......................................................................................................................................................................... 124
The use of Taguchi method for process design of experiment to resolve gate oxide integrity issue
T. Cahyadi, P.Y. Tan, M.T. Ng, T. Yeo, J.J. Boh, and B. Fun .............................................................................................. 128
Effects of various applications on relative lifetime of processor cores
T. Gupta, C. Bertolini, O. Heron, N. Ventroux, T. Zimmer, and F. Marc ............................................................................ 132

2009
The Helium Ion Microscope for interconnect material imaging
W. Thompson, S. Ogawa, L. Stern, L. Scipioni, and J. Notte ................................................................................................ 136
Improvement on erase characteristics of SONOS flash memory by Bandgap Engineering of tunnel oxide
D.H. Li and B.-G. Park ............................................................................................................................................................ 138
fWLR supported process development based on V- and J-ramp stress tests
A. Aal.......................................................................................................................................................................................... 141
Correlation of electrical properties with interface structures of CVD oxide-based oxynitride tunnel dielectrics
Z. Liu, H. Ishigaki, S. Ito, T. Ide, M. Makabe, M. Wilde, K. Fukutani, M. Kimura, V.A. Miha, and H. Yoshikawa ........ 145
IMD stack thermal resistance effects on SiCr thin film resistor’s current density performance
F. Downey .................................................................................................................................................................................. 148
The investigation of the electro-thermal characteristics of a GTO thyristor at turn off using Silvaco Atlas
J. Ciezki, G. Vineyard, T. Weatherford .................................................................................................................................. 151
Effects of statistical thin-oxide thickness variations on the time-dependent dielectric breakdown (TDDB)
parameters for wafer level reliability
A.A. Keshavarz and L.F. Dion ................................................................................................................................................. 155
TCAD analysis of self heating in AlGaN/GaN HEMTs under pulsed conditions
T. Weatherford, Y. Wang, and S. Tracey ................................................................................................................................ 159
An improved fast Id-Vg measurement technology with expanded application range
C. Wang, L.C. Yu, J.P. Campbell, K.P. Cheung, Y. Xuan, P.D. Ye, J.S. Suehle, and D.W. Zhang ...................................... 163
NBTI performance enhancement with process integration of high current fluorine incorporation and
O 2 gas asher process in 45nm CMOS Technology
S. Mahesh, X. Bin, M.F. Karim, S. Yongliang, Li Yu, Zeng Xu, Hung Odd, and Cheng Weihua ...................................... 166
Effect of metal thickness variations on IC metal lifetime due to electromigration
A.A. Keshavarz and L.F. Dion ................................................................................................................................................. 170
TUTORIAL ABSTRACTS
2009
2009
DNA Self-Assembled Nanostructures for Device Applications
Bill Knowlton ............................................................................................................................................................................ 174
International fWLR Monitoring Guideline
Andreas Martin and Andreas Aal .......................................................................................................................................... 174
ESD Protection Design and Qualification Challenges
Charvaka Duvvury ................................................................................................................................................................... 174
NBTI: Why Won’t This Thing Go Away?
Jason P. Campbell ................................................................................................................................................................... 174
BEOL Reliability Challenges and its Interaction with Process Integration
Oliver Aubel .............................................................................................................................................................................. 174
Three Dimensional Systems Integration - Concepts and Challenges
Alan Mathewson ....................................................................................................................................................................... 175
Reliability of Gate Dielectrics in MOSFETs:
A Nanometer Scale Approach with Conductive Atomic Force Microscopy
Montserrat Nafría and Marc Porti ........................................................................................................................................ 175
Degradation and Reliability of Metal Gate / High-k CMOS Technologies
Andreas Kerber ......................................................................................................................................................................... 175
v

DISCUSSION GROUP (DG) SUMMARIES
DG: NBTI .................................................................................................................................................................................... 176
DG: Metal Gate / High-k ............................................................................................................................................................ 177
DG: fast Wafer Level Reliability (fWLR) monitoring .............................................................................................................. 178
DG: Product/Memory Reliability .............................................................................................................................................. 181
BIOGRAPHIES ................................................................................................................................................................................ 182
PICTURES ...................................................................................................................................................................................... 185
2009
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2009
2009

2008
2008
contents
Foreword ............................................................................................................................................................................................. vii
Keynote address abstract ....................................................................................................................................................................ix
PLATFORM TECHNICAL PRESENTATIONS
NBTI–1
The effect of recovery on NBTI characterization of thick non-nitrided oxides
H. Reisinger, R.P. Vollertsen, P.J. Wagner, S. Aresu, W. Gustin, T. Grasser, C. Schlünder ................................................... 1
Total recovery of defects generated by negative bias temperature instability
C. Benard, J.-L. Ogier, and D. Goguenheim............................................................................................................................... 7
Advanced On-The-Fly method with correction of initial values to characterize negative
bias temperature instability reliability
C. Benard, J.-L. Ogier, and D. Goguenheim..............................................................................................................................12
Back-end Reliability
Copper line topology impact on the reliability of SiOCH low-k dielectrics for the advanced
45 nm technology node and beyond
M. Vilmay, D. Roy, C. Monget, F. Volpi, J-M. Chaix ...............................................................................................................16
Impact of oxygen vacancies profile and fringe effect on leakage current instability of tantalum pentoxide
metal-insulator-metal (MIM) capacitors
Vi. Martinez, C. Besset, F. Monsieur, L. Montès, G. Ghibaudo...............................................................................................21
The influence of complex geometries and stress non-uniformity on reliability
A. Aal.............................................................................................................................................................................................25
Stress characterization for stress-induced voiding in Cu/Low K interconnects with geometry and upper
cap layer dependences
M. Lin, J.W. Liang, and K.C. Su .................................................................................................................................................32
Reliability of Sensors/Memories
Ageing under illumination of MOS transistors for active pixel sensors (APS) applications
D. Lopez, F. Monsieur, S. Ricq, J.-M. Roux, and F. Balestra ..................................................................................................36
Investigation of GIDL current Injection disturb mechanism in two-transistor-eNVM memory devices
S.R. Kim, K.J. Han, J. Lee, P.Y. Lee, T. Zhou, K.-S. Lee, P. Liu, H.C. Tseng, B. Cronguist ...................................................40
High-k Reliability
Effect of substrate hot carrier stress on high-k gate stack
H. Park, G. Bersuker, C. Y. Kang, C. Young, H-H Tseng, R. Jammy .......................................................................................44
Temperature (6-300K) dependence comparison of HfO 2 /SiO 2 and SiO 2 MOS gate stacks
R.G. Southwick III, J. Reed, C. Buu, H. Bui, G. Bersuker, W.B. Knowlton .............................................................................48
Positive bias temperature instability effects in advanced high-k / metal gate NMOSFETs
D.P. Ioannou, S. Mittl, G. LaRosa ..............................................................................................................................................55
Breakdown mechanism for the thin EOT Dy 2 O 3 /HfO 2 dielectric
T. Lee, S. Park, J. Lee, S. K. Banerjee ........................................................................................................................................58
2008
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2008
NBTI–2
Geometry effects on the NBTI degradation of PMOS transistors
G. Math, C. Benard, J.-L. Ogier, D. Goguenheim .....................................................................................................................60
Study of transistor and product NBTI lifetime distributions
J. Qin, B. Yan, Y. Shoshany, D. Roy, H. Rahamim, J.B. Bernstein ...........................................................................................64
Reliability of Compound Materials and Devices
Interface traps in silicon carbide MOSFETs
C.J. Cochrane, P.M. Lenahan, A.J. Lelis ...................................................................................................................................68
Effect of threshold-voltage instability on SIC DMOSFET reliability
A.J. Lelis, D. Habersat, R. Green, N. Goldsman ........................................................................................................................72
Coupled approach for reliability study of fully self aligned SiGe:C 250 GHz HBTs
M. Diop, N. Revil, M. Marin, F. Monsieur, T. Schwartzmann, G. Ghibaudo .........................................................................77
fWLR Reliability
Quantitative reliability assessment of plasma induced damage on product wafers with fast WLR measurements
A. Martin, C. Bukethal, K.-H. Rydén, S. Baier, M. Schwerd ....................................................................................................81
Negative bias temperature stress on PFETs within fast wafer level reliability monitoring
R.-P. Vollertsen, H. Reisinger, C. Schlünder ............................................................................................................................86
Late News
Defect creation stimulated by thermally activated hole trapping as the driving force behind negative bias
temperature instability in SiO , SiON, and high-k gate stacks
2
T. Grasser, B. Kaczer, T. Aichinger, W. Gös, and M. Nelhiebel ..............................................................................................91
The effect of the subthreshold slope degradation on NBTI device characterization
D. Brisbin and P. Chaparala ......................................................................................................................................................96
Reliability guardband reduction by differential targeting of pMOS gate oxide thickness
R. Geilenkeuser, K. Wieczorek, M. Trentzsch, F. Graetsch, B. Bayha, V. Samohvalov, T. Paetzold, and T. Schink ...... 100
The origins of random telegraph noise in highly scaled SiON nMOSFETs
J.P. Campbell, J. Qin, K.P. Cheung, L. Yu, J.S. Suehle, A. Oates, and K. Sheng ............................................................... 105
POSTER PRESENTATIONS—REFEREED
Repeatability and stress level dependence on ESD-CDM testing for microelectronic components
Y. Satirakul, T. Butngam, and S. Phunyapinuant ................................................................................................................. 110
Concept and implementation of an in-situ test structure for HTGS reliability testing of Power FETs on
a wafer level basis
S. Baier....................................................................................................................................................................................... 114
Fully automatical test and qualification system for a high endurance embedded EEPROM module
J. Fellner, G. Schatzberger, and A. Wiesner .......................................................................................................................... 118
A robust single event upset hardened clock distribution network
A.S. Mallajosyula and P. Zarkesh-Ha .................................................................................................................................... 121
Reliability simulation and design consideration of high speed ADC circuits
B. Yan, J. Qin, J. Dai, Q. Fan, and J.B. Bernstein.................................................................................................................. 125
Dispersion and the worst case of thermal fatigue life of solder joints in vehicle electronic devices
T. Maruoka, Q. Yu, T. Shibutani, and H. Miyauchi ............................................................................................................... 129
A comparison between V-ramp TDDB techniques for reliability evaluation
A. Aal.......................................................................................................................................................................................... 133
An electrically-detected magnetic resonance study of the atomic-scale effects of fluorine on the
negative bias temperature instability
J.T. Ryan, P.M. Lenahan, A.T. Krishnan, S. Krishnan, J.P. Campbell ............................................................................... 137
2008

2008
Oxide reliability of SiC MOS devices
L. Yu, K.P. Cheung, J. Campbell, J.S. Suehle, and K. Sheng ............................................................................................... 141
TUTORIAL ABSTRACTS
Circuit Failure Prediction for Robust System Design in Scaled CMOS
Subhasish Mitra. ....................................................................................................................................................................... 145
Measurement Issues for High-k Technology including NBTI
Chadwin Young ........................................................................................................................................................................ 145
JEDEC Overview
Alvin Strong .............................................................................................................................................................................. 145
Toward Understanding Negative Bias Temperature Instability
Tibor Grasser ............................................................................................................................................................................ 145
eFuse Design and Reliability
William Tonti ............................................................................................................................................................................. 145
Reliability of “Future” Devices
Wilfried Haensch ....................................................................................................................................................................... 145
DISCUSSION GROUP (DG) REPORTS
2008
DG: fast Wafer Level Reliability (fWLR) monitoring .............................................................................................................. 146
DG: NVM reliability ................................................................................................................................................................... 150
DG: NBTI .................................................................................................................................................................................... 151
DG: Dielectric electrical characterization ................................................................................................................................. 152
DG: Product reliability............................................................................................................................................................... 153
BIOGRAPHIES ................................................................................................................................................................................ 154
PICTURES ...................................................................................................................................................................................... 157
2008
v

2007
2007
contents
Foreword ............................................................................................................................................................................................. vii
Keynote address abstract .................................................................................................................................................................... ix
PLATFORM TECHNICAL PRESENTATIONS
A new smart V th -extraction methodology considering recovery and mobility degradation due to NBTI
C. Schlünder, M. Hoffmann, R.-P. Vollertsen, G. Schindler, W. Heinrigs, W. Gustin, H. Reisinger .............................................1
A rigorous study of measurement techniques for negative bias temperature instability
T. Grasser, P.-J Wagner, P. Hehenberger, W. Gös, B. Kaczer ...........................................................................................................6
Atomic-scale defects involved in NBTI in plasma-nitrided pMOSFETs
J.P. Campbell, P.M. Lenahan, A.T. Krishnan, S. Krishnan ............................................................................................................ 12
Effect of NBTI degradation on transistor variability in advanced technologies
S. Pae, J. Maiz, C. Prasad .................................................................................................................................................................. 18
Enhanced PMOS NBTI degradation due to halo implant channeling in a DGO CMOS process
D. Brisbin, J. Yang, S. Bahl, C. Parker ............................................................................................................................................ 22
Charging and discharging of oxide defects in reliability issues
W. Gös, T. Grasser ............................................................................................................................................................................... 27
SRAM stability analysis considering gate oxide SBD, NBTI and HCI
J. Qin, X. Li, J.B. Bernstein ................................................................................................................................................................ 33
Investigation of NBTI recovery induced by conventional measurements for pMOSFETs
with ultra-thin SiON gate dielectrics
L. Jin, M. Xu ........................................................................................................................................................................................ 38
Charge-gain program disturb mechanism in split-gate flash memory cell
V. Markov, K. Korablev, A. Kotov, X. Liu, Y.B. Jia, T.N. Dang, A. Levi ....................................................................................... 43
Scaling tunneling oxide to 50Å in floating-gate logic NVM at 65nm and beyond
B. Wang, M. Niset, Y. Ma, H. Nguyen, R. Paulsen........................................................................................................................... 48
A simple and accurate method to extract neutral threshold voltage of floating gate flash devices
and its application to flash reliability characterization
G. Tao, H. Chauveau, D. Boter, D. Dormans, R. Verhaar ............................................................................................................... 52
New approach for the assessment of the effect of plasma induced damage on MOS devices
and subsequent design manual rules
A. Martin.............................................................................................................................................................................................. 57
Charge pumping revisited – the benefits of an optimized constant base level charge pumping
technique for MOS-FET analysis
T. Aichinger, M. Nelhiebel ................................................................................................................................................................. 63
Characterization and analysis of gate-induced-drain-leakage current in 45nm CMOS technology
X. Yuan, J.-E. Park, J. Wang, E. Zhao, D. Ahlgren, T. Hook, J. Yuan, V. Chan, H. Shang, C.-H. Liang,
R. Lindsay, S. Park, H. Choo ............................................................................................................................................................. 70
Electromigration multistress pattern technique for copper drift velocity and Black’s parameters extraction
L. Doyen, X. Federspiel,L. Arnaud, F. Terrier, Y. Wouters, V. Girault .......................................................................................... 74
2007
iii

iv
Optimized structure design for wafer level electromigration tests
X. Federspiel, D. Ney, G. Sers, L. Doyen........................................................................................................................................... 79
Programming conditions for silicided poly-Si or copper electrically programmable fuses
H. Suto, S. Mori, M. Kanno, N. Nagashima ..................................................................................................................................... 84
Reliability investigation of NiPtSi electrical fuse with different programming mechanism
C. Tian, D. Moy, B. Messenger, C. Kothandaraman, J. Safran, S. Wu, N. Robson, S.S. Iyer ....................................................... 90
Defects in the interfacial layer of SiO 2 -HfO 2 gate stacks: Depth distribution and identification
O. Ghobar, D. Bauza, B. Guillaumot................................................................................................................................................. 94
Charge trapping of ultra-thin ZrHfO x /RuO x /ZrHfO x high-k stacks
R. Wan, C.-H. Lin, Y. Kuo, W. Kuo ..................................................................................................................................................... 99
New defect generation in nitrogen contented nMOS high-k devices
D. Heh, P.D. Kirsch, C.D. Young, C.Y. Kang, G. Bersuker .............................................................................................................103
Direct observation of electrically active interfacial layer defects which may cause threshold voltage
instabilities in HfO 2 based MOSFETs
J.T. Ryan, P.M. Lenahan ...................................................................................................................................................................107
Characterization of interface and bulk oxide traps in SiC MOSFETs with epitaxialy grown and implanted channels
M. Gurfinkel, J. Kim, S. Potbhare, H.D. Xiong, K.P. Cheung, J. Suehle, J.B. Bernstein, Y. Shapira, A.J. Lelis,
D. Habersat, N. Goldsman ................................................................................................................................................................. 111
POSTER PRESENTATIONS—REFEREED
2007
2007
Investigation of substrate injection disturb mechanism in high density flash FPGA devices
S.R. Kim, N. Chan, B. Sharokhi, H. Micael, J. Yaonan, S. Samiee, K.J. Han, B. Cronquist ......................................................114
Fast wafer level reliability assessment of ultra thick oxides under impact ionization conditions
A. Aal .................................................................................................................................................................................................117
80V HVDMOS reliability characterization for 0.6µm and 0.35µm technologies
C. Heffernan, M. Forde ..................................................................................................................................................................... 121
Comparison of line stress predictions with measured electromigration failure times
R.R. Morusupalli, W.D. Nix, J.R. Patel ...........................................................................................................................................124
Comprehensive hot carrier mechanism investigation of 40V LDNMOS transistor
Y.-C. Wang, Y.-P. Chen, J.-S. Li , K.-C. Su .....................................................................................................................................128
Optimized reliability guardbands using variation aware junction temperature models
P. Pereira, D. Kim, P. O’Shea .......................................................................................................................................................... 132
Process variabilities and performances in a 90nm embedded SRAM
M.Y.S. Min, P. Maurine, M. Bastian, M. Robert............................................................................................................................. 135
A reliability study in p-channel punchthrough for ASIC CMOS I/O buffer leakage
E. Spory.............................................................................................................................................................................................. 139
Impact of DRAM process technology on neutron-induced soft errors
L. Borucki, G. Schindlbeck, C. Slayman ........................................................................................................................................ 143
DC bias effects on data retention at room temperature in SONOS nonvolatile memory devices
J.-M. Hwang, T. Wallinger ............................................................................................................................................................... 147
2007

TUTORIAL ABSTRACTS
Detection of atomic scale defects in MOS reliability problems
P.M. Lenahan ............................................................................................................................................................................ 150
Current issues in SRAM reliability
B. Woolery.................................................................................................................................................................................. 150
Reliability of floating-gate flash memories
N. Mielke ................................................................................................................................................................................... 151
Reliability assessment methodology for high-k gate stacks
G. Bersuker ................................................................................................................................................................................ 151
Beam-based defect localization in ICs
E.I. Cole Jr. ................................................................................................................................................................................ 152
Semiconductor device scaling: general trends and reliability implications for space
A. Johnston ................................................................................................................................................................................ 152
DISCUSSION GROUP (DG) REPORTS
DG: NBTI .................................................................................................................................................................................... 153
DG: High-k dielectric stacks...................................................................................................................................................... 155
DG: Interconnects ..................................................................................................................................................................... 156
DG: Product reliability............................................................................................................................................................... 157
SPECIAL INTEREST GROUP (SIG) REPORT
2007
2007
SIG: fast Wafer Level Reliability (fWLR) Monitoring ............................................................................................................ 159
BIOGRAPHIES ................................................................................................................................................................................ 161
PICTURES ...................................................................................................................................................................................... 164
2007
v

2006
2006
contents
Foreword ....................................................................................................................................................................................... vi
PLATFORM TECHNICAL PRESENTATIONS
On the impact of the NBTI recovery phenomenon on lifetime prediction of modern p-MOSFETs
C. Schlunder, W. Heinrigs, W. Gustin, H. Reisinger................................................................................................................. 1
Modeling of dispersive transport in the context of negative bias temperature instability
T. Grasser, W. Gos, B. Kaczer .................................................................................................................................................... 5
Negative bias stressing interface trapping centers in metal gate hafnium oxide field effect transistors
using spin dependent recombination
C.J. Cochrane, P.M. Lenahan, J.P. Campbell, G. Bersuker, P. Lysaght, A. Neugroschel ................................................ 11
Effects of delay time and AC factors on negative bias temperature instability of PMOSFETs
J-S. Li, M Chen, P. Juan, and K. Su ......................................................................................................................................... 16
Bias stress induced conduction mechanism evolution in silica based inter-metal dielectrics
Y. Li, G. Groeseneken, K. Maex, Z Tõkei ................................................................................................................................. 20
Dynamics of resistance evolution during electromigration
X. Federspiel, D. Ney, L. Doyen, V. Girault .......................................................................................................................... 24
Stress migration phenomena in narrow copper lines
H. Matsuyama et al..................................................................................................................................................................... 28
Impact of TiN plasma post-treatment on alumina electron trapping
A. Bajolet, S. Bruyère, M. Proust, L. Montès, G. Ghibaudo .................................................................................................. 31
Constant-current stressing of SiCr-based thin film resistors: Initial “wearout” investigation
R. Brynsvold, K. Manning .......................................................................................................................................................... 37
Effect of photo misalignment on N-LDMOS hot carrier device reliability
D. Brisbin, P. Lindorfer, P. Chaparala .................................................................................................................................... 44
Ultra-fast measurements of V th instability in SiC MOSFETs due to positive and negative constant bias stress
M. Gurfinkel, J. Suehle, J. Bernstein, Y. Shapira, A.J. Lelis, D. Habersat, N. Goldsman .................................................. 49
Effect of self-heating on HCI lifetime prediction in SOI technologies
J.M. Roux, X. Federspiel, D. Roy .............................................................................................................................................. 54
Reliability characterizations of a 150GHz Ft/Fmax Si/SiGeC heterjunction bipolar transistor
under reverse, forward and mixed-mode stress
M. Ruat, J. Bourgeat, M. Marin, G. Ghibaudo, N. Revil, G. Pananakakis........................................................................... 59
Impact of hot carrier degradation modes on I/O nMOSFETS aging prediction
C. Guerin, V. Huard, A. Bravaix, M. Denais ........................................................................................................................... 63
Reliability issues related to fast charge loss mechanism in embedded non volatile memories
P. Mora, S. Renard, G. Bossu, P. Waltz, G. Pananakakis, G. Ghibaudo ............................................................................. 68
Flash oxide scalability model and impact of program/erase method
A. Haggag, P. Kuhn, P. Ingersoll, C. Li, T. Harp, A. Hoefler, D. Burnett, K. Baker, K. Chang ................................................... 73
Experimental study of temperature dependence of program/erase endurance of embedded Flash
memories with 2T-FNFN device architecture
G. Tao, H. Chauveau, S. Nath ................................................................................................................................................... 76
A critical failure source in 65nm-MLC NOR flash memory incorporating Co-salicidation process
J. Han, B. Lee, J. Han, W. Kwon, C. Chang, S. Sim, C. Park, and K. Kim........................................................................... 80
2006
iii

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2006
2006
Study of electrically programmable fuses through series of I-V measurements
H. Suto, S. Mori, M. Kanno, N. Nagashima ............................................................................................................................. 83
NiSi polysilicon fuse reliability in 65nm logic CMOS technology
B. Ang, S. Tumakha, J. Im, S. Paak........................................................................................................................................... 89
Non-Arrhenius temperature acceleration and stress-dependent voltage acceleration for
semiconductor device involving multiple failure mechanisms
J. Qin, J. Bernstein ..................................................................................................................................................................... 93
Fast productive WLR characterization methods of plasma induced damage of thin and thick MOS gate oxides
A. Martin, C. Siol, C. Schlünder................................................................................................................................................ 98
Practical considerations for wafer-level electromigration monitoring in high volume production
O. Aubel, T.D. Sullivan, D. Massey, T.C. Lee, T. Merrill, S. Polchlopek, A. Strong ......................................................... 105
Spatial probing of traps in nMOSFETs with ALD HfO 2 /SiO 2 stacks using low frequency noise characteristics
H. Xiong, J. Suehle ................................................................................................................................................................... 111
New insight on the origin of Stress Induced Leakage Current for SiO 2 /HfO 2 dielectric stacks
M. Rafik, G. Ribes, D. Roy, S. Kalpat, G. Ghibaudo............................................................................................................. 116
Fast and slow charge trapping/detrapping processes in high-k nMOSFETs
D. Heh, R. Choi, C. D. Young, and G. Bersuker .................................................................................................................. 120
Influence of stress-induced-leakage-current on reliability of HfSiO x with EOT>1.5nm and TiN gate
S. Jakschik, T. Kauerauf, R. Degreave, Y.N. Hwang, R. Duschl, M. Kerber, A. Avelan, S. Kudelka .............................. 125
Leakage current variation with time in Ta 2 O 5 MIM and MIS capacitors
J-P. Manceau, S. Bruyere, S. Jeannot, A. Sylvestre, P. Gonon............................................................................................ 129
POSTER PRESENTATIONS—REFEREED
Residual resistivity model and its application
L. Doyen, X. Fererspiel, D. Ney, G. Sers, V. Girault, L. Arnaud, Y. Wouters....................................................................... 134
Ultra-fast NBTI monitoring and end-of-life projection
C. Wang, W. Chang, W. Ke, K. Su ............................................................................................................................................. 136
Impact of monitoring voltage on the lifetime extrapolation during the accelerated degradation tests
F. Duan, S. Cooper, A. Marathe, J. Zhang, S. K. Jayanarayanan ...................................................................................... 139
Oxide reliability: a new methodology for reliability evaluation at parametric testing
R. Bottini, A. Sebastiani, N. Galbiati, C. Scozzri, G. Ghidini ................................................................................................... 142
Preliminary study of the breakdown strength of TiN/HfO 2 /SiO 2 /Si MOS gate stacks
R. Southwick, M.C. Elgin, G. Bersuker, R. Choi, W.B. Knowlton ...................................................................................... 146
Cryogenic performance & reliability of GaAs CHFETs
R. Leon & Y. Chen .................................................................................................................................................................... 148
Lithography CD variation effects on LFNDMOS transistor hot carrier degradation
M.Thomason, C.A. Billman, B. Greenwood, B. Williams, C. Belisle, F. Bauwens .............................................................. 152
Product reliability trends, derating considerations and failure mechanisms with scaled CMOS
M White, D. Vu, D. Nguyen, R. Ruiz, Y. Chen, J.B. Bernstein ............................................................................................. 156
Modeling and characterization of bias stress-induced instability of SiC MOSFETs
A.J. Lelis, S. Potbhare, D. Habersat, G. Pennington, N. Goldsman ................................................................................... 160
Temperature effects on the hot-carrier induced degradation of pMOSFETs
S-Y. Chen, C-H. Tu, J-C. Lin, P-W. Kao, W-C. Lin, Z-W. Jhou, S. Chou, J. Ko, H-S. Haung ......................................... 163
ESD robustness of 40-V CMOS devices with/without drift implant
W-J. Chang, M-D. Ker, T-H. Lai, R. Choi,T-H. Tang, K-C. Su ........................................................................................... 167
Burn-in acceleration considerations in 90nm system LSI
N. Wakai, Y. Kobira, T. Oishi, S. Yamasaki, H. Egawa ........................................................................................................ 171
Reliability of strain-Si FPGA product fabricated by novel ultimate spacer process
2006
Y.H. Luo, D. Nayak, J. Lee, D. Gitlin, C.T.Tsai .................................................................................................................... 175

2006
2006
The correlation of interface defect density and power-law exponent factor on ultra-thin gate dielectric reliability
J.Y.C. Yang, C-L. Lin, C-Y. Hu, J-P. Chen, C-J. Kao, K.C. Su............................................................................................ 179
Fast prediction of gate oxide reliability – Application of the cumulative damage principle for transforming
V-ramp breakdown distributions into TDDB failure distributions
A. Aal .......................................................................................................................................................................................... 182
Ultra-thin gate oxide lifetime projection and degradation mechanism beyond 90 nm CMOS technology
C.-L. Lin, T. Kao, J-P. Chen, J.Y.C. Yang, K.C. Su .............................................................................................................. 186
Impact of error correction code and dynamic memory reconfiguration on high reliability/low cost server memory
C. Slayman, M. Ma, S. Lindley ................................................................................................................................................ 190
Blowing polysilicon fuses: What conditions are best?
Y. Li and A. Tang ...................................................................................................................................................................... 194
A new mechanism of poly-silicon crater defect induced from Al tiny particle charging effect during water rinse
in oxide patterning process
L.J. Duan, H.H. Au, M. Kuan, P.S. Quek, K.S. Pey .............................................................................................................. 198
Wafer reliability evaluation and monitoring for InGaAsP devices
D.E. Verbitsky ........................................................................................................................................................................... 201
Surface roughness enhanced current in defectively stressing poly-oxide-poly capacitors
L. Sheng, E. DeBacker, D. Wojciechowski, J. DeGreve, K. Dhondt, S. Boonen, D. Malschaert, E. Snyder................... 205
Retention reliability improvement of SONOS non-volatile memory with N 2 O oxidation tunnel oxide
J.-L. Wu, C-H. Kao, H-C. Chien, T-K. Tsai, C-Y. Lee, C-W. Liao, C-Y. Chou, M-I. Yang ............................................... 209
Surface morphology change of titanium nitride film after metal layer photolithography rework
causing oxide film de-lamination
H.T. Chiew, J. Tan, S. Lim, K.S. Lee, L.Y. Ren, B.C. Lee, P.S. Quek, K.S. Pey ................................................................. 213
TUTORIAL ABSTRACTS
Reliability of on-the-shelf stored image sensors
A.J.P. Theuwissen ..................................................................................................................................................................... 215
New Challenges and requirements to reliability research and development in semiconductor technology evolution
Y. Ma .......................................................................................................................................................................................... 215
Phase change memory reliability
S.J. Ahn ...................................................................................................................................................................................... 216
Stategy of future reliability qualification
A. Preussger .............................................................................................................................................................................. 216
SiON gate dielectric reliability
P.E. Nicollian ............................................................................................................................................................................ 217
The Negative bias temperature instability in MOS devices
S. Zafar ...................................................................................................................................................................................... 217
Current challenges in Cu electromigration reliability
C. Hau-Riege ............................................................................................................................................................................. 217
Reliability aspects of integrating high-k dielectrics into back-end-of-line (BEOL) process technology
T. Remmel, J. Walls, D. Roberts.............................................................................................................................................. 218
DISCUSSION GROUP (DG) REPORTS
DG: High-k dielectric stacks...................................................................................................................................................... 219
DG: NBTI ................................................................................................................................................................................... 220
DG: Interconnects ...................................................................................................................................................................... 221
DG: Product reliability ............................................................................................................................................................... 222
BIOGRAPHIES................................................................................................................................................................................. 223
2006
PICTURES ...................................................................................................................................................................................... 226
v

2005
contents
Foreword ........................................................................................................................................................................................ vi
PLATFORM TECHNICAL PRESENTATIONS*
Observations of NBTI-induced atomic scale defects
J.P. Campbell, P.M. Lenahan, A.T. Krishnan, and S. Krishnan .............................................................................................. 1
Single-hole detrapping events in pMOSFETs NBTI degradation
V. Huard, C.R. Parthasarathy, and M. Denais ......................................................................................................................... 5
Combined effect of NBTI and channel hot carrier effects in pMOSFETs
C. Guerin, V. Huard, A. Bravaix, M. Denais, J.M. Roux, F. Perrier, and W. Baks .................................................................10
NBTI in SOI p-channel MOS field effect transistors
S.T. Liu, D.E. Ioannou, D.P. Ioannou, M. Flanery, and H.L. Hughes .....................................................................................17
Via depletion electromigration in copper interconnects
C. Christiansen, B. Li, J. Gill, R. Filippi, and M. Angyal ........................................................................................................22
Blech effect in dual damascene copper-low k interconnects
D. Ney, X. Federspiel, V. Girault, O. Thomas, and P. Gergaud ..............................................................................................27
An integrated solution with a novel bi-layer etch stop to eliminate 90 nm Cu/low k package fail
P. Sun, E. Bei, Y.W. Chen, T. Hu, F. Ji, C.C. Liao, V. Ruan, A. Tsai, D.L. Wang, S. Wu, G. Zhang,
A. Fan, and I.C. Chen ..................................................................................................................................................................31
Impact of moisture on porous low-k reliability
J. Michelon and R.J.O.M. Hoofman ...........................................................................................................................................35
Effect of moisture on the Time Dependent Dielectric Breakdown (TDDB) behavior in an
ultra-low-k (ULK) dielectric
J.R. Lloyd, T.M. Shaw, and E.G. Liniger....................................................................................................................................39
Voltage acceleration of oxide breakdown in the sub-10nm Fowler-Nordheim and direct tunneling regime
R. Duschl and R.P. Vollertsen ....................................................................................................................................................44
Design for ASIC reliability for low temperature applications
Y. Chen, M. Mojaradi, L. Westergard, C. Billman, S. Cozy, G. Burke, and E. Kolawa .........................................................49
Lifetime prediction of ultra-thin gate oxide PMOSFETs submitted to hot hole injections
T. Di Gilio and A. Bravaix ..........................................................................................................................................................54
A new degradation mode for advanced heterojunction bipolar transistors under reverse bias stress
M. Ruat, R. Angers, G. Ghibaudo, N. Revil, and G. Pananakakis .........................................................................................59
Degradation of rise time in NAND gates using 2.0 nm gate dielectrics
M.L. Ogas, P.M. Price, J.C. Kiepert, R.J. Baker, G. Bersuker, and W.B. Knowlton ..............................................................63
Charge retention of silicided and unsilicided floating gates in embedded logic nonvolatile memory
B. Wang, H. Nguyen, A. Horch, Y. Ma, and R. Paulsen ............................................................................................................67
On intrinsic failure rate of products with error correction
G. Tao, J. Bisschop, and S. Nath ................................................................................................................................................71
Physical origin of V t instabilities in high-k dielectrics and process optimisation
G. Ribes, S. Bruyère, D. Roy, C. Parthasarthy, M. Müller, M. Denais, V. Huard,
T. Skotnicki, and G. Ghibaudo...................................................................................................................................................75
* Paper 6.1: Asymmetries in the electrical activity of intrinsic grain-boundary and O-atom vacancy defects in HfO /ZrO , and at their interfaces with
2 2
SiO : a disabling flaw for CMOS gate dielectric applications—G. Lucovsky, C. Fluton, C. Hinkle, S. Lee, North Carolina State Univ., J. Lüning,
2
Stanford Synchrotron Research Center has be folded into the tutorial "Intrinsic limitations on the performance and reliability of high-k
2005
gate dielectrics for advanced silicon devices" by G. Lucovsky on page 145-157.
2005
iii

iv
2005
Detection of trap generation in high-k gate stacks
C.D. Young, D. Heh, S. Nadkarni, R. Choi, J.J. Peterson, H.R. Harris, J.H. Sim, S.A. Krishnan,
J. Barnett, E. Vogel, B.H. Lee, P. Zeitzoff, G.A. Brown, and G. Bersuker ...............................................................................79
Charge instability in high-k gate stacks with metal and polysilicon electrodes
A. Neugroschel and G. Bersuker ................................................................................................................................................84
Charge trapping dependence on the physical structure of ultra-thin ALD-HfSiON/TiN gate stacks
S.A. Krishnan, M.A. Quevedo-Lopez, R. Choi, P.D. Kirsch, C. Young, R. Harris, J.J. Peterson,
H. Li, B.H. Lee, and J.C. Lee .......................................................................................................................................................89
POSTER PRESENTATIONS—REFEREED
Testing methodology for lifetime extrapolation of PZT capacitors
E. Bouyssou, S. Bruyere, G. Guégan, C. Anceau and R. Jérisian...........................................................................................91
Efficient fWLR inline monitoring of hot carrier reliability by means of one simple, comprehensive parameter
R. Vollertsen and H. Nielen ........................................................................................................................................................95
Impact of NBTI-driven parameter degradation on lifetime of a 90nm p-MOSFET
R. Wittmann , H. Puchner, L. Hinh, H. Ceric, A. Gehring, and S. Selberherr ........................................................................99
Impact of device scaling on deep sub-micron transistor reliability - A study of reliability trends using SRAM
M. White , B. Huang, J. Qin, Z. Gur, M. Talmor , , Y. Chen, J. Heidecker,
D. Nguyen, and J. Bernstein .................................................................................................................................................... 103
Matching variation after HCI stress in advanced CMOS technology for analog applications
J.C. Lin, S.Y. Chen, H.W. Chen, H.C. Lin, Z.W. Jhou, S. Chou, J. Ko, T.F. Lei, and H.S. Haung...................................... 107
One time programming device yield study based on anti-fuse gate oxide breakdown on P-type
and N-type substrates
N. Mathur, Y. Ahn, I. Kouznetov, F. Jenne, and J. Fulford ................................................................................................... 111
IREM usage in the detection of highly resistive failures on 65 nm products
I. Wan, D. Bockelman, Y. Xuan, and S. Chen ......................................................................................................................... 114
Predictive simulation to improve reliability of a snapback-based NMOS clamp
P. Gaitonde, S. J. Gaul, T.L. Crandell, and S.K. Earles ...................................................................................................... 117
An investigation on substrate current & hot carrier degradation at elevated temperatures
for nMOSFETs of 0.13 µm technology
S.Y. Chen, J.C. Lin, H.W. Chen, Z.W. Jhou, H.C. Lin, S. Chou, J. Ko, T.F. Lei and H.S. Haung....................................... 120
Characterization of EOS induced on submicron devices using 2D spectral imaging
M.F. Bailon, P.F. Salinas, J.S. Arboleda, and J.C. Miranda................................................................................................... 123
First steps toward aging simulation of complex analog circuits with behavioural modeling
F. Marc and Y. Danto ............................................................................................................................................................... 126
Some applications of V and Q tests
BD BD
J.T.C. Chen, T. Dimitrova, D. Dimitrov, K. Park, and D.K. Schroder ................................................................................. 130
Accurate method for determination of interconnect cross section
X. Federspiel, D. Ney, and V. Girault ..................................................................................................................................... 133
Resistance instability in Cu-damascene structures during the isothermal electromigration test
M. Impronta, S. Farris, A. Ficola, and A. Scorzoni ............................................................................................................... 135
POSTER P RESENTATIONS—OPEN
Resistivity of Nanometer-Scale Films and Interconnects: Model and Simulation
A.E. Yarimbiyik, H.A. Schafft, R.A. Allen, M.E. Zaghloul, and D.L. Blackburn ....................................................................... 139
TUTORIAL ABSTRACTS
From Micro Breakdown to Hard Breakdown - from Artifact to Destructive Failure?
R. Degraeve ............................................................................................................................................................................... 141
MEMS Reliability
D. Tanner ................................................................................................................................................................................... 2005
141

2005
2005
Designing radiation hardened CMOS microelectronic components at commercial foundries: Space
and terrestrial radiation environments and device and circuit techniques to mitigate radiation effects
R. Lacoe ..................................................................................................................................................................................... 142
Reliability engineering tools: Bootstrapping and extreme value statistics
L. Stout ....................................................................................................................................................................................... 143
Flash memory reliability
A. Modelli and A. Visconti ......................................................................................................................................................... 144
Back end reliability
G. Alers....................................................................................................................................................................................... 144
TUTORIAL SUMMARIES
Intrinsic limitations on the performance and reliability of high-k gate dielectrics for advanced silicon devices
G. Lucovsky ................................................................................................................................................................ 145
Characterization and modeling NBTI for design-in reliability
C.R. Parthasarathy, M. Denais , V. Huard, G. Ribes, E. Vincent, and A. Bravaix ............................................................ 158
Product reliability in 90nm CMOS and beyond
A.A. Turner ................................................................................................................................................................................. 163
DISCUSSION G ROUP (DG) AND S PECIAL INTEREST GROUP (SIG) SUMMARY REPORTS
SIG: Copper stress migration ....................................................................................................................................................... 168
DG: Gate oxide/high-k reliability .................................................................................................................................................. 169
DG: NBTI ..................................................................................................................................................................................... 170
DG: Interconnect reliability .......................................................................................................................................................... 171
DG: Product/circuit reliability....................................................................................................................................................... 172
BIOGRAPHIES ................................................................................................................................................................................. 173
PICTURES ....................................................................................................................................................................................... 177
2005
v

2005
contents
Foreword ........................................................................................................................................................................................ vi
PLATFORM TECHNICAL PRESENTATIONS*
Observations of NBTI-induced atomic scale defects
J.P. Campbell, P.M. Lenahan, A.T. Krishnan, and S. Krishnan .............................................................................................. 1
Single-hole detrapping events in pMOSFETs NBTI degradation
V. Huard, C.R. Parthasarathy, and M. Denais ......................................................................................................................... 5
Combined effect of NBTI and channel hot carrier effects in pMOSFETs
C. Guerin, V. Huard, A. Bravaix, M. Denais, J.M. Roux, F. Perrier, and W. Baks .................................................................10
NBTI in SOI p-channel MOS field effect transistors
S.T. Liu, D.E. Ioannou, D.P. Ioannou, M. Flanery, and H.L. Hughes .....................................................................................17
Via depletion electromigration in copper interconnects
C. Christiansen, B. Li, J. Gill, R. Filippi, and M. Angyal ........................................................................................................22
Blech effect in dual damascene copper-low k interconnects
D. Ney, X. Federspiel, V. Girault, O. Thomas, and P. Gergaud ..............................................................................................27
An integrated solution with a novel bi-layer etch stop to eliminate 90 nm Cu/low k package fail
P. Sun, E. Bei, Y.W. Chen, T. Hu, F. Ji, C.C. Liao, V. Ruan, A. Tsai, D.L. Wang, S. Wu, G. Zhang,
A. Fan, and I.C. Chen ..................................................................................................................................................................31
Impact of moisture on porous low-k reliability
J. Michelon and R.J.O.M. Hoofman ...........................................................................................................................................35
Effect of moisture on the Time Dependent Dielectric Breakdown (TDDB) behavior in an
ultra-low-k (ULK) dielectric
J.R. Lloyd, T.M. Shaw, and E.G. Liniger....................................................................................................................................39
Voltage acceleration of oxide breakdown in the sub-10nm Fowler-Nordheim and direct tunneling regime
R. Duschl and R.P. Vollertsen ....................................................................................................................................................44
Design for ASIC reliability for low temperature applications
Y. Chen, M. Mojaradi, L. Westergard, C. Billman, S. Cozy, G. Burke, and E. Kolawa .........................................................49
Lifetime prediction of ultra-thin gate oxide PMOSFETs submitted to hot hole injections
T. Di Gilio and A. Bravaix ..........................................................................................................................................................54
A new degradation mode for advanced heterojunction bipolar transistors under reverse bias stress
M. Ruat, R. Angers, G. Ghibaudo, N. Revil, and G. Pananakakis .........................................................................................59
Degradation of rise time in NAND gates using 2.0 nm gate dielectrics
M.L. Ogas, P.M. Price, J.C. Kiepert, R.J. Baker, G. Bersuker, and W.B. Knowlton ..............................................................63
Charge retention of silicided and unsilicided floating gates in embedded logic nonvolatile memory
B. Wang, H. Nguyen, A. Horch, Y. Ma, and R. Paulsen ............................................................................................................67
On intrinsic failure rate of products with error correction
G. Tao, J. Bisschop, and S. Nath ................................................................................................................................................71
Physical origin of V t instabilities in high-k dielectrics and process optimisation
G. Ribes, S. Bruyère, D. Roy, C. Parthasarthy, M. Müller, M. Denais, V. Huard,
T. Skotnicki, and G. Ghibaudo...................................................................................................................................................75
* Paper 6.1: Asymmetries in the electrical activity of intrinsic grain-boundary and O-atom vacancy defects in HfO /ZrO , and at their interfaces with
2 2
SiO : a disabling flaw for CMOS gate dielectric applications—G. Lucovsky, C. Fluton, C. Hinkle, S. Lee, North Carolina State Univ., J. Lüning,
2
Stanford Synchrotron Research Center has be folded into the tutorial "Intrinsic limitations on the performance and reliability of high-k
2005
gate dielectrics for advanced silicon devices" by G. Lucovsky on page 145-157.
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Detection of trap generation in high-k gate stacks
C.D. Young, D. Heh, S. Nadkarni, R. Choi, J.J. Peterson, H.R. Harris, J.H. Sim, S.A. Krishnan,
J. Barnett, E. Vogel, B.H. Lee, P. Zeitzoff, G.A. Brown, and G. Bersuker ...............................................................................79
Charge instability in high-k gate stacks with metal and polysilicon electrodes
A. Neugroschel and G. Bersuker ................................................................................................................................................84
Charge trapping dependence on the physical structure of ultra-thin ALD-HfSiON/TiN gate stacks
S.A. Krishnan, M.A. Quevedo-Lopez, R. Choi, P.D. Kirsch, C. Young, R. Harris, J.J. Peterson,
H. Li, B.H. Lee, and J.C. Lee .......................................................................................................................................................89
POSTER PRESENTATIONS—REFEREED
Testing methodology for lifetime extrapolation of PZT capacitors
E. Bouyssou, S. Bruyere, G. Guégan, C. Anceau and R. Jérisian...........................................................................................91
Efficient fWLR inline monitoring of hot carrier reliability by means of one simple, comprehensive parameter
R. Vollertsen and H. Nielen ........................................................................................................................................................95
Impact of NBTI-driven parameter degradation on lifetime of a 90nm p-MOSFET
R. Wittmann , H. Puchner, L. Hinh, H. Ceric, A. Gehring, and S. Selberherr ........................................................................99
Impact of device scaling on deep sub-micron transistor reliability - A study of reliability trends using SRAM
M. White , B. Huang, J. Qin, Z. Gur, M. Talmor , , Y. Chen, J. Heidecker,
D. Nguyen, and J. Bernstein .................................................................................................................................................... 103
Matching variation after HCI stress in advanced CMOS technology for analog applications
J.C. Lin, S.Y. Chen, H.W. Chen, H.C. Lin, Z.W. Jhou, S. Chou, J. Ko, T.F. Lei, and H.S. Haung...................................... 107
One time programming device yield study based on anti-fuse gate oxide breakdown on P-type
and N-type substrates
N. Mathur, Y. Ahn, I. Kouznetov, F. Jenne, and J. Fulford ................................................................................................... 111
IREM usage in the detection of highly resistive failures on 65 nm products
I. Wan, D. Bockelman, Y. Xuan, and S. Chen ......................................................................................................................... 114
Predictive simulation to improve reliability of a snapback-based NMOS clamp
P. Gaitonde, S. J. Gaul, T.L. Crandell, and S.K. Earles ...................................................................................................... 117
An investigation on substrate current & hot carrier degradation at elevated temperatures
for nMOSFETs of 0.13 µm technology
S.Y. Chen, J.C. Lin, H.W. Chen, Z.W. Jhou, H.C. Lin, S. Chou, J. Ko, T.F. Lei and H.S. Haung....................................... 120
Characterization of EOS induced on submicron devices using 2D spectral imaging
M.F. Bailon, P.F. Salinas, J.S. Arboleda, and J.C. Miranda................................................................................................... 123
First steps toward aging simulation of complex analog circuits with behavioural modeling
F. Marc and Y. Danto ............................................................................................................................................................... 126
Some applications of V and Q tests
BD BD
J.T.C. Chen, T. Dimitrova, D. Dimitrov, K. Park, and D.K. Schroder ................................................................................. 130
Accurate method for determination of interconnect cross section
X. Federspiel, D. Ney, and V. Girault ..................................................................................................................................... 133
Resistance instability in Cu-damascene structures during the isothermal electromigration test
M. Impronta, S. Farris, A. Ficola, and A. Scorzoni ............................................................................................................... 135
POSTER P RESENTATIONS—OPEN
Resistivity of Nanometer-Scale Films and Interconnects: Model and Simulation
A.E. Yarimbiyik, H.A. Schafft, R.A. Allen, M.E. Zaghloul, and D.L. Blackburn ....................................................................... 139
TUTORIAL ABSTRACTS
From Micro Breakdown to Hard Breakdown - from Artifact to Destructive Failure?
R. Degraeve ............................................................................................................................................................................... 141
MEMS Reliability
D. Tanner ................................................................................................................................................................................... 2005
141

2005
2005
Designing radiation hardened CMOS microelectronic components at commercial foundries: Space
and terrestrial radiation environments and device and circuit techniques to mitigate radiation effects
R. Lacoe ..................................................................................................................................................................................... 142
Reliability engineering tools: Bootstrapping and extreme value statistics
L. Stout ....................................................................................................................................................................................... 143
Flash memory reliability
A. Modelli and A. Visconti ......................................................................................................................................................... 144
Back end reliability
G. Alers....................................................................................................................................................................................... 144
TUTORIAL SUMMARIES
Intrinsic limitations on the performance and reliability of high-k gate dielectrics for advanced silicon devices
G. Lucovsky ................................................................................................................................................................ 145
Characterization and modeling NBTI for design-in reliability
C.R. Parthasarathy, M. Denais , V. Huard, G. Ribes, E. Vincent, and A. Bravaix ............................................................ 158
Product reliability in 90nm CMOS and beyond
A.A. Turner ................................................................................................................................................................................. 163
DISCUSSION G ROUP (DG) AND S PECIAL INTEREST GROUP (SIG) SUMMARY REPORTS
SIG: Copper stress migration ....................................................................................................................................................... 168
DG: Gate oxide/high-k reliability .................................................................................................................................................. 169
DG: NBTI ..................................................................................................................................................................................... 170
DG: Interconnect reliability .......................................................................................................................................................... 171
DG: Product/circuit reliability....................................................................................................................................................... 172
BIOGRAPHIES ................................................................................................................................................................................. 173
PICTURES ....................................................................................................................................................................................... 177
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contents
Foreword ........................................................................................................................................................................................ vi
PLATFORM TECHNICAL PRESENTATIONS
Modeling charge to breakdown using hydrogen multi-vibrational exitation (thin SiO 2 and high-K dielectrics)
G. Ribes, S. Bruyère, M. Denais, D. Roy, and G.Ghibaudo....................................................................................................... 1
Hydrogen release and defect generation rate in ultra-thin oxides
Vincent Huard, M. Denais, and F. Monsieur ............................................................................................................................. 4
Gate oxide reliability and deuterated CMOS processing
A.J. Hof, A.Y. Kovalgin, J. Schmitz, W.M. Baks, and R. van Schaijk........................................................................................ 7
A temperature accelerated model for high state retention loss of nitride storage flash memory
Ming-Yi Lee, N.K. Zous, T. Huang, W.J. Tsai, A. Kuo, Tahui Wang, Shaw Yin, and Chih-Yuan Lu ....................................11
Reliability response of plasma nitrided gate dielectrics to physical and electrical CET-scaling
R. Geilenkeuser, K. Wieczorek, T. Mantei, F. Grätsch, L. Herrmann, and J.-O. Weidner.....................................................15
New gate oxide wear-out model for accurate device lifetime projections on vertical drain NMOSFET
Sangwoo Pae, M. Agostinelli, G. Curello, S. Lau, S. Ramey and M. Alavi ............................................................................19
Impact of buried layer processing on gate oxide integrity
Barry O'Connell, Robert Yang, Wipawan Yindeepol, Joseph De Santis, Andy Strachan,
W. Coppock, Richard Foote, Charles Dark, Prochy Sethna, and Prasad Chaparala .........................................................23
Study of stress-induced leakage current and charge loss of nonvolatile memory cell with 70Å logic
tunnel oxide using floating-gate integrator technique
Bin Wang, Chih-Hsin Wang, Yanjun Ma, Chris Diorio, and Todd Humes .............................................................................28
Survey of oxide degradation in inverter circuits using 2.0 nm MOS devices
Mike L. Ogas, R.G. Southwick III, B.J. Cheek, R.J. Baker, G. Bersuker, and W.B. Knowlton .............................................32
Reversible leakage current switching in thin gate oxides–soft breakdown or noise?
Joachim Reiner ............................................................................................................................................................................37
Fast wafer level data acquisition for reliability characterization of sub-100 nm CMOS technologies
Andreas Kerber and Martin Kerber ..........................................................................................................................................41
Thermal and electromigration challenges for advanced interconnects
Baozhen Li, Dave Harmon, Jason Gill, Fen Chen, and Timothy Sullivan .............................................................................46
Analytical extraction of thermal conductivities of low k dielectrics for advanced technologies
David Ney, V. Girault, and X. Federspiel .................................................................................................................................52
Modeling interconnect behavior with a calibrated FEM model
Alvin Strong and Fen Chen ........................................................................................................................................................59
90nm node damascene copper stress voiding model and lifetime extrapolation methodology
Xavier Federspiel and S. Orain ..................................................................................................................................................64
Electromigration in narrow and large damascene copper lines
Valerie Girault, F. Terrier, and M. Gregoire ............................................................................................................................71
Effects of capillary forces on the global thinning of copper metallization under electromigration stress
Jun-Ho Choy, Yan Zhang, and Karen L. Kavanagh.................................................................................................................75
A model for electromigration-induced degradation mechanisms in dual-inlaid copper interconnct
Valeriy Sukharev and Ehrenfried Zschech ...............................................................................................................................79
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Electromigration-limited lifetime of aluminum bond pads
Martina Hommel, Sabine Penka, and Franz Ungar.................................................................................................................86
Electromigration of MRAM-customized Cu interconnects with cladding barriers and top cap
Donald A. Gajewski, Tom Meixner, Bill Feil, Mitch Lien, and James Walls. ........................................................................90
A comprehensive analysis of NFET degradation due to off-state stress
Karl Hofmann, S. Holzhauser, and C.Y. Kuo ............................................................................................................................94
New insights into threshold voltage shifts for ultrathin gate oxides
Dawei Heh, Eric M. Vogel, and Joseph B. Bernstein ...............................................................................................................99
Anomalous NMOSFET hot carrier degradation due to hole injection in a DGO CMOS process
Doug Brisbin, Yuri Mirgorodski, and Prasad Chaparala ................................................................................................... 102
Oxide field dependence of interface trap generation, during negative bias temperature instability in PMOS
Mickael Denais, V. Huard, C. Parthasarathy, G. Ribes, F. Perrier , N. Revil, and A. Bravaix ........................................ 109
Mechanism of dynamic NBTI pMOSFETs
Baozhong Zhu, J.S. Suehle, J.B. Bernstein, and Y. Chen ...................................................................................................... 113
Atomic scale defects involved in NBTI
J.P. Campbell, P.M. Lenahan, A.T. Krishnan, and S. Krishnan .......................................................................................... 118
New hole trapping characterization during NBTI in 65nm node technology with distinct nitridation processing
Mickael Denais, A. Bravaix, V. Huard, C. Parthasarathy, M. Bidaud, G. Ribes, D. Barge, L. Vishnubhotla,
B. Tavel, Y. Rey-Tauriac, F. Perrier, N. Revil, F. Arnaud, and P. Stolk.............................................................................. 121
Trapping and detrapping mechanism in hafnium based dielectrics characterized by pulse gate voltage techniques
Guillaume Ribes, S. Bruyere, D. Roy, M. Müller, M. Denais, V. Huard, T. Skotnicki, G. Ghibaudo .............................. 125
Effects of drain to gate stress on NMOSFET with polysilicon/Hf-silicate gate stack
Rino Choi, B.H. Lee, C.D. Young, J.H. Sim, K. Mathews, G. Bersuker, and P. Zeitzoff...................................................... 128
Recovery of NBTI degradation in HfSiON/metal gate transistors
Rusty Harris, Rino Choi, B.H. Lee, C.D. Young, J.H. Sim, K. Mathews, P. Zeitzoff, P. Majhi and G. Bersuker............... 132
Hot carrier stress study in Hf-silicate NMOS transistors
Johnny Sim, B.H. Lee, R. Choi , S.C. Song, C.D. Young,D.L. Kwong, P. Zeitzoff, and G. Bersuker .................................. 136
Mobility evaluation in high-K devices
Gennadi Bersuker, P. Zeitzoff, J. Sim, B.H. Lee, R. Choi, G. Brown, and C. Young ........................................................... 141
POSTER PRESENTATIONS—REFEREED
Dopant influence on polysilicon capacitor oxide failure
Janet M. Towner and John J. Naughton ................................................................................................................................ 145
Gate oxide integrity improvement by optimising poly deposition process
Tze Kiong Ng, Andrew Yap, Keng Foo Lo, and Poh Chuan Ang ......................................................................................... 148
Pseudo-progressive breakdown of ultra-thin nitrided gate oxide
Joachim Reiner ......................................................................................................................................................................... 151
An innovative multi-via test structure for wafer-level isothermal electromigration
Summer Tseng, Wei-Ting Kary Chien, and Willings Wang................................................................................................... 154
The study of sputtered RF Ta on the PID in Cu dual damascene technology
Wen Hui Lu, Kim Keng Teo, Chaw Sing Ho, Andrew Yap, and Keng Foo Lo..................................................................... 158
DF-RQA practice for SoC
Haim Marom .............................................................................................................................................................................. 162
Process dependence of hot carrier degradation in PMOSFETS
Erhong Li, Sharad Prasad, and Lesly Duong ........................................................................................................................ 166
Circuit and silicide impact on the correlation between TLP and ESD (HBM and MM)
S.C. Huang, J.H. Lee, S.C. Lee, K.M. Chen, M.H. Song, C. Y. Chiang, and M.C. Chang................................................... 169
DRAM standby current failure: The influence of hot carrier degradation on voltage level-up shifter circuit
2004
K. Lee, J.Y. Seo, J.W. Jung, G.J. Jung, J.H. Lee, S.J. Hwang, and C.K. Yoon..................................................................... 173

2004
2004
Reliability issues in advanced monolithic embedded high voltage CMOS technologies
Guoqiao Tao.............................................................................................................................................................................. 175
Improvement of spacer particle induced reliability failures
Summer Tseng, Kary Chien, Vivi Ruan, and Scott Liao ....................................................................................................... 178
Procedure for quantitative fWLR monitoring of gate dielectric reliability
Rolf-Peter Vollertsen ................................................................................................................................................................ 182
POSTER P RESENTATIONS—OPEN
Bayesian approach to reliability projection for high k dielectric thin films
Wen Luo, Way Kuo, and Yue Kuo ............................................................................................................................................ 186
DISCUSSION G ROUP SUMMARY REPORTS
Gate oxide reliability ..................................................................................................................................................................... 188
NBTI ............................................................................................................................................................................................ 190
Interconnect ................................................................................................................................................................................ 192
Product reliability......................................................................................................................................................................... 193
SPECIAL INTEREST G ROUP
Al and Cu test structure designs for stress voiding .............................................................................................................. 195
TUTORIAL ABSTRACTS
Characterization of alternative gate dielectrics using electrical I-V and C-V measurements
Khaled Ahmed ........................................................................................................................................................................... 196
High-k dielectrics: Materials physics, instabilities, defects, and reliability
John Conley .............................................................................................................................................................................. 196
Dielectric lifetime limited by pre- and post-breakdown degradation
Frederic Monsieur .................................................................................................................................................................... 197
a-Si:H Thin Film Transistors - reliability from materials to processes to devices
Yue Kuo ...................................................................................................................................................................................... 197
Electromigration reliability of Cu interconnects and impact of low k interconnects
Paul Ho and Martin Gall ......................................................................................................................................................... 197
Overview of physics of stress-induced voiding in microelectronics metallizations
Tim Sullivan .............................................................................................................................................................................. 198
Modeling NBTI: Kinetics to circuits
Anand Krishnan ........................................................................................................................................................................ 198
TUTORIAL SUMMARY
NBTI: What we know and what we need to know
Greg Massey .............................................................................................................................................................................. 199
MINI-WORKSHOP
Mentoring in the technical environment
Deborah Massey........................................................................................................................................................................ 212
BIOGRAPHIES ................................................................................................................................................................................. 215
PICTURES ....................................................................................................................................................................................... 218
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contents
Foreword ...................................................................................................................................................................................... vii
PLATFORM TECHNICAL PRESENTATIONS
Interface traps and oxide traps creation under NBTI and PBTI in advanced CMOS
technology with a 2nm gate-oxide
M. Denais, V. Huard, C. Parthasarathy, G. Ribes, F. Perrier, N. Revil, and A. Bravaix ..................................................... 1
Non-invasive nature of corona charging on thermal Si/SiO 2 structures
M. Dautrich, P.M. Lenahan, A.Y. Kang, and J.F. Conley, Jr. ................................................................................................. 7
Gate oxide reliability parameters in the range 1.6 to 10 nm
R.-P. Vollertsen and E.Y. Wu ..................................................................................................................................................... 10
PMOS NBTI-Induced circuit mismatch in advanced technologies
M. Agostinelli, S. Lau, S. Pae, P. Marzolf, H. Muthali, and S. Jacobs ................................................................................. 16
Stress testing and characterization of high-k dielectric thin films
W. Luo, D. Sunardi, Y. Kuo, and W. Kuo ................................................................................................................................. 18
Reliability Concerns for HfO 2 /Si (and ZrO 2 /Si) systems: Interface and dielectric traps
A.Y. Kang, P.M. Lenahan, J.F. Conley, Jr., and Y. Ono........................................................................................................ 24
Charge Trapping in MOCVD Hafnium-based Gate Dielectric Stack Structures and Its
Impact on Device Performance
C.D. Young, G. Bersuker, G.A. Brown, C. Lim, P. Lysaght, P. Zeitzoff, R.W. Murto, and
H.R. Huff...................................................................................................................................................................................... 28
Product specific sub-micron E-Fuse reliability and design qualification
W.R. Tonti, J.A. Fifield, J. Higgins, W.H. Guthrie, W. Berry, and C. Narayan ................................................................... 36
Projecting the reliability of SiGe NPN transistors after AC vbe reverse stress from DC device lifetime
K. Hofmann.................................................................................................................................................................................. 41
A current mirror method for thermal instability of SOI BJT
J. Kim, Y. Liu, and J.A De Santis .............................................................................................................................................. 45
DC and AC hot-carrier characteristics of partially depleted SOI MOSFETs with ultra-thin DPN
gate dielectrics
E. Zhao, J. Chan, J. Zhang, A. Marathe and K. Taylor .......................................................................................................... 49
Performance-reliability trade-offs in high speed Si-Ge BiCMOS
B. O’Connell, P. Chaparala, and B. Mehrotra ....................................................................................................................... 52
Breakdown walk-in a new PMOS failure mode in high power BiCMOS applications
D. Brisbin, A. Strachan, and P. Chaparala.............................................................................................................................. 56
Using time-dependent reliability fallout as a function of yield to optimize burn-in time
for a 130 nm SRAM device
K.R. Forbes and N. Arguello ..................................................................................................................................................... 61
Leakage current recovery in SRAM after AC stressing
C. Payan, S. Kumar, A. Thupil, S. Kasichainula, and W.B. Knowlton .................................................................................. 67
Effects of circuit-level stress on inverter performance and MOSFET characteristics
N. Stutzke, B.J. Cheek, S. Kumar, R.J. Baker, A.J. Moll, and W.B. Knowlton...................................................................... 71
Physically based simulation of the early and long-term failures in the copper
dual-damascene interconnect
V. Sukharev, R. Choudhury and C.W. Park.............................................................................................................................. 80
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Dielectric reliability studies of metal insulator metal capacitors (MIMCAP) with SiN dielectric under
unipolar to bipolar AC-stress
R. Schwab and K.H. Allers ......................................................................................................................................................... 86
A reliability evaluation methodology for memory chips for space applications when sample size is small
Y. Chen, D. Nguyen, S. Guertin, J. Bernstein, M. White, R. Menke, and S. Kayali ............................................................. 91
Improvement of write/erase cycling of memory cells with SiO 2 /HfO 2 tunnel dielectric
P. Blomme, B. Govoreanu, J. Van Houdt, and K. De Meyer .................................................................................................. 95
POSTER PRESENTATIONS—REFEREED*
Correlation of ramped current to constant voltage gate oxide reliability testing on leading edge
DRAM technology
G. Aichmayr and A. Beyer.......................................................................................................................................................... 99
Massively parallel GOI test
T.K. Ng, K.F. Lo, B.B. Jie and Y. Andrew .............................................................................................................................. 101
Effect of new inter-layer-dielectric on plasma charging damage in 0.13 µm dual gate oxide
W.H. Lu, L.H. Ko, K.L.Y. Andrew, and K.F. Lo ..................................................................................................................... 105
Similarity of Pre-Breakdown Leakage Current Fluctuations for p- and nMOSFETs
J.C. Reiner ................................................................................................................................................................................. 109
Latch-up failure path between power pins in the mixed-voltage process
C.-N. Wu, H.-M. Chou, and M. Chang.................................................................................................................................... 112
Determination of the maximum voltage for a product screening stress based on TDDB and HC measurements
H.-H. Kuge................................................................................................................................................................................. 115
HCI lifetime enhancement by PLDD implant energy optimization of Pch MOSFET in 0.13 µm CMOS technology
L. Hyeokjae, E. Quek, Y. Andrew and M. Karim ................................................................................................................... 119
A design technique to reduce hot carrier effect
E. Xiao ....................................................................................................................................................................................... 122
Effect of reverse measurement on the HC instability evaluation of MOSFETs
H. Katto, M. Miyauchi, and Y. Higuchi .................................................................................................................................. 124
Effect of nitrogen incorporation on PMOS negative bias temperature instability in ultrathin oxy-nitrides
L. Duong, E. Li, V. Gopinath, S. Prasad, J. Lin, D.Pachura, and V. Hornback ................................................................ 128
NBTI mechanism explored on the back gate bias for pMOSFETs
M.-G. Chen, J.-S. Li, C. Jiang, C.H. Liu, K.-C. Su, and Y.-J. Chang .................................................................................. 131
Impact of junction temperature on microelectronic device reliability and considerations for space applications
M. White, M. Cooper, Y. Chen, and J. Bernstein ................................................................................................................... 133
Reliability of dielectric barriers in copper damascene applications
A.S. Lee, A. Lakshmanan, N. Rajagopalan, Z. Cui, M. Le, L.Q. Xia, B.H. Kim, and H. M’Saad ..................................... 137
Effect of joule heating on the determination of electromigration parameters
X. Federspiel, V. Girault, and D. Ney..................................................................................................................................... 139
Reliability results on a 0.25 micron aluminum backend with a TiN sidewall
M. Nelson, L. Westergard, B. Williams, and J. Prasad ......................................................................................................... 143
POSTER PRESENTATIONS—DROP IN
Voltage Acceleration NBTI study fo a 90nm CMOS technology
S.J. Wen, L. Hinh, and H. Puchner ......................................................................................................................................... 147
* Refereed poster, Y.N. Shunin, K. Budilov, Y. Zhukovskii, O. Sychev, and G. Borstel, “Calculations of electronic and elastic properties of Cu-interconnects,” was
not presented at the workshop nor included in the printed Final Report but can be found on the 2003 IRW Final Report CDROM, IEEE Catalog No. 03TH8715C
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DISCUSSION GROUP SUMMARY REPORTS
Oxide Breakdown ...................................................................................................................................................................... 149
Electromigration ........................................................................................................................................................................ 151
High-K ....................................................................................................................................................................................... 153
NBTI .......................................................................................................................................................................................... 154
Reliability .................................................................................................................................................................................. 155
TUTORIAL SUMMARIES
Theory and application of non-contact methods for in-line reliability determination
J. D'Amico .................................................................................................................................................................................. 157
Magnetoresistive Random Access Memory (MRAM) and reliability
B. Hughes................................................................................................................................................................................... 169
TUTORIAL ABSTRACTS
Fast wafer level reliability monitoring of product wafers
A. Martin .................................................................................................................................................................................... 175
Reliability physics and chemistry of thin and high-k gate oxides
P. Lenahan ................................................................................................................................................................................. 175
BIOGRAPHIES ................................................................................................................................................................................. 176
PICTURES ...................................................................................................................................................................................... 179
2003

2002
2002
contents
Foreword ....................................................................................................................................................................................... vii
PLATFORM TECHNICAL PRESENTATIONS
Evidence for defect-generation-driven wear-out of breakdown conduction path in ultra thin oxides
F. Monsieur, E. Vincent, G. Ribes, V. Huard, S. Bruyere, D. Roy, G. Pananakakis, and G. Ghibaudo ............................... 1
Defect generation in ultra-thin oxide over large fluence ranges
D. Heh, E.M. Vogel, and J.B. Bernstein ..................................................................................................................................... 9
Comparison of low leakage and high speed deep submicron PMOSFET’s submitted to hole injections
A. Bravaix, D. Goguenheim, N. Revil, and E. Vincent ............................................................................................................14
Conducting atomic force microscopy studies for reliability evaluation of ultrathin SiO 2 films
G. Benstetter, W. Frammelsberger, T. Schweinboeck, R.J. Stamp, and J. Kiely ...................................................................21
Parametric reliability test: Wafer surface contamination study
G. Bersuker, J. Guan, G. Gale, P. Lysaght, D. Riley, and H.R. Huff ........................................................................................29
Relationship between interfacial adhesion and electromigration in Cu metallization
J.R. Lloyd, M.W. Lane, and E.G. Liniger...................................................................................................................................32
Intra-metal leakage reliability characteristics for line/via in copper/low-k interconnect structures
J.-W. Kim, N.-H. Lee, H.-W. Kim, H.-S. Kim, and C.-B. Rim ......................................................................................................36
Extrapolation of highly accelerated electromigration tests on copper to operation conditions
J. von Hagen, R. Bauer, S. Penka, A. Pietsch, W. Walter, and A. Zitzelsberger ....................................................................41
Temperature determination methods on copper material for highly accelerated electromigration tests (e.g. SWEAT)
J. von Hagen and H.A. Schafft ....................................................................................................................................................45
A practical methodology for multi-modality electromigration lifetime prediction
M.H. Lin, G.S. Yang, Y.L. Lin, MT. Lin, C.C. Lin, M.S. Yeh, K.P. Chang, K.C. Su, J.K. Chen, Y.J. Chang,
and T. Wang ..................................................................................................................................................................................50
Electromigration simulation of Cu–Low-k multilevel interconnect segments
V. Sukharev, R. Choudhury, and C.W. Park .............................................................................................................................55
Effect of reduced current density stress on the results of isothermal electromigration test for Cu damascene lines
A. Yap and B.H. Lim .....................................................................................................................................................................62
Gate oxide reliability correlation between test structures and DRAM product chips
R.-P. Vollertsen, K. Nierle, E.Y. Wu, and S. Wen.......................................................................................................................67
Time-dependent dielectric breakdown evaluation of deep trench capacitor with sidewall hemispherical, polysilicon
grains for Gigabit DRAM technology
F. Chen, P. Parkinson, I. McStay, K. Settlemyer, R. Reviere, H. Tews, M. Seitz, M. Kim, M. Ruprecht,
J. Li, R. Jammy, and A. Strong ...................................................................................................................................................71
Fast wafer level monitoring of stress induced leakage current in deep sub-micron embedded non-volatile
memory processes
G. Tao, A. Scarpa, H. Valk, L. van Marwijk, K. van Dijk, and F. Kuper ................................................................................76
Wafer-level reliability assessment of SiGe NPN HBTs after high temperature electrical operation
K. Hofmann, G. Brügmann, and A. Lill ......................................................................................................................................79
Fast and reliable WLR monitoring methodology for assessing thick dielectrics test structures integrated
in the kerf of product wafers
A. Martin, J. von Hagen, J. Fazekas, and K.H. Allers ..............................................................................................................83
Direct correlation of electrical reliability data to SEM analysis for deep trench dielectric weakness
M. Wühn, G. Diestel, and M. Obry ..............................................................................................................................................88
Polarity dependent reliability of advanced MOSFET using MOCVD nitrided Hf-silicate high-k gate dielectric
J. Zhang, E. Zhao, Q. Xiang, J. Chan, J. Jeon, J.-S. Goo, A. Marathe, B. Ogle, M.-R. Lin, and K. Taylor .........................92
2002
2002
iii

2002
iv
2002
Thermal and dielectric breakdown for metal insulator metal capacitors (MIMCAP)with tantalum pentoxide dielectric
K.H. Allers, R. Schwab, W. Walter, M. Schrenk, and H. Körner .............................................................................................96
Reliability concerns for HfO 2 /Si devices: Interface and dielectric traps
A.Y. Kang, P.M. Lenahan, and J.F. Conley, Jr. .................................................................................................................... 102
Electrical properties and reliability of HfO 2 deposited via ALD using Hf (NO 3 ) 4 precursor
J.F. Conley, Jr., Y. Ono, W. Zhuang, L. Stecker, and G. Stecker ............................................................................................ 108
Bias and temperature dependent hot-carrier characteristics of sub-100 nm partially depleted SOI MOSFET's
E.-X. Zhao, J. Chan, J. Zhang, A. Marathe, and K. Taylor ................................................................................................... 113
Hot carrier luminescence for backside 0.15 µm CMOS device analysis
W. Ng, G. Gao, A. Abraham, and T. Lundquist ...................................................................................................................... 116
1-D and 2-D hot carrier layout optimization of N-LDMOS transistor arrays
D.J. Brisbin, A. Strachan, and P. Chaparala ........................................................................................................................ 120
Negative bias temperature instability of deep sub-micron p-MOSFETs under pulsed bias stress
B. Zhu, J.S. Suehle, Y. Chen, and J.B. Bernstein .................................................................................................................. 125
The impact of NBTI and HCI on deep sub-micron PMOSFETs’ lifetime
C.-H. Jeon, S.-Y. Kim, H.-S. Kim, and C.-B. Rim..................................................................................................................... 130
Model for NBTI in p-MOSFETs with ultra thin nitrided gate oxides
M. Houssa, C.R. Parthasarathy, V. Huard, N. Revil, E. Vincent, and J. Autran ................................................................. 133
Interface traps and oxide charges during NBTI stress in p-MOSFETs
V. Huard, F. Monsieur, C.R. Parthasarathy, and S. Bruyere ............................................................................................... 135
POSTER PRESENTATIONS
How to check the design for the possible reliability problems?
M. Zaslavsky .............................................................................................................................................................................. 139
Self-consistent integrated system for susceptibility to terrestrial neutron induced soft-error of
sub-quarter micron memory devices
Y. Yahagi, E. Ibe, Y. Saito, A. Eto, M. Sato, H. Kameyama, M. Hidaka, K. Terunuma, T. Nunomiya, and T. Nakamura ........ 143
New applications of the infrared emission microscopy to wafer-level backside and flip-chip package analyses
S. Hsiung, K. Tan, and J. Luo .................................................................................................................................................. 147
Combined AFM methods to improve reliability investigations of thin oxides
W. Frammelsberger, G. Benstetter, R.J. Stamp, and J. Kiely ................................................................................................. 151
One-dimensional estimation of interconnect temperatures
A. Labun and J. Jensen ............................................................................................................................................................ 155
Light enhanced tungsten via corrosion
L. Westergard, C. Belisle, D. Florence, and T. Haskett.......................................................................................................... 159
Electromigration test on via line structure with a self-heated method
H.K. Yap, A.Yap, Y.C. Tan, and K.F. Lo .................................................................................................................................. 162
Real case study of SWEAT EM test on via/line structure as process reliability monitor methodology
A. Yap, B. H. Lim, H.K. Yap, Y.C. Tan, and K.F. Lo ............................................................................................................. 165
Sub-quarter micron SRAM cells stability in low-voltage operation: a comparative analysis
O. Semenov, A. Pavlov, and M. Sachdev ................................................................................................................................. 168
Infrared optical beam induced resistance change (IROBIRCH) technology for IC failure localization and analysis
K. Weaver, H. Acedo, and G. Gao ............................................................................................................................................. 172
Using life-cycle information for reliability assessment of electronic assemblies
A. Middendorf , H. Griese, H. Reichl, and W.M. Grimm ........................................................................................................ 176
Alternate method of TDDB study for aluminum oxide using magneto-resistance
S. Kumar and W. B. Knowlton .................................................................................................................................................. 180
Linear logistic regression: an introduction
T. Haifley.................................................................................................................................................................................... 184
2002
2002
2002

2002
2002
Comparison of calculated AC to DC Hot Carrier lifetimes based on combined single MOST DC stress results
and inverter simulations with AC stress measurements on single MOST’s to check the duty factor approach
H.-H. Kuge ................................................................................................................................................................................... 188
Comparison of Isothermal Wafer-Level EM and Package-Level EM for via test structure in Dual Damascene
low k/Copper Process
M. N. Chang, K. P. Chang, and K C Sue ................................................................................................................................ 192
A systematic leakage current analysis of gate oxide soft breakdown
J.C. Reiner ................................................................................................................................................................................. 196
A new approach in flash memory testing to increase quality and reduce cycle time on improvements
G. Giglio, T. Masi, M. Mastrocola, and F. Morgana ............................................................................................................ 199
DI water tribocharging damage at CMP
B. Lloyd and F. Zeid ................................................................................................................................................................. 202
ELECTROMIGRATION DISCUSSION GROUP SUMMARY ...................................................................................................... 204
TUTORIAL ABSTRACTS ........................................................................................................................................................... 207
BIOGRAPHIES ............................................................................................................................................................................ 208
PICTURES .................................................................................................................................................................................... 211
2002
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v

2001
2001
contents
Foreword ........................................................................................................................................................................................ v
Keynote:Can Praseodymium Oxide be an Alternative High-k Gate Dielectric Material for Silicon Integrated Circuits?
Hans-Joachim Müssig and Hans-Jörg Osten ................................................................................................................................ 1
PLATFORM TECHNICAL PRESENTATIONS
Preliminary Investigation of Hafnium Oxide Deposited via Atomic Layer Chemical Vapor Deposition (ALCVD)
J.F. Conley, Jr., Y. Ono, D.J. Tweet, W. Zhuang, M. Khaiser, and R. Solanki .......................................................................... 11
Latent Reliability Degradation of Ultra Thin Oxides After Heavy Ion and Gamma-Ray Irradiation
B. Wang, J.S. Suehle, E.M. Vogel, J.F. Conley, Jr., A.H. Johnston, and J.B. Bernstein ......................................................... 16
Time to Breakdown and Voltage to Breakdown for Ultra Thin Oxides (Tox

iv
2001
2001
POSTER PRESENTATIONS
On the Nature of Ultra-thin Gate Oxide Degradation During Pulse Stressing of nMOSCAPs
W.B. Knowlton, S. Kumar, T. Caldwell, J.J. Gomez, and B. Cheek ........................................................................................... 87
Fast and Accurate Isothermal Measurements on Process-Split Wafers
J. Chan, A. Marathe, and V. Pham ............................................................................................................................................. 89
The Influence of Temperature Gradients in Isothermal Electromigration Tests
A.(K.Leong) Yap and T.E. Turner ............................................................................................................................................... 91
Implementation of FWLR for Process Reliability Monitoring
K.L.Yap, H.K. Yap, Y.C. Tan, K.F. Lo, M.F. Karim, and I. Manna ........................................................................................... 94
DISCUSSION GROUP SUMMARY REPORTS
Electromigration Discussion Group Summary ............................................................................................................................ 97
Device Reliability Discussion Group Summary .......................................................................................................................... 98
TUTORIAL ABSTRACTS .......................................................................................................................................................... 99
BIOGRAPHIES.......................................................................................................................................................................... 101
PICTURES ................................................................................................................................................................................. 104
2001

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1999
1999
contents
Foreword ........................................................................................................................................................................................ v
KEYNOTE ADDRESS
Influencing Factors for Consideration of Future Generation System Design
Benjamin DeLuca ......................................................................................................................................................................... vi
TECHNICAL PRESENTATIONS
A Methodology to Assess the Influence of Burn-In Relating to Long Term Reliability of Submicron CMOS Transistors
S. Holzhauser and A. Narr. .......................................................................................................................................................... 1
Signal Margin Test to Identify Process Sensitivities Relevant to DRAM Reliability and Functionality at
Low Temperatures
E. Nelson, Y. Li, D. Poindexter, M. Ruprecht, E. Lim, Y. Matsubara, H. Sawazaki, Q.Ye, M. Iwatake, and W. Tonti ........ 6
Reliability Aspects of Stress Induced Voiding in 0.25 �m Metallization
A.E. Zitzelsberger and M.U. Lehr ...............................................................................................................................................10
Reliability Test Results for W FIB Interconnect Structures
M. Zaragoza, J. Zhang, and M. Abramo ....................................................................................................................................14
Predicting Plasma Charging Damage to Ultrathin Gate Oxide by Using Nondestructive DCIV Technique
H. Guan, M.F. Li, Y.H. Zhang, B.J. Cho, B.B. Jie, J. Xie, J.L.F. Wang, A.C. Yen, G.T.T. Sheng, Z. Dong and W. LI ...........20
Temperature Gradient Effects in Electromigration Using an Extended Transition Probability Model and Temperature
Gradient Free Tests
K. Jonggook, V.C. Tyree, and C.R. Crowell..............................................................................................................................24
An Evaluation of Electrical Linewidth Determination Using Cross-Bridge and Multi-Bridge Test Structures
L.M. Head and H.A. Schafft ........................................................................................................................................................41
Impact of Test-Structure Design and Test Methods for Electromigration Testing
S. Menon, J. Fazekas, J. von Hagen, L.M. Head, C.H. Ellenwood, and H.A. Schafft ............................................................46
Predicting Thermal Behavior of Interconnects
J.P. Gill, D.L. Harmon, J. Furukawa, and T.D. Sullivan ........................................................................................................54
Hot-Carrier Damage In AC-Stressed Deep-Submicrometer CMOS Technologies
A. Bravaix, D. Goguenheim, N. Revil, and E. Vincent ..............................................................................................................61
Dependence of HCI Mechanism on Temperature for 0.18 �m Technology and Beyond
W. Wang, J. Tao, and P. Fang.....................................................................................................................................................66
Conduction Mechanisms in Cu/Low-K Interconnect
G. Bersuker, V. Blaschke, S. Choi, and D. Wick ......................................................................................................................69
A Successful Application of WLR Fast Test on Al Via Process Optimisation
X. Liu, K.F. Lo, Q. Guo, and J. Cai ..............................................................................................................................................74
Limiting Oxide Failure Mode versus Oxide Thickness. Some Insights for Deep-submicron Technologies
S. Bruyere, E. Vincent, and G. Ghibaudo .................................................................................................................................78
Breakdown Voltage Distribution and Extrinsic TDDB Failures of MOS Gate Oxides
H. Katto .........................................................................................................................................................................................85
Simulation of Hot-Carrier Degradation Using Self-Consistent Solution of Semiconductor Energy-Balance and
Oxide Carrier Transport Equations
S.K. Mukundam, M.P. Pagey, R.D. Schrimpf, and K.F. Galloway ..........................................................................................92
Product Reliability and Maximum Voltage Limits from Extrinsic Gate Oxide Voltage Ramp Data
R. S. Hijab .....................................................................................................................................................................................98
New Experimental Findings on Constant Voltage and Current Soft-Breakdown in Ultra-Thin Oxides
D. J. Brisbin and P. Chaparala ............................................................................................................................................... 102
The Sensitivity and Correlation Study on Jramp Test and High-Field, Constant-Voltage Stress Test for WLR
Y. Chen, F. Li, P.M. Mason, Y. Ma, and A.S. Oates ............................................................................................................... 108
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Analysis of Evolution To and Beyond Quasi-breakdown in Ultra-thin Oxide and Oxynitride
M. Okandan, S.J. Fonash, B. Maiti, H.H. Tseng, and P. Tobin ............................................................................................ 111
New Experimental Findings on SILC and Soft Breakdown of Ultra-Thin Gate Oxides
M.G. Chen , C.H. Liu, M.T. Lee, and K.Y. Fu ......................................................................................................................... 114
Detecting Breakdown in Ultra-thin Dielectrics Using a Fast Voltage Ramp
E.S. Snyder and J.S. Suehle ..................................................................................................................................................... 118
WLR Monitoring Stresses and Suitable Test Structures for Future Product Reliability Targets
A. Martin, M. Kerber, and G. Diestel ...................................................................................................................................... 124
DISCUSSION GROUP SUMMARY REPORTS
WLR: C.D. Graas and E.T. Achee ........................................................................................................................................... 129
Burn-In: R.-P. Vollertsen and R.S. Hijab ............................................................................................................................... 132
Thin Oxide Limits: E. Vincent and J.S. Suehle ...................................................................................................................... 134
Electromigration: T.D. Sullivan and H.A. Schafft .................................................................................................................. 136
Hot Carriers: A. Bravaix ........................................................................................................................................................... 138
POSTER PRESENTATIONS
Gate Oxide Improvement: Statistics and Methodology
P. Baumgartner, M. Hammer, R. Heinrich, R. Berger, and G. Poppel ................................................................................. 140
Temperature Dependence of Resistance in Black’s Equation and in Calibration for SWEAT and NIST Structures:
The Parameter TEO
C.R. Crowell, C. Shih, K. Jonggook, V.C. Tyree ................................................................................................................... 142
HCI Characterization of Trans-LC and HCI Gate Oxidation Process
Z. Ma, G. Chapman, and V. Ho ................................................................................................................................................ 144
On the Bimodal Lognormal Distribution of Electromigration Lifetimes
M. Lepper, A.H. Fischer, and A.E. Zitzelsberger ................................................................................................................... 146
A New Technique for the Precise Measurement of Gate Oxide Damage Caused by Process Induced Charging
T.E. Turner, A. Pronin, and J. Daniels.................................................................................................................................... 148
Modeling of Polycrystalline Silicon thermal Coefficient of Resistance
S. Kumar and L. Bouknight ..................................................................................................................................................... 150
Reliability Engineering - An Integrated Approach at DaimlerChrysler
J.H. Renner ................................................................................................................................................................................ 152
Impact of Si/N Ratios in a Pre-Metal Si x N y :H z Dielectric Film on NMOS Channel Hot Carrier Reliability
J. Mason, R. Mena, M. Brugler, and B. Rajagopalan ........................................................................................................... 154
Special Interest Groups (SIGs) Report (WLR) ........................................................................................................................ 156
TUTORIALS
Abstract of Tutorial 1A Basic Reliability: Electromigration
T. D. Sullivan............................................................................................................................................................................. 157
Abstract of Tutorial 2B: Hot Carriers: Simulation, Modeling and Lifetime Prediction for HCI
B.W. McGaughy ......................................................................................................................................................................... 157
Summary of Tutorial 1B: (Ultra) Thin Oxide Breakdown(s), an Overview
E. Vincent .................................................................................................................................................................................. 158
Summary of Tutorial 1C: Burn-in
R-P. Vollertsen .......................................................................................................................................................................... 167
Summary of Tutorial 2A: Hot-Carrier Degradation Evolution in Deep Submicrometer CMOS Technlogies
A. Bravaix .................................................................................................................................................................................. 174
BIOGRAPHIES ........................................................................................................................................................................... 184
1999

contents
1998
1998
Foreword ........................................................................................................................................... v
KEYNOTE ADDRESS
Semiconductor Equipment Industry: Migration from equipment to entire
process module solutions
Dennis Yost ......................................................................................................................................vi
TECHNICAL PRESENTATIONS
Thermal Conductance of IC Interconnects Embedded in Dielectric
J.P. Gill, T.D. Sullivan, and D.L. Harmon ..................................................................................... 1
Wafer Level Electromigration Applied to Advance Copper/Low k Dielectric
Process Sequence Integration
Donald Pierce, James Educato, Viren Rana, and Dennis Yost ................................................. 10
Wafer Level Monitoring and Process Optimization for Robust Via EM Reliability
T. Zhao, C. Shih, J. McCollum, F. Hawley, F. Issaq, B. Cronquist,
R. Lambertson, E. Hamdy, Z. Yang, C. Chern, M. Liao, G. Say, G. Koh,
L. Chan, R. Sundaresan................................................................................................................. 16
A Study of Stress Voiding Effect on AlSi Metal Bank Allowed Lifetime
for a IC Foundry Fabs
K.P. Lin, C.D. Chang, K.S. Huang, S.L. Hsu................................................................................ 19
A Study of Field Dependence of TDDB of Ultra-Thin Gate Oxide and Anomaly
in the I-V of MOS Devices with Active Guard Ring
Abdullah Yassine, Homi Nariman, Kola Olasupo, and Laura Govea ...................................... 23
Practical Triggering of Early Breakdown in Thin Oxides
J.C. Jackson, D.J. Dumin, and Cleston Messick ......................................................................... 27
Complete method for Ebd Correction by Series Resistance Characterization
David K. Monroe and Scot E. Swanson ...................................................................................... 33
A Constant Gate Current Technique for Obtaining Low-Frequency
C-V Characteristics of MOS Capacitors
Jack G. Qian, Roy A. Hensley, and Eric Littlefield .................................................................... 39
The Life Time Model using the Correlation between Dielectric Thickness,
and Voltage Stress for 64MB Accelerated Reliability Testing
Yumi Kwon, Namhyun Cha, Samjin Whang, Namsung Cho, Whajoon Lee .............................. 45
Electric Field and Temperature Acceleration of Quasi-Breakdown
Phenomena in Ultrathin Oxides
D. Roy, S. Bruyere, E. Vincent, and G. Ghibaudo....................................................................... 49
A Comprehensive Physical Model of Oxide Wearout and Breakdown
Involving Trap Generation, Charging and Discharging
D. Qian and D.J. Dumin ................................................................................................................ 55
A Preliminary Investigation of the Kinetics of Post-Oxidation Anneal
Induced E’-Precursor Formation
J.F. Conley, Jr., W.F. McArthur, and P.M. Lenahan .................................................................. 62
A New Mechanism for Gate Oxide Degradation
Chuan H. Liu, Thomas A. DeMassa, and Julian J. Sanchez ...................................................... 68
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ESD Technology Benchmarking for Evaluation of Electrostatic Discharge
Robustness of CMOS Technologies
S. Voldman, W. Anderson, R. Ashton, M. Chaine, C. Duvvury,
T. Maloney, and E. Worley............................................................................................................ 72
Non-Contact In-Line Monitoring of Plasma-Induced Latent Damage
Tim Turner and Steve Weinzierl ................................................................................................... 78
Monitoring Charging in High Current Ion Implanters Yields Optimum
Preventive Maintenance Schedules and Procedures
Henry Gonzalez, Steven Reno, Cleston Messick, Wes Lukaszek, and
Thomas Romanski .......................................................................................................................... 82
Characterizing Electron Shower with CHARM-2 wafers on Eaton NV-8200P
Medium Current Ion Implanter
Steve Reno, Henry Gonzalez, Cleston Messick , Wes Lukaszek,
David A. St. Angelo, Klaus Becker, and Bobby Rogers ............................................................. 86
DISCUSSION GROUP SUMMARY REPORTS
Interconnect Reliability—with a Focus on Copper: T. Sullivan and D. Pierce ....................... 90
Oxides—Ultra Thin Oxides: R.P. Vollertsen and D.J. Dumin .................................................... 92
Electrostatic Discharge—ESD: H. Gieser and E. Worley ........................................................... 94
C-V Measurements – and Its Implication on Oxide, Tranisitor, and
Non-Volatile Memory Cell Reliability: U. Schwalke and B. Gordon......................................... 97
POSTER PRESENTATIONS
Investigation of Initial Charge Trapping and Oxide Breakdown under
Fowler-Nordheim Injection
A. Martin......................................................................................................................................... 99
Equilibrium Controlled Static C-V Method and Its Application
U. Schwalke, C. Gruensfelder, and M. Kerber.......................................................................... 105
Investigation on the Reduction of the Dark Current for PIN Silicon Photodiodes
Using Statistical Methods
M. Aceves, P. Rosales, A. Cerdeira, M. Estrada, A. E. Cabal, J. Ramírez .............................. 107
Interconnect Reliability Test Chip NIST 36: for Development of
Measurement Tools and Standards
H.A. Schafft ................................................................................................................................... 109
Characterization of Quasi-Breakdown in Ultra-Thin Gate Oxides
in an Automated Test Environment
D. Brisbin ...................................................................................................................................... 112
TUTORIALS
Summary of Tutorial 1:
The Analysis of Oxide Reliability Data
W.R. Hunter ................................................................................................................................... 114
Abstract of Tutorial 2:
Reliability Issues and the Development of Advanced DRAM Products
W. Ellis .......................................................................................................................................... 135
BIOGRAPHIES .............................................................................................................................. 136
Special Interest Groups (SIGs) Report ........................................................................................... 138
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