FROM C4 PbSn FLIP CHIP TO LEAD-FREE µBUMP FLIP ... - VeMet

FROM C4 PbSn FLIP CHIP TO
LEAD-FREE µBUMP FLIP CHIP
ERIC BEYNE
“VIJF JAAR LOODVRIJ SOLDEREN”
22 SEPTEMBER 2011
TNO, EINDHOVEN
© IMEC 2011

OUTLINE
o Introduction: Flip chip Scaling
o µbump interconnect
o Improving Bond quality
o Die stacking strategies
o Wafer-level underfill
o Conclusion
© IMEC 2011 E.BEYNE 2

SCALING FLIP-CHIP INTERCONNECTS
IMC
100µm pad diameter
150-200µm bump pitch
40µm pad Ø
60µm pitch
20µm pad
40µm pitch
10µm pad
20µm pitch
- With solder joint scaling, the intermetallics formed by
UBM solder interaction are of increasing importance
- For the smallest flip chip pitches : only intermetallic
compounds after solder bump reflow
© IMEC 2011
ERIC BEYNE 3

MICRO-BUMP JOINING
Si
Si
Si
M
Si
M
Solder
M
Si
M
Solder
M
Si
M
IMC
M
M
Solder - IMC
Similar to flip chip interconnect:
▸ Low temperature melting solder metal, UBM metals.
However:
▸ Entire solder volume is transformed into intermetallic compounds
▸ Small dimension : no solder „ball‟, typically < 10m thick
▸ Connection by thermo/compression-reflow method
▸ Requires improved control and flatness of the solder “bumps”
© IMEC 2011
ERIC BEYNE 4

APPLICATION SPACE µBUMP JOINING
‣ Si-Si face-to-face bonding
‣ 2.5D integration:
Si chips to Si interposers
DRAM
Logic
‣ 3D integration : chip stacking with TSV
© IMEC 2011
ERIC BEYNE 5

OUTLINE
o Introduction: Flip chip Scaling
o Baseline µbump interconnect
o Improving Bond quality
o Die stacking strategies
o Wafer-level underfill
o Conclusion
© IMEC 2011 E.BEYNE 6

BASELINE µBUMPING SCHEME: Cu/SnTO Cu
Baseline µbump scheme
▸ Die 1: Cu/Sn (5/3.5 µm)
▸ Die 2: Cu (5 µm)
µBump Ø: 25 down to 7.5 µm
µBump pitch: 40 down to 20 µm
Cu/Sn bump
5µm Cu
3.5µm Sn
5µm Cu
Top Si die
Bottom Si die
‣ Smooth side wall for
Cu and Sn
‣ No residues after
seed layer etch
© IMEC 2011
ERIC BEYNE
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DEMONSTRATION OF COLLECTIVE
TRANSIENT-LIQUID PHASE µBUMP BONDING
Bonding procedure:
• Pick & place die on wafer by Flip Chip bonding Tool, at
room temperature
• Collective Bonding in Wafer Bonder @ 250ºC
© IMEC 2011 ERIC BEYNE 8

SOLID METAL BONDING:
CuSn INTERMETALLIC BONDING @ 150ºC
Ф 25m bump, 40/15m
pitch/spacing
Top die
(Cu/Sn bump)
Bottom wafer
(Cu bump)
150°C/50MPa
150C/150MPa
150C/50MPa
Ф 25m bump, 40/15m
pitch/spacing
with no-flow underfill
© IMEC 2011 ERIC BEYNE 9

40 µm PITCH, Cu/Sn µBUMP DIE STACKING
PTCM/N TEST CHIPS
© IMEC 2011
5x5mm PTCM,
40 µm pitch
µbumps,
2 peripheral rows
ERIC BEYNE
8x8mm PTCN
“landing”die
Cu/Sn microbump samples:
‣ 3.5 µm and 8µm thick Sn on 40µm pitch Cu bumps,
100 µm thick Silicon
‣ Si-Si assembly in BGA package and SMD on test board
‣ Use of a no-flow underfill
Package level reliability of TLP bumps demonstrated
‣ >1800 temp cycles
‣ >1000 hrs in electromigration tests
‣ 96 hrs HAST
PTCN/M stack wire
bonded in BGA package
10

Resistance [Ohm]
Daisy chain Resistance (Ohm)
Resistance [Ohm]
Daisy chain Resistance (Ohm)
Resistance [Ohm]
Daisy chain Resistance (Ohm)
THERMAL CYCLING 40 µm PITCH Cu/Sn
µBUMP PTCM/N BGA ASSEMBLIES ON PCB
180
180
THERMAL CYCLING (-45°C/125°C) – IN-SITU
160
140
RESISTANCE MONITORING
120
In-situ measurement at 125°C
170
100
80
60
40
20
8.0µm Sn bump DC
3.5µm Sn bump DC
160
110
In-situ R at 125°C
0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Time (h) = # cycles Time -45°C/+125°C
[h] = Cycles [#]
In-situ resistance monitoring during
30’ 45ºC/30’125ºC thermal cycling
Cu/Sn microbump samples:
▸ 3.5 µm and 8µm thick Sn on 40µm pitch
Cu bumps, 100 µm thick Silicon
▸ Use of a no-flow underfill (NCP)
150
3000 3100 3200 3300
100
90
In-situ R @-45°C
No failures up to 4000 cycles
80
2950 3050 3150 3250 3350
© IMEC 2011
ERIC BEYNE 11

AGEING BEHAVIOUR OF LOW T Cu/SnTLP
µBUMP: VOID FORMATION
• Shift over time from Cu 6 Sn 5 to Cu 3 Sn, due to the excess of Cu.
• The difference in diffusion rates of Cu and Sn results in vacancies
that aglomerate to form voids : Kirkendall voids.
Initial state
Cu
Cu 3 Sn
After ageing at 250ºC for 15’
Cu
Cu 3 Sn
Cu 6 Sn 5
Cu 3 Sn
Cu
Cu 6 Sn 5
Cu 3 Sn
Cu
After ageing at 250ºC for
45’
Cu
Cu 3 Sn
Cu
© IMEC 2011
ERIC BEYNE 12

WHY FULL TRANSFORMATION TO IMC?
When using low volume “mini-bumps” with excess Sn, the risk of
electro-migration failure strongly increases
EM reliability test comparison: 40 µm pitch Cu/Sn µbump packaged
F2F chip assemblies on PCB
Cu/Sn microbump samples:
‣ 3.5 µm and 8µm thick Sn on 40µm pitch
Cu bumps, 100 µm thick Silicon
‣ Si-Si assembly in BGA package and SMD
on test board
‣ Use of a no-flow underfill
EM test structure with build-in
temperature monitor
© IMEC 2011
ERIC BEYNE
13

No data
WHY FULL TRANSFORMATION TO IMC?
When using low volume “mini-bumps” with excess Sn, the risk of
electro-migration failure strongly increases
EM reliability test comparison: Early failures when using excess Sn
(8 vs. 3.5 µm)
voiding at Cu-Cu 3 Sn interface
150 o C – 200 o C eff – 1.1mA/um 2
NUF particle entrapment
8.0µm Sn µbump
3.5µm Sn µbump
© IMEC 2011
ERIC BEYNE
14

OUTLINE
o Introduction: Flip chip Scaling
o Baseline µbump interconnect
o Improving Bond quality
o Die stacking strategies
o Wafer-level underfill
o Conclusion
© IMEC 2011 E.BEYNE 15

INTERMETALLIC µBUMP CONNECTIONS
Issues with pure Cu/Sn system:
▸ CuSn intermetallics already form at low
temperature: no elevated temperature
processes between bump formation
and assembly
Sn
Cu
IMC
voids
• Cu and Sn form 2 intermetallic compounds: Cu 3 Sn and Cu 6 Sn 5
• When soldering at high T: single Cu 3 Sn alloy can be obtained
• Unfortunately, low bonding T is required (particularly for memory,
even below 200ºC)
• At practical assembly conditions : Cu 3 Sn and Cu 6 Sn 5 are formed
• Over time this is transformed to Cu 3 Sn, causing Kirkendall void
formation
© IMEC 2011
ERIC BEYNE
16

µBUMPS WITH THIN Ni UBM
Introduction of solder diffusion layer: Cu/Ni/Sn
Sn
Cu
Ni
Sn
Ni
Cu
This resolves thermal stability of the µbump prior to
assembly, it however does not avoid the formation of
Cu 3 Sn intermetallics and Kirkendall voids upon ageing at
Cu-bump side
© IMEC 2011
ERIC BEYNE
17

AVOIDING KIRKENDALL VOIDS AND (Cu, Ni) 3 Sn
FORMATION IN THE Ni/ Thin Cu/Sn SYSTEM
Study using blanket layers and controlled thermal ageing at 200ºC
Sn
3.0 µm ECD Sn
Sn
200˚C/96h
Cu
Ni
0.5 µm ECD Cu
1.5 µm ECD Ni
150 nm PVD Cu
30 nm PVD Ti
(Cu,Ni) 6 Sn 5
Ni
2.5h@200C 4h@200C 96h@200C
Sn Sn Sn
(Cu,Ni) 6 Sn 5 (Cu,Ni) 6 Sn 5
(Cu,Ni) 6 Sn 5
No Kirkendall voids and
no cracks observed in the
(Cu, Ni) 6 Sn 5 phase (all
samples), even after long
ageing at high temperature
© IMEC 2011 ERIC BEYNE 18

NOVEL µBUMP SCHEME: Ni/Cu BI-LAYER UBM
Top Si die
Ni/Cu/Sn bump
3-5 µm Ni
0.5-1µm Cu
3-4 µm Sn
0.5-1µm Cu
3-5 µm Ni
Sn
Cu
Ni
Ni/Cu bump
Cu
Bottom Si die
Ni
3-5 µm Ni bump can also be a Cu/Ni bump
© IMEC 2011
ERIC BEYNE
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THERMAL AGEING Ni/Cu/SnTO Ni/Cu
µBUMP CONNECTIONS
After ageing at 150°C for 730 hours only a
single phase (Cu,Ni)6Sn5 is observed
150C/730h
pt Ni Cu Sn Phase
4
Ni/Cu/Sn(2/1/4 um)
1
2
3
Ni
1 9.23 39.73 51.04 ~(Cu, Ni) 6 Sn 5
2 - 10.31 89.69 ~Sn (diff. Cu)
3 8.54 41.80 49.66 ~(Cu, Ni) 6 Sn 5
Ni/Cu(2.5/0.5 um)
Ni
4 - 8.65 91.35 ~Sn (diff. Cu)
• Uniform (Cu, Ni) 6 Sn 5 no (Cu,Ni) 3 Sn
• No Kirkendall voids in (Cu,Ni) 6 Sn 5
• Some remaining Sn
© IMEC 2011
ERIC BEYNE
20

BUMP-PLANARIZATION
DIAMOND BIT CUTTING TECHNIQUE
As deposited bump structures
Wafer
Chuck table
Cutting direction
Cutting bit
Fixed distance
from chuck table
Interconnect line
Wafer
Planarized bumps
Cut Cu surface
R a ~ 9nm / R z ~ 50nm
in collaboration with DISCO
© IMEC 2011 ERIC BEYNE 21

CU-BUMP FLY CUTTING RESULTS
After plating :
After fly-cutting:
passivation opening
• Ra = 0.5 µm
• Rt = 1.7 µm
• Within Die variation = 1.0 µm
• Ra = 0.009 µm
• Rt = 0.033 µm
• Within Die variation = 0.020 µm
in collaboration with DISCO
© IMEC 2011 ERIC BEYNE 22

SN-BUMP FLY CUTTING RESULTS
After plating :
After fly-cutting:
• Ra = 0.25 µm
• Rt = 1.60 µm
• Within Die variation = 0.7 µm
in collaboration with DISCO
• Ra = 0.01 µm
• Rt = 0.05 µm
• Within Die variation = 0.10 µm
© IMEC 2011 ERIC BEYNE 23

CU/SN SOLID METAL BONDING @ 150ºC USING
FLY-CUT CU AND CU/SN BUMPS
Cu and Cu/Sn bumps:
▸ 40 µm bump Ø
▸ 15 µm bump spacing
Bonding conditions:
Cu
▸ max. temperature 150ºC
▸ Nom. pressure 50 MPa
▸ Using a no-flow underfill
Results:
▸ Clear formation of an
intermetallic bond
▸ Very smooth interfaces
after bonding
▸ Some misalignment in this
sample
Cu
Cu x Sn y
© IMEC 2011 ERIC BEYNE 24

OUTLINE
o Introduction: Flip chip Scaling
o Baseline µbump interconnect
o Improving Bond quality
o Die stacking strategies
o Wafer-level underfill
o Conclusion
© IMEC 2011 E.BEYNE 25

3D DIE STACKING APPROACHES
1. Sequential Die-to-package-substrate stacking
1
2
3
- Close to standard packaging practice
- Challenge: substrate warpage after first die assembly will limit µbump
assembly capability for next tier die stacking
1. Sequential Die-to-Wafer stacking, followed by stacked die-topackage
stacking.
2 2
3
1
- Si-Si stacking : highest alignment accuracy, finest pitch and narrow gap between
die possible.
- Challenge: fragile thin TSV bottom wafer Wafer “reconstruction”
© IMEC 2011
ERIC BEYNE
26

© IMEC 2011

WAFER-LEVEL UNDERFILL ASSEMBLY
Wafer-level Spin Coated Underfill
Wafer-level Laminated Film Underfill
Stacking Assembly
Die-to-Die Assembly
Die-to-Wafer Assembly
© IMEC 2011
ERIC BEYNE 28

WAFER-LEVEL LAMINATED WLUF
Good transparency of the WLUF film
PTCM/PTCN stacks
after Assembly
Some (up to 100µm)
underfill squeeze out:
to be minimized
CSAM
T-SCAN
Particle entrapment seen on some bumps seen.
May be also due to bump topography
Initial results:
• Good electrical yields w/high bond force
• Good material transparency
• Good filling capability (no voids and delamination)
© IMEC 2011
SAM : No voids or
delamination seen
ERIC BEYNE 29

TOPOGRAPHY AFTER DIE-TO-WAFER STACKING
25µm thin ETNA test die stacked on DRAM-Die:
Dispensed
NUF (single point)
NO underfill
Laminated WLUF
Sample #1 Sample #2
Significant topography after stacking:
NUF process requires multiple point dispense & accurate volume control.
WLUF allows for flattest assembly, even flatter than when not using
underfill during stacking
May be a problem for multi-tier stacking
Expected to be less severe with thicker die (Die bending stiffness t 3 )
© IMEC 2011 ERIC BEYNE 30

ASSEMBLY MODULE
SUCCESSFUL LOGIC-ON-DRAM STACKING W. FILM-WLUF
SAM: No UF Voids
Topo by optical
profilometry < 2μm
© IMEC 2011 ERIC BEYNE 31

OUTLINE
o Introduction: Flip chip Scaling
o Baseline µbump interconnect
o Improving Bond quality
o Die stacking strategies
o Wafer-level underfill
o Conclusion & Outlook
© IMEC 2011 E.BEYNE 32

CONCLUSIONS
‣ Flip chip scaling results in an increased
importance of the intermetallic phases.
‣ µbump flip-chip for Silicon-to-Silicon relies
on full transformation of the solder joint
into intermetallics
‣ This allows for an improved
electromigration resistance
‣ Requires „bump engineering‟ to
avoid Kirkenadll voiding
‣ What are the pitch limits
µbump solder joining?
© IMEC 2011 E.BEYNE 33

BUMP SIZE DEFINED BY BUMP ALIGNMENT
Contact/no contact and/or contact area reduction
H Sn
Optimum condition : Bump
diameter Ø b = Pad spacing S p
Ø b
Ø P
P
S p
P
Before reaching an open
connection, the bump to pad
contact area is reduced,
resulting in an increase in
contact resistance
Non-contact
area
Non-contact
area
Ø p >Ø b : Capture Solder squeeze-out
Misalignment
Misalignment
H Sn
Ø b
Ø P
Ø’ b
H’ Sn
‣ Ø p ≥ Ø b SQRT(H Sn /H‟ Sn )
‣ Therefore : S = P/(1+SQRT(H Sn /H‟ Sn ))
If e.g. (H Sn /H‟ Sn ) max is 4 : S= P/3
© IMEC 2011
34
Eric
beyne

St.dev. alignment (µm)
SCALING ROADMAP
ALIGNMENT ACCURACY REQUIREMENTS
Required alignment accuracy for a maximum increase in contact resistance
of 100% and a Yield of 99.9999 (4N)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
R/Rn < 2
Y = 4N
P=10µm
0 5 10 15 20 25 30 35 40
© IMEC 2011
P=20µm
P=40µm
Pad Diameter, Dp (µm)
ERIC BEYNE 35
5
10
15
20
25
5
10
3
4
5
Db (µm)
for
P=40µm
Db (µm)
for
P=20µm
Db (µm)
for
P=10µm

ACKNOWLEDGEMENT
3D SYSTEM INTEGRATION PROGRAM
Logic IDM Memory IDM
Foundries
FABLESS
3D Program
SAT
Material Suppliers
EDA
Equipment Suppliers
Lam
RESEARCH
© IMEC 2011 3D SYSTEM INTEGRATION PROGRAM 36

© IMEC 2011