A 90 nm Communication Technology Featuring SiGe HBT ...
A 90 nm Communication Technology Featuring SiGe HBT ... A 90 nm Communication Technology Featuring SiGe HBT ...
A 90 nm Communication Technology Featuring SiGe HBT Transistors, RF CMOS, Precision R-L-C R C RF Elements and 1 mm 2 6-T T SRAM Cell K. Kuhn, M. Agostinelli, , S. Ahmed, S. Chambers, S. Cea, , S. Christensen, P. Fischer, J. Gong, C. Kardas, , T. Letson, , L. Henning, A. Murthy, , H. Muthali, , B. Obradovic, , P. Packan, , S. W. Pae, , I. Post, S. Putna, , K. Raol, , A. Roskowski, , R. Soman, , T. Thomas, P. Vandervoorn, , M. Weiss and I. Young Logic Technology Development Intel Corporation, Hillsboro, OR 97124, USA IEDM 2002 1
- Page 2 and 3: Outline • Technology Features •
- Page 4 and 5: Matching Circuit Needs to Device Ty
- Page 6 and 7: Matching Circuit Needs to Device Ty
- Page 8 and 9: Outline • Technology Features •
- Page 10 and 11: FREQUENCY (GHz) 90nm Communications
- Page 12 and 13: F T : Intrinsic PMOS Performance 50
- Page 14 and 15: Comparison of CMOS: F T and F MAX F
- Page 16 and 17: Criteria for BJT device definition
- Page 18 and 19: HBT: SiGe:C Epitaxy B Ge E C B 0 20
- Page 20 and 21: No CMOS Degradation IOFF [LOG (nA/
- Page 22 and 23: Outline • Technology Features •
- Page 24 and 25: Substrates: Latch-up, P-P versus P+
- Page 26 and 27: Outline • Technology Features •
- Page 28 and 29: TTF seconds (0.2%C at Bias=0V, 1MHz
- Page 30 and 31: Hi-Q Q Inductor Library Templates P
- Page 32 and 33: Measuring Q 0.4 0.2 0.0 Imaginary S
- Page 34 and 35: Hi-Q Q Inductors and substrates PEA
- Page 36 and 37: Validation vehicles GHz 10 9 10GHz
- Page 38 and 39: Conclusions • Manufacturable comm
- Page 40 and 41: References 1. Tiemeijer, L.F.; Boot
- Page 42: A soft copy of this and other recen
A <strong>90</strong> <strong>nm</strong> <strong>Communication</strong> <strong>Technology</strong><br />
<strong>Featuring</strong> <strong>SiGe</strong> <strong>HBT</strong> Transistors,<br />
RF CMOS, Precision R-L-C R C RF<br />
Elements and 1 mm 2 6-T T SRAM Cell<br />
K. Kuhn, M. Agostinelli, , S. Ahmed, S. Chambers, S. Cea, , S. Christensen,<br />
P. Fischer, J. Gong, C. Kardas, , T. Letson, , L. Henning, A. Murthy, , H.<br />
Muthali, , B. Obradovic, , P. Packan, , S. W. Pae, , I. Post, S. Putna, , K. Raol, , A.<br />
Roskowski, , R. Soman, , T. Thomas, P. Vandervoorn, , M. Weiss and I. Young<br />
Logic <strong>Technology</strong> Development<br />
Intel Corporation, Hillsboro, OR 97124, USA<br />
IEDM 2002 1
Outline<br />
• <strong>Technology</strong> Features<br />
• CMOS<br />
• <strong>SiGe</strong>:C <strong>HBT</strong><br />
• Isolation<br />
• Passives<br />
• Validation Vehicles<br />
• Conclusions<br />
IEDM 2002 2
Baseline CMOS<br />
• Shallow Trench Isolation<br />
• CMOS Well Implants<br />
• Thin gate and poly<br />
• Tip implants<br />
• Spacer Formation<br />
• NSD/PSD<br />
• Silicide & contacts<br />
• Metal 1 - 6 Layers<br />
• Metal 7<br />
Integration<br />
<strong>Communication</strong>s<br />
• High resistivity substrate<br />
• Triple Well (deep n-well)<br />
• LP CMOS 15Å (1.2V)<br />
• Analog CMOS 50Å (2.5V)<br />
• <strong>SiGe</strong> <strong>HBT</strong> module<br />
• Poly Resistor<br />
• MIM Capacitor / TF resistor<br />
• Inductors<br />
IEDM 2002 3
Matching Circuit Needs to Device Type<br />
VHS differential<br />
RF power amp<br />
Low-noise amp<br />
Mixer<br />
Op amp<br />
Limiting amp<br />
Switch cap filter<br />
ADC/DAC<br />
Bandgap ref<br />
MUX/DeMUX<br />
VCO<br />
Logic MOS<br />
Analog MOS<br />
?<br />
Precision R<br />
Precision C<br />
Logic and analog MOS are the foundation for the majority of<br />
critical communications circuits<br />
IEDM 2002 4<br />
High-Q L<br />
Varactors<br />
LN BJT<br />
HF BJT<br />
HV BJT<br />
III-V FET<br />
III-V <strong>HBT</strong>
Matching Circuit Needs to Device Type<br />
VHS differential<br />
RF power amp<br />
Low-noise amp<br />
Mixer<br />
Op amp<br />
Limiting amp<br />
Switch cap filter<br />
ADC/DAC<br />
Bandgap ref<br />
MUX/DeMUX<br />
VCO<br />
Logic MOS<br />
Analog MOS<br />
?<br />
Precision R<br />
Precision C<br />
IEDM 2002 5<br />
High-Q L<br />
Varactors<br />
LN BJT<br />
HF BJT<br />
HV BJT<br />
III-V FET<br />
Precision single elements are key to many circuits<br />
III-V <strong>HBT</strong>
Matching Circuit Needs to Device Type<br />
VHS differential<br />
RF power amp<br />
Low-noise amp<br />
Mixer<br />
Op amp<br />
Limiting amp<br />
Switch cap filter<br />
ADC/DAC<br />
Bandgap ref<br />
MUX/DeMUX<br />
VCO<br />
Logic MOS<br />
Analog MOS<br />
?<br />
Precision R<br />
Precision C<br />
Most circuits have multiple implementation paths,<br />
redundancy is important in process definition<br />
IEDM 2002 6<br />
High-Q L<br />
Varactors<br />
LN BJT<br />
?<br />
?<br />
?<br />
HF BJT<br />
?<br />
HV BJT<br />
III-V FET<br />
III-V <strong>HBT</strong>
Matching Circuit Needs to Device Type<br />
VHS differential<br />
RF power amp<br />
Low-noise amp<br />
Mixer<br />
Op amp<br />
Limiting amp<br />
Switch cap filter<br />
ADC/DAC<br />
Bandgap ref<br />
MUX/DeMUX<br />
VCO<br />
Logic MOS<br />
Analog MOS<br />
?<br />
Precision R<br />
Precision C<br />
Specialized BJT devices cover gaps<br />
where MOS falls short<br />
IEDM 2002 7<br />
High-Q L<br />
Varactors<br />
LN BJT<br />
?<br />
?<br />
?<br />
HF BJT<br />
?<br />
HV BJT<br />
III-V FET<br />
III-V <strong>HBT</strong>
Outline<br />
• <strong>Technology</strong> Features<br />
• CMOS<br />
IEDM 2002 8
<strong>90</strong><strong>nm</strong> CMOS<br />
Performance versus Low Power<br />
10000<br />
IOFF (nA/mm)<br />
1000<br />
100<br />
10<br />
1<br />
0.1<br />
Performance<br />
Devices<br />
Low Power<br />
Devices<br />
0.01<br />
0.5 1.5 2.5 3.5<br />
CV/I (Gate delay in pS)<br />
IEDM 2002 9
FREQUENCY (GHz)<br />
<strong>90</strong><strong>nm</strong> <strong>Communication</strong>s CMOS<br />
RF Performance (Low Power Device)<br />
240<br />
200<br />
160<br />
120<br />
NMOS<br />
F T<br />
F MAX<br />
0 0.5 1 1.5<br />
FREQUENCY (GHz)<br />
PMOS<br />
120<br />
100<br />
F T<br />
80<br />
F MAX<br />
60<br />
0 0.5 1<br />
IDSAT (mA/mm)<br />
IDSAT (mA/mm)<br />
NMOS: 225/143 F T /F<br />
PMOS: 114/70 F T /F<br />
(Vg=0.7V, Vds=1.2V)<br />
/F MAX<br />
/F MAX<br />
IEDM 2002 10
F T : Intrinsic NMOS Performance<br />
FT (GHz)<br />
(CUT-OFF FREQUENCY)<br />
500<br />
200<br />
100<br />
50<br />
20<br />
[6]<br />
[3]<br />
[1]<br />
This work<br />
[4]<br />
[2]<br />
10<br />
0.02 0.05 0.1 0.2 0.5 1.0<br />
L GATE (mm)<br />
IEDM 2002 11
F T : Intrinsic PMOS Performance<br />
500<br />
FT (GHz)<br />
(CUT-OFF FREQUENCY)<br />
200<br />
100<br />
50<br />
20<br />
[8]<br />
[7]<br />
This work<br />
[6]<br />
10<br />
0.02 0.05 0.1 0.2 0.5 1.0<br />
L GATE (mm)<br />
IEDM 2002 12
Fmax: : Layout<br />
• Make R G small<br />
Two-sided gates<br />
Minimize field extension<br />
Contacts close to devices<br />
Multiple fingers<br />
• Minimize pad coupling<br />
HiRES substrates<br />
Isolate/shield signal pads<br />
Use higher-level metal<br />
• Minimize cap/scatter<br />
Isolate gate from drain<br />
Taper source bus<br />
Similar to: L. F. Tiemeijer, et al.<br />
“A record high 150 GHz fmax<br />
realized at 0.18 um gate length<br />
in an industrial RF-CMOS<br />
technology,” IEDM 2001.<br />
IEDM 2002 13
Comparison of CMOS: F T and F MAX<br />
FMAX (GHz)<br />
(MAX OSC. FREQUENCY)<br />
250<br />
200<br />
150<br />
100<br />
50<br />
0<br />
[1]<br />
[2] This work<br />
[3]<br />
[4]<br />
[5]<br />
0 100 200 300<br />
F T (GHz)<br />
(CUT-OFF FREQUENCY)<br />
IEDM 2002 14
Outline<br />
• <strong>Technology</strong> Features<br />
• CMOS<br />
• <strong>SiGe</strong>:C <strong>HBT</strong><br />
IEDM 2002 15
Criteria for BJT device definition<br />
• Manufacturing simplicity<br />
• Maximum leverage of the main <strong>90</strong><strong>nm</strong><br />
microprocessor process (all tools shared,<br />
no special tools)<br />
• Meets the needs of the circuit design<br />
community<br />
• No impact to CMOS performance<br />
IEDM 2002 16
<strong>SiGe</strong>:C <strong>HBT</strong> Architecture<br />
Extrinsic base implant<br />
2<br />
1<br />
Emitter poly<br />
B<br />
a.<br />
E<br />
<strong>SiGe</strong><br />
C<br />
Quasi-<br />
Self-aligned<br />
B<br />
b.<br />
1<br />
Replacement emitter<br />
pedestal<br />
Spacer<br />
Fully<br />
Self-aligned<br />
Quasi-self-aligned chosen as the better tradeoff<br />
between manufacturing complexity and performance<br />
IEDM 2002 17
<strong>HBT</strong>: <strong>SiGe</strong>:C<br />
Epitaxy<br />
B<br />
Ge<br />
E<br />
C<br />
B<br />
0 20 40 60 80<br />
Depth (nanometers)<br />
G.L. Patton, et al. “<strong>SiGe</strong>-base heterojunction bipolar transistors: physics and<br />
design issues,” Electron Devices Meeting, 19<strong>90</strong>.<br />
L.D. Lanzerotti et al. “Suppression of boron outdiffusion in <strong>SiGe</strong> <strong>HBT</strong>s by<br />
carbon incorporation,” Electron Devices Meeting, 1996<br />
H.J. Osten, et al. “The effect of carbon incorporation on <strong>SiGe</strong> heterobipolar<br />
transistor performance and process margin,” Electron Devices Meeting, 1997.<br />
IEDM 2002 18
Baseline: 130/100 F T /F<br />
/F MAX<br />
H21 and Mason’s gain (dB)<br />
50<br />
40<br />
30<br />
H21<br />
20<br />
Mason’s gain<br />
10<br />
-20dB/dec<br />
0<br />
0.1 1 10 100 1000<br />
FREQUENCY (GHz)<br />
Cum Prob %<br />
95%<br />
<strong>90</strong>%<br />
80%<br />
70%<br />
50%<br />
30%<br />
20%<br />
10%<br />
5%<br />
80<br />
100<br />
OJ<br />
MH<br />
NI<br />
GF<br />
EB<br />
DC<br />
PA<br />
HO<br />
JM<br />
IG<br />
NP<br />
FE<br />
BD<br />
CA<br />
HHHH I<br />
III<br />
AAAAA<br />
HI GO OOOOOOO HHH III J JJJJJJJ GGGGGGG M MMMMMMM AB BBBBBBB N NNNNNNN PE PPPPPPP EEEEEEE DF C DDDDDDD AA FFFFFFF CCCCCCC<br />
GO<br />
IH<br />
JM<br />
NA<br />
BP<br />
EC<br />
DF<br />
HI<br />
OJ<br />
MN<br />
BC<br />
F<br />
120<br />
140<br />
300 mm BASELINE LOT, WIW and<br />
WTW F T VARIATION (GHz)<br />
IEDM 2002 19
No CMOS Degradation<br />
IOFF [LOG (nA/ /µM)]<br />
-4.0<br />
-4.5<br />
-5.0<br />
-5.5<br />
-6.0<br />
-6.5<br />
-7.0<br />
-7.5<br />
-8.0<br />
-8.5<br />
-9.0<br />
NMOS WITH <strong>HBT</strong><br />
POR NMOS<br />
-6.0<br />
0.60 0.80 1.00 1.20 1.40 -7.0<br />
1.60<br />
IDSAT [mA/µm]<br />
IOFF [LOG (nA/ /µM)]<br />
-4.0<br />
-5.0<br />
-8.0<br />
-9.0<br />
-10.0<br />
-11.0<br />
-12.0<br />
-0.15<br />
-0.25<br />
•NMOS and PMOS<br />
I ON versus I OFF<br />
characteristics are<br />
not degraded by<br />
<strong>HBT</strong> integration<br />
PMOS WITH <strong>HBT</strong><br />
POR PMOS<br />
-0.35<br />
-0.45<br />
IDSAT [mA/µm]<br />
-0.55<br />
-0.65<br />
IEDM 2002 20
BJT Yield issues: impact of volume<br />
Incoming to EPI<br />
OLD Process<br />
Start of epi dep<br />
NEW Process<br />
Start of epi dep<br />
Increased wafer<br />
volume generated<br />
Ge deposits on<br />
chamber walls:<br />
Fixed with purges<br />
and pre-coats<br />
OLD Process<br />
After epi dep<br />
NEW Process<br />
After epi dep<br />
IEDM 2002 21
Outline<br />
• <strong>Technology</strong> Features<br />
• CMOS<br />
• <strong>SiGe</strong>:C <strong>HBT</strong><br />
• Isolation<br />
IEDM 2002 22
Isolation: P-P<br />
versus P+ epi (with DNW)<br />
-20<br />
Guard ring on p+ epi (LoRes)<br />
-40<br />
Guard ring on p- (HiRes)<br />
S21 (dB)<br />
-60<br />
-80<br />
DNW on<br />
P- (HiRes)<br />
DNW on<br />
P+ epi<br />
(LowRes)<br />
-100<br />
10 MHz 100 MHz 1 GHz 10 GHz 100 GHz<br />
FREQUENCY<br />
S21 = forward transmission gain/loss<br />
IEDM 2002 23
Substrates: Latch-up, P-P<br />
versus P+ epi<br />
|CROSSTALK in dB|<br />
80<br />
70<br />
60<br />
50<br />
40<br />
30<br />
24-36<br />
Ω-cm<br />
5.5 µm epi<br />
on p+<br />
24-36<br />
Ω-cm<br />
10 µm epi<br />
on p+<br />
25-45<br />
Ω-cm<br />
Non-epi<br />
13<br />
11<br />
9<br />
7<br />
5<br />
LATCH-UP<br />
OVERVOLTAGE<br />
Merrill, R.B.; Young, W.M.; Brehmer, K. Effect of substrate<br />
material on crosstalk in mixed analog/digital integrated circuits<br />
Electron Devices Meeting, 1994.<br />
IEDM 2002 24
Substrates: Latch-up, P-P<br />
versus P+ epi<br />
with and without DNW<br />
HOLDING VOLTAGE (V)<br />
3.0<br />
2.0<br />
1.0<br />
P-<br />
(50 ohm-cm)<br />
P+ epi<br />
DNW (magenta)<br />
No DNW (cyan)<br />
0.4 77 100 0.4 77 100<br />
N+ TO PWELL TAP<br />
DISTANCE (microns)<br />
IEDM 2002 25
Outline<br />
• <strong>Technology</strong> Features<br />
• CMOS<br />
• <strong>SiGe</strong>:C <strong>HBT</strong><br />
• Isolation<br />
• Passives<br />
IEDM 2002 26
MIM Capacitor<br />
1.10<br />
M7<br />
SiN<br />
V6<br />
Ta<br />
M6<br />
M7<br />
V6<br />
NORMALIZED<br />
CAPACITANCE<br />
1.05<br />
1.00<br />
0.95<br />
0.<strong>90</strong><br />
R38<br />
R58<br />
R60<br />
R68<br />
RB4<br />
RC1<br />
RC9<br />
BASELINE TREND<br />
IEDM 2002 27
TTF seconds<br />
(0.2%C at Bias=0V, 1MHz)<br />
1.E+09<br />
1.E+07<br />
1.E+05<br />
1.E+03<br />
1.E+01<br />
MIM Capacitor BiasTemp. Reliability (T=125C)<br />
0 5 10 15 20 25 30<br />
Bias (V)<br />
317 years<br />
< MIM Cap<br />
Bias Temp.<br />
MIM Cap<br />
CV ><br />
NORMALIZED<br />
CAPCITANCE<br />
1.002<br />
1.0015<br />
1.001<br />
1.0005<br />
1<br />
0.9995<br />
15 -10 -5 0 5 10 15<br />
Bias (V)<br />
IEDM 2002 28
MIM Capacitor Reliability<br />
OLD Process ><br />
Cum %<br />
3<br />
2<br />
1<br />
0<br />
-1<br />
-2<br />
Cum Prob %<br />
99.9%<br />
99%<br />
<strong>90</strong>%<br />
50%<br />
10%<br />
After Stress<br />
Before Stress<br />
0.01 0.1 1 10 100<br />
Qbd (C/cm2)<br />
< New Process<br />
1%<br />
A=5.2k um 2 A=26k um 2 A=130k um 2<br />
0.1%<br />
1.E-07 1.E-06 1.E-05 1.E-04<br />
MIM CAP LEAKAGE AT HIGH BIAS [A]<br />
IEDM 2002 29
Hi-Q Q Inductor Library Templates<br />
PEAK Q<br />
60<br />
50<br />
40<br />
30<br />
20<br />
10<br />
This work<br />
0 0.5 1 1.5 2 2.5<br />
INDUCTANCE (nH)<br />
Literature<br />
Focusing on lower L, Hi-Q inductors to support 10/40G circuits<br />
IEDM 2002 30
Hi-Q Q Inductor Library Templates<br />
60<br />
PEAK Q<br />
70<br />
60<br />
50<br />
40<br />
30<br />
PEAK Q<br />
40<br />
20<br />
0 20 40 60<br />
FREQUENCY OF PEAK Q (GHz)<br />
20<br />
10<br />
0 0.5 1 1.5 2 2.5<br />
This work<br />
INDUCTANCE (nH)<br />
IEDM 2002 31
Measuring Q<br />
0.4<br />
0.2<br />
0.0<br />
Imaginary<br />
Short<br />
De-embedded<br />
-0.2<br />
-0.4<br />
Real<br />
1 GHz<br />
10 GHz<br />
S_dev(1,1)<br />
S_open(1,1)<br />
S_short(1,1)<br />
S_dev_final(1,1)<br />
As Measured<br />
Q =<br />
- Im (Y11)<br />
Re (Y11)<br />
Open<br />
FREQUENCY<br />
(250.0MHz to 50.25GHz)<br />
IEDM 2002 32
Measured versus simulated Q<br />
Inductor Dimension:<br />
Do = 154 um W = 12 um<br />
S = 1 um T = 1.5<br />
20<br />
10<br />
Simulated<br />
Q<br />
0<br />
-10<br />
Measured<br />
1GHz 10 GHz<br />
FREQUENCY<br />
IEDM 2002 33
Hi-Q Q Inductors and substrates<br />
PEAK Q<br />
30<br />
25<br />
20<br />
15<br />
10<br />
5<br />
0<br />
50 ohm-cm<br />
w/o parasitic<br />
control<br />
P+epi<br />
w/o parasitic<br />
control<br />
50 ohm-cm<br />
with parasitic<br />
control<br />
P+ epi<br />
with parasitic<br />
control<br />
0.1 1 10 100<br />
FREQUENCY (GHz)<br />
IEDM 2002 34
Outline<br />
• <strong>Technology</strong> Features<br />
• CMOS<br />
• <strong>SiGe</strong>:C <strong>HBT</strong><br />
• Isolation<br />
• Passives<br />
• Validation Vehicles<br />
• Conclusions<br />
IEDM 2002 35
Validation vehicles<br />
GHz<br />
10<br />
9<br />
10GHz<br />
LC-VCO<br />
Tuning<br />
Curve<br />
8<br />
0.5 1.0 1.5<br />
VCTL<br />
A large variety of learning vehicles are being supported<br />
Illustrated is an LC-VCO from a 10G SerDes test circuit<br />
IEDM 2002 36
Intel CMOS 10G SerDes Test Circuit<br />
Transmit PLL – Measured Jitter<br />
Meets jitter<br />
transfer function<br />
specification ><br />
This work<br />
OC-192<br />
OC-192 Specification is integral<br />
under curve = 100 mUI;<br />
Actual performance is 40 mUI<br />
~ 2X better<br />
IEDM 2002 37
Conclusions<br />
• Manufacturable communications process<br />
integrated into <strong>90</strong><strong>nm</strong> digital CMOS<br />
• RF NMOS devices at 225/140 F T /F<br />
• RF PMOS devices at 114/70 F T /F<br />
/F MAX<br />
/F MAX<br />
• Baseline <strong>HBT</strong> device at 130/100 F T /F<br />
/F MAX<br />
• Reliable 1.15 fF/mm 2 Cu-MIM and resistor<br />
• Hi-Q Q inductors<br />
IEDM 2002 38
Acknowledgment<br />
The authors gratefully acknowledge the<br />
many people at Intel who contributed to this<br />
work, including individuals from the<br />
following organizations:<br />
– PTD Process and Design Groups<br />
– Sort Test <strong>Technology</strong> Development<br />
– Quality and Reliability Engineering<br />
– <strong>Technology</strong> Computer Aided Design<br />
IEDM 2002 39
References<br />
1. Tiemeijer, L.F.; Boots, H.M.J.; Havens, R.J.; Scholten, A.J.; de Vreede, P.H.W.; Woerlee, P.H.; Heringa, A.; Klaassen, D.B.M.<br />
A record high 150 GHz fmax realized at 0.18 um gate length in an industrial RF-CMOS technology<br />
Electron Devices Meeting, 2001. IEDM Technical Digest. International , 2001. Page(s): 10.4.1 -10.4.4<br />
2. Hirose, T.; Momiyama, Y.; Kosugi, M.; Kano, H.; Watanabe, Y.; Sugii, T. A 185 GHz fmax SOI DTMOS with a new metallic<br />
overlay-gate for low-power RF applications. Electron Devices Meeting, 2001. IEDM Technical Digest. International , 2001.<br />
Page(s): 33.5.1 -33.5.3<br />
3. Matsumoto, T.; Maeda, S.; Ota, K.; Hirano, Y.; Eikyu, K.; Sayama, H.; Iwamatsu, T.; Yamamoto, K.; Katoh, T.; Yamaguchi, Y.;<br />
Ipposhi, T.; Oda, H.; Maegawa, S.; Inoue, Y.; Inuishi, M. 70 <strong>nm</strong> SOI-CMOS of 135 GHz fmax with dual offset-implanted<br />
source-drain extension structure for RF/analog and logic applications. Electron Devices Meeting, 2001. IEDM Technical<br />
Digest. International , 2001. Page(s): 10.3.1 -10.3.4<br />
4. Zamdmer, N.; Ray, A.; Plouchart, J.-O.; Wagner, L.; Fong, N.; Jenkins, K.A.; Jin, W.; Smeys, P.; Yang, I.; Shahidi, G.;<br />
Assaderghi, F. A 0.13- um SOI CMOS technology for low-power digital and RF applications VLSI <strong>Technology</strong>, 2001.<br />
Digest of Technical Papers. 2001 Symposium on , 2001. Page(s): 85 -86<br />
5. Momiyama, Y.; Hirose, T.; Kurata, H.; Goto, K.; Watanabe, Y.; Sugii, T. A 140 GHz ft and 60 GHz fmax DTMOS integrated<br />
with high-performance SOI logic technology. Electron Devices Meeting, 2000. IEDM Technical Digest. International , 2000.<br />
Page(s): 451 -454<br />
6. Momose, H.S.; Morifuji, E.; Yoshitomi, T.; Ohguro, T.; Saito, M.; Iwai, H. Cutoff frequency and propagation delay time of<br />
1.5-<strong>nm</strong> gate oxide CMOS. Electron Devices, IEEE Transactions on , Volume: 48 Issue: 6 , June 2001. Page(s): 1165 –1174<br />
7. Lee, K.F.; Yan, R.H.; Jeon, D.Y.; Kim, Y.O.; Tennant, D.M.; Westerwick, E.H.; Early, K.; Chin, G.M.; Morris, M.D.; Johnson,<br />
R.W.; Liu, T.M.; Kistler, R.C.; Voshchenkov, A.M.; Swartz, R.G.; Ourmazd, A. 0.1 mu m p-channel MOSFETs with 51 GHz fT.<br />
Electron Devices Meeting, 1992. Technical Digest., International , 1992. Page(s): 1012 -1014<br />
8. Taur, Y.; Wind, S.; Mii, Y.J.; Lii, Y.; Moy, D.; Jenkins, K.A.; Chen, C.L.; Coane, P.J.; Klaus, D.; Bucchignano, J.; Rosenfield,<br />
M.; Thomson, M.G.R.; Polcari, M. High performance 0.1 um CMOS devices with 1.5 V power supply. Electron Devices<br />
Meeting, 1993. Technical Digest., International , 1993. Page(s): 127 -130<br />
IEDM 2002 40
References<br />
9. Min Park; Seonghearn Lee; Hyun Kyu Yu; Kee Soo Nam Optimization of high Q CMOS-compatible<br />
microwave inductors using silicon CMOS technology. Radio Frequency Integrated Circuits (RFIC)<br />
Symposium, 1997., IEEE , 1997. Page(s): 181 -184<br />
10. Jenei, S.; Decoutere, S.; Maex, K.; Nauwelaers, B. Add-on Cu/SiLK/sup TM/ module for high Q<br />
inductors. IEEE Electron Device Letters , Volume: 23 Issue: 4 , April 2002. Page(s): 173 -175<br />
11. Xiao Huo; Chen, K.J.; Chan, P.C.H. High-Q copper inductors on standard silicon substrate with a<br />
low-k BCB dielectric layer. Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE , 2002<br />
Page(s): 403 -406<br />
12.Hongrui Jiang; Yeh, J.-L.A.; Ye Wang; Norman Tien Electromagnetically shielded high-Q CMOScompatible<br />
copper inductors. Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC.<br />
2000 IEEE International , 2000. Page(s): 330 -331<br />
13. Patton, G.L.; Stork, J.M.C.; Comfort, J.H.; Crabbe, E.F.; Meyerson, B.S.; Harame, D.L.; Sun, J.Y.-C.<br />
<strong>SiGe</strong>-base heterojunction bipolar transistors: physics and design issues Electron Devices Meeting,<br />
19<strong>90</strong>.<br />
14. Lanzerotti, L.D.; St. Amour, A.; Liu, C.W.; Sturm, J.C. Si/Si1-x-y/Gex/Cy/Si heterojunction bipolar<br />
transistors Electron Devices Meeting, 1994 and Lanzerotti, L.D.; Sturm, J.C.; Stach, E.; Hull, R.;<br />
Buyuklimanli, T.; Magee, C. Suppression of boron outdiffusion in <strong>SiGe</strong> <strong>HBT</strong>s by carbon incorporation<br />
Electron Devices Meeting, 1996<br />
15. Osten, H.J.; Lippert, G.; Knoll, D.; Barth, R.; Heinemann, B.; Rucker, H.; Schley, P. The effect of carbon<br />
incorporation on <strong>SiGe</strong> heterobipolar transistor performance and process margin Electron Devices<br />
Meeting, 1997.<br />
IEDM 2002 41
A soft copy of this and other recent Intel<br />
presentations can be found at:<br />
www.intel.com/research/silicon<br />
IEDM 2002 42