AMSV Newsletter 2014

Normalized Power-delay product
In TVLSI 2015
Energy Optimized Sub-threshold VLSI Logic Family with Unbalanced
Pull-up/down Network and Inverse-Narrow-Width Techniques
Ming-Zhong Li, Chio-In Ieong, Man-Kay Law, Pui-In Mak, Mang-I Vai, Sio-Hang Pun and Rui P.
Martins
From Biomedical IC research line
(Accepted in 2014)
Motivation
Ultra-low-energy biomedical applications have
urged the development of a sub-threshold VLSI
logic family in standard CMOS. Instead of the
traditionally preferred balanced pull-up (PU) and
pull-down (PD) network approach in logic cell
design, this work proposes an unbalanced pullup/down
network together with an inversenarrow-width
technique to improve the operating
speed of the individual logic cell. Effective logical
efforts save both power and die area in the process
of device sizing and topology optimization.
Three experimental 14-tap 8-bit finite impulse
response (FIR) filters optimized for ultra-lowvoltage
operation were fabricated in 0.18-μm
CMOS. Measurements show that the optimized
0.45-V and 0.6-V libraries achieve minimum energy
operations at 100 kHz, with a Figure-of-
Merit (FoM) of 0.365 (at 0.31 V) and 0.4632 (at
0.39 V), respectively. They correspond to
35.96% and 18.74% improvements, and the
overall performances are well comparable with
the state-of-the-art.
Power-delay product (J)
10 -17
10 -18
10 -19
Architecture
10 -15 Operating
with balancing
w/o balancing
frequency limit
10 -16 difference
(unbalanced)
40%
30%
20%
10%
0%
10 3 10 4 10 5 10 6
Frequency (Hz)
10 7
Difference in power-delay product
4.0
3.2
2.4
1.6
WNMOS = 0.88 mm
WNMOS = 0.66 mm
WNMOS = 0.44 mm
WNMOS = 0.22 mm
0.8
0.2 0.4 0.6 0.8 1 1.2 1.4
PMOS Width (mm)
Power-delay product of an inverter (FO4 loading) with balanced (P/N ratio =
5/1) and unbalanced (P/N ratio = 2/1) PU/PD network vs. operating frequency
at 0.3 V (left); Normalized power-delay product of a FO4 inverter at various
NMOS/PMOS widths at 0.3 V (right).
0.5
NMOS VT (V)
Minimum
PMOS |VT|
-0.41
PMOS VT (V)
0.5
Minimum PMOS
|VT| interval @
400 – 590 nm
-0.46
Minimum
Minimum
NMOS VT
NMOS VT
@ 220 nm
0.42
-0.49 0.42
-0.5
0 0.5 1 1.5 2 2.5
0.1 0.5 0.9 1.3 1.7 2.1 2.5
Transistor Length (mm)
Transistor Width (mm)
NMOS/PMOS VT vs. transistor length (left); Transistor width (right)
at VDD = 0.3 V.
NMOS VT (V)
INW
PMOS VT (V)
System Implementation
Verification
Normalized Energy/Cycle
1.0
0.6
0.2
Circuit with 0.30-V .lib
Circuit with 0.45-V .lib
Circuit with 0.60-V .lib
0.32V
0.44V
0.34V
0
0.25 0.35 0.45 0.55
Power Supply Voltage (V)
Normalized Energy/Cycle
Circuit with 0.30-V .lib
Circuit with 0.45-V .lib
1.0
Circuit with 0.60-V .lib
0.6
0.28V
0.39V
0.2 0.31V
0
0.25 0.35 0.45 0.55
Power Supply Voltage (V)
0.35 mm
0.3 V liberty
file (.lib)
based FIR
0.33 mm
0.2 mm
0.265 mm
0.45 V liberty
file (.lib)
based FIR
0.25 mm
0.196 mm
0.6 V liberty
file (.lib)
based FIR
Die micrographs of the 0.18-µm sub-threshold FIR test chips using the 0.3V,
0.45V and 0.6V liberty file.
Die micrographs of the 0.18-µm sub-threshold FIR test chips using the 0.3V,
0.45V and 0.6V liberty file.
Number of Chips
5
4
3
2
1
σ = 0.0678 pJ
μ = 0.3829 pJ
0
0 0.33 0.37 0.41 0.45 0.49 0.53 0.60
Energy/Cycle (pJ)
Number of Chips
4
3
2
1
σ = 0.0543 pJ
μ = 0.4995 pJ
0
0 0.41 0.45 0.49 0.53 0.57 0.63
Energy/Cycle (pJ)
Die micrographs of the 0.18-µm sub-threshold FIR test chips using the 0.3V,
0.45V and 0.6V liberty file.