AMSV Newsletter 2014
AMSV Newsletter 2014
AMSV Newsletter 2014
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Selected works from each research line<br />
In ESSCIRC <strong>2014</strong><br />
An 11b 900 MS/s Time-Interleaved Sub-ranging Pipelined-SAR ADC<br />
[Best Paper Award]<br />
Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui P. Martins<br />
From Data Conversion and Signal Processing research line<br />
Motivation<br />
The highly Time-Interleaved(TI) SAR ADC with<br />
timing-calibration obtains the best power efficiency<br />
for the GHz speed goal, which removes<br />
the power and accuracy trade-off in the clock<br />
generator. However, the calibration sensitivity is<br />
limited by the type of input signal or the other<br />
non-idealities among sub-SAR ADCs such as<br />
reference noise, offset and gain mismatches.<br />
The skew calibration achieves better than 63dB<br />
SFDR in a TI-SAR ADC with GHz sampling rate<br />
and 10b resolution, while the calibration power<br />
from offset, gain and timing occupies near 50%<br />
total ADC power. This paper presents an 11b TI<br />
-sub-ranging pipelined-SAR ADC that achieves<br />
a maximum 1.1GS/s sampling rate with competitive<br />
power-efficiency as compared with the<br />
timing-calibrated TI-SAR ADCs. We propose the<br />
optimization Based on ADC’s sampling frontend<br />
for better SFDR by using the proposed<br />
channel-selection-embedded bootstrap rather<br />
than timing-calibration.<br />
Architecture<br />
Channel Selection Embedded (CSE)<br />
Bootstrap Circuit<br />
Φ 1(Φ 2)<br />
ΦM<br />
Φ1<br />
Vin<br />
Φ2<br />
Vdd<br />
2 Main S/H<br />
channels<br />
CSE<br />
Bootstrap<br />
A1<br />
CSE<br />
Bootstrap<br />
A2<br />
CF<br />
CF<br />
Vin<br />
6 Sub-S/H channels<br />
Φ1,1<br />
Φ1,2<br />
Φ1,3<br />
Φ2,1<br />
Φ2,2<br />
Φ2,3<br />
VB1(B2)<br />
DAC<br />
DAC<br />
DAC<br />
DAC<br />
DAC<br />
DAC<br />
Bootstraped<br />
switch<br />
M4<br />
A1(A2) M3<br />
V dd<br />
M1<br />
Φ P1(Φ P2)<br />
M2<br />
Φ s(Φ s)<br />
Φ M<br />
System Implementation<br />
Power (dB)<br />
System Implementation<br />
Gain Mismatches offset Mismatches<br />
0<br />
fs=900MS/s, fin=11MHz<br />
HD3<br />
HD2<br />
HD4<br />
HD5 HD8<br />
-100<br />
Verification<br />
Power (dB)<br />
0 0.1 0.2 0.3 0.4 0.5<br />
Normalized Frequency (fin / fs)(decimate by 25)<br />
Skew/Gain Mismatches offset Mismatches<br />
0<br />
SNR = 51.7 dB, SNDR = 51.5 dB, fs=900MS/s, fin=431MHz<br />
SFDR = 65.9 dB, THD = -64.3 dB<br />
HD3<br />
HD8 HD2<br />
-100<br />
0 0.1 0.2 0.3 0.4 0.5<br />
Normalized Frequency (fin / fs)(decimate by 25)<br />
SNDR & SFDR (dB)<br />
70<br />
68<br />
66<br />
64<br />
62<br />
60<br />
58<br />
56<br />
54<br />
52<br />
50<br />
SFDR<br />
SNR<br />
SNDR<br />
CLK Jitter 650fs<br />
10 100 200 300 400 500<br />
Input frequency (MHz) @f s=900MS/s<br />
Verification<br />
[1]<br />
[2]<br />
[3]<br />
[8]<br />
ISSCC’14 ISSCC’14 JSSCC’13 VLSI’13<br />
This Work<br />
Architecture<br />
Technology (nm)<br />
TI-SAR<br />
40<br />
TI-SAR<br />
65<br />
TI-SAR<br />
65<br />
Pipeline<br />
65<br />
TI-Pipelined-SAR<br />
65<br />
Resolution (bit)<br />
Sampling Rate (MS/s)<br />
Supply Voltage (V)<br />
10<br />
1.62<br />
1.1<br />
10<br />
1<br />
1<br />
10<br />
2.8<br />
1<br />
10<br />
0.8<br />
1.2<br />
11<br />
0.9<br />
1.2/1.2<br />
11<br />
1.1<br />
1.2/1.3<br />
Input Swing (Vp-p)<br />
1<br />
N/A N/A<br />
1.8 1.2 1.2<br />
SNDR @DC (dB)<br />
SNDR @Nyq. (dB)<br />
51<br />
48<br />
53.5<br />
51.2<br />
53.5<br />
51.2<br />
51<br />
48<br />
57.6<br />
51.5<br />
56.2<br />
50.7<br />
SFDR @Nyq. (dB) 62 60 55<br />
N/A 65.9 64<br />
DNL/INL (LSB)<br />
N/A 0.1/0.1 N/A 0.7/1.8 0.66/1.5 0.69/1.6<br />
Area (mm 2 )<br />
0.83<br />
0.78<br />
1.7<br />
0.18<br />
0.15<br />
Power (mW)<br />
71<br />
19.8<br />
44.6<br />
19 15.5 18<br />
FoM @DC (fJ/conv.step) 150<br />
51 56<br />
53 28 32<br />
FoM @Nyq. (fJ/conv.step) 210<br />
62 78<br />
71 56 58<br />
Require Timing Correction Yes Yes Yes No No<br />
Calibration (on-chip)<br />
Offset, gain,<br />
time<br />
Offset Offset, time No Offset