AMSV Newsletter 2014

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900MS/s 11b ADC (65nm) State-of-the-Art Chips - Designed and Tested in 2014 (9 chips) DCSP Chips Integrated Power Chips A 123-Phase DC-DC Converter-Ring with Fast-DVS for Microprocessors (65nm) 430μm Ch.1 Ch.2 2 nd -stage 1 st -stage 340μm CLK Gen. Output Buffers Wireless Chips High efficient 5GHz ADC (65nm) A VCO-based Switched-Capacitor DC-DC Converter with Segment Frequency Modulation Control for Fast Recovery (65nm) BME (Biomedical Engineering) Chips Ultra-high Area Efficient and Low- Power Wireless Receiver (65nm) Single Chip Solar Energy Harvesting IC (180nm) Supply Modulated Micro-stimulator with Energy Recycling (180nm) ISSCC 2015 µNMR Transceiver for Chemical/Biological Diagnosis and Ultra-low Power Wavelet Shrinkage ECG Processor (180nm) Optogenetic Frontend IC and Nested- Current-Mirror Amplifier (180nm) Four PhD students and one assistant professor from the University of Macau (UM) State Key Laboratory of Analog and Mixed-Signal VLSI (AMS-VLSI Lab) and Faculty of Science and Technology attended the Institute of Electrical and Electronics Engineer’s (IEEE) 62 nd International Solid-State Circuits Conference (ISSCC) in February 2015, which is considered the ‘Chip Olympics’, the most competitive conference in the field of chip design. The 6 papers from UM were "A 5.5mW 6b 5GS/s 4-times Interleaved 3b/cycle SAR ADC in 65nm CMOS", "A Multi- Step Multi-Sample µNMR Relaxometer Using Inside-Magnet Digital Microfluidics and a Butterfly-Coil-Input CMOS Transceiver", "A 12b 180MS/s 0.068mm 2 Full-Calibration- Integrated Pipelined-SAR ADC", "A 123-Phase DC-DC Converter-Ring with Fast-DVS for Microprocessors", "A 0.028mm 2 11mW Single-Mixing Blocker-Tolerant Receiver with Double-RF N-Path Filtering, S 11 Centering, +13dBm OB-IIP 3 and 1.5-to-2.9dB NF", and "A 2-/3-Phase Fully- Integrated Switched-Capacitor DC-DC Converter in Bulk- CMOS for Energy-Efficient Digital Circuits With 14% Efficiency Improvement". There included 2 Pre-Doctoral Achievement Awards and 2 Student Research Previews. UM’s 1st book in Power Electronics UM PhD graduates to join the world’s No 1 mobile chip maker and Asia’s largest fabless IC design company Four PhD graduates from SKL AMS-VLSI recently passed their oral defenses, with external examiners unanimously praising their works for reaching world-class standards. The 4 new doctors are Un Ka-Fai, Yan Zushu, Lin Zhicheng, and Lin Fujian. Two of them have received job contracts from Qualcomm in the United States, which is the world’s No 1 mobile chip maker. One has joined Mediatek in Singapore, which is Asia’s largest fabless IC design company and ranks No 4 in the world. The last has decided to stay at UM as a post-doctoral researcher. US Patents granted in 2014 1. C. Shi, M. K. Law and A. Bermak, “Method and Apparatus for Energy Harvesting using CMOS Sensor”, US Patent, US8629386 B2, Jan. 14, 2014. 2. Chi-Hang Chan, Yan Zhu, U-Fat Chio, Sai-Weng Sin, Seng-Pan U and Martins, R.P., "Comparator and Calibration Thereof", US Patent, US8829942 B2, Sept. 9, 2014.
Selected works from each research line In ESSCIRC 2014 An 11b 900 MS/s Time-Interleaved Sub-ranging Pipelined-SAR ADC [Best Paper Award] Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui P. Martins From Data Conversion and Signal Processing research line Motivation The highly Time-Interleaved(TI) SAR ADC with timing-calibration obtains the best power efficiency for the GHz speed goal, which removes the power and accuracy trade-off in the clock generator. However, the calibration sensitivity is limited by the type of input signal or the other non-idealities among sub-SAR ADCs such as reference noise, offset and gain mismatches. The skew calibration achieves better than 63dB SFDR in a TI-SAR ADC with GHz sampling rate and 10b resolution, while the calibration power from offset, gain and timing occupies near 50% total ADC power. This paper presents an 11b TI -sub-ranging pipelined-SAR ADC that achieves a maximum 1.1GS/s sampling rate with competitive power-efficiency as compared with the timing-calibrated TI-SAR ADCs. We propose the optimization Based on ADC’s sampling frontend for better SFDR by using the proposed channel-selection-embedded bootstrap rather than timing-calibration. Architecture Channel Selection Embedded (CSE) Bootstrap Circuit Φ 1(Φ 2) ΦM Φ1 Vin Φ2 Vdd 2 Main S/H channels CSE Bootstrap A1 CSE Bootstrap A2 CF CF Vin 6 Sub-S/H channels Φ1,1 Φ1,2 Φ1,3 Φ2,1 Φ2,2 Φ2,3 VB1(B2) DAC DAC DAC DAC DAC DAC Bootstraped switch M4 A1(A2) M3 V dd M1 Φ P1(Φ P2) M2 Φ s(Φ s) Φ M System Implementation Power (dB) System Implementation Gain Mismatches offset Mismatches 0 fs=900MS/s, fin=11MHz HD3 HD2 HD4 HD5 HD8 -100 Verification Power (dB) 0 0.1 0.2 0.3 0.4 0.5 Normalized Frequency (fin / fs)(decimate by 25) Skew/Gain Mismatches offset Mismatches 0 SNR = 51.7 dB, SNDR = 51.5 dB, fs=900MS/s, fin=431MHz SFDR = 65.9 dB, THD = -64.3 dB HD3 HD8 HD2 -100 0 0.1 0.2 0.3 0.4 0.5 Normalized Frequency (fin / fs)(decimate by 25) SNDR & SFDR (dB) 70 68 66 64 62 60 58 56 54 52 50 SFDR SNR SNDR CLK Jitter 650fs 10 100 200 300 400 500 Input frequency (MHz) @f s=900MS/s Verification [1] [2] [3] [8] ISSCC’14 ISSCC’14 JSSCC’13 VLSI’13 This Work Architecture Technology (nm) TI-SAR 40 TI-SAR 65 TI-SAR 65 Pipeline 65 TI-Pipelined-SAR 65 Resolution (bit) Sampling Rate (MS/s) Supply Voltage (V) 10 1.62 1.1 10 1 1 10 2.8 1 10 0.8 1.2 11 0.9 1.2/1.2 11 1.1 1.2/1.3 Input Swing (Vp-p) 1 N/A N/A 1.8 1.2 1.2 SNDR @DC (dB) SNDR @Nyq. (dB) 51 48 53.5 51.2 53.5 51.2 51 48 57.6 51.5 56.2 50.7 SFDR @Nyq. (dB) 62 60 55 N/A 65.9 64 DNL/INL (LSB) N/A 0.1/0.1 N/A 0.7/1.8 0.66/1.5 0.69/1.6 Area (mm 2 ) 0.83 0.78 1.7 0.18 0.15 Power (mW) 71 19.8 44.6 19 15.5 18 FoM @DC (fJ/conv.step) 150 51 56 53 28 32 FoM @Nyq. (fJ/conv.step) 210 62 78 71 56 58 Require Timing Correction Yes Yes Yes No No Calibration (on-chip) Offset, gain, time Offset Offset, time No Offset
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AMSV Newsletter 2014

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