AMSV Newsletter 2014

State Key Lab of Analog and Mixed-Signal VLSI (SKL AMS-VLSI)
Newsletter
Motto: “Locally, from (World) Quality towards (National) Quantity”
座 右 銘 : 立 足 本 土 、 人 才 培 養 , 以 世 界 級 質 量 創 建 國 家 級 規 模
Year 4
No . 4
2014 Milestones
March 2015
Co-Funded by
Macao Science and Technology
Development Fund (FDCT)
Events
President Xi Jinping visited UM, and listened to the report of SKL (AMSV-VLSI) research achievements. President Xi
mentioned that was happy to see the self-developed state-of-the-art leading chips and encouraged our team to contribute
further to China high-level strategy policy of "Leading by Innovation" - as quoted by online Chinese Media.
At Macao Science and Technology Awards presented this
year, SKL AMS-VLSI won two 2nd and one 3rd prizes in
the Technological Invention Award category. Also, Technology
Development Award was granted to 3 PhD students
and 1 Master Student from SKL AMS-VLSI
SKL AMS-VLSI awarded "Excellence in INNOVATION"
by Business Awards of Macau on Nov-2014

900MS/s 11b ADC (65nm)
State-of-the-Art Chips - Designed and Tested in 2014 (9 chips)
DCSP Chips
Integrated Power Chips
A 123-Phase DC-DC Converter-Ring with Fast-DVS for
Microprocessors (65nm)
430μm
Ch.1
Ch.2
2 nd -stage
1 st -stage
340μm
CLK Gen.
Output Buffers
Wireless Chips
High efficient 5GHz ADC (65nm)
A VCO-based Switched-Capacitor DC-DC Converter with Segment
Frequency Modulation Control for Fast Recovery (65nm)
BME (Biomedical Engineering) Chips
Ultra-high Area Efficient and Low-
Power Wireless Receiver (65nm)
Single Chip Solar Energy
Harvesting IC (180nm)
Supply Modulated Micro-stimulator
with Energy Recycling (180nm)
ISSCC 2015
µNMR Transceiver for Chemical/Biological Diagnosis and
Ultra-low Power Wavelet Shrinkage ECG Processor (180nm)
Optogenetic Frontend IC and Nested-
Current-Mirror Amplifier (180nm)
Four PhD students and one assistant professor from the University of Macau (UM) State Key Laboratory of Analog
and Mixed-Signal VLSI (AMS-VLSI Lab) and Faculty of Science and Technology attended the Institute of Electrical
and Electronics Engineer’s (IEEE) 62 nd International Solid-State Circuits Conference (ISSCC) in February 2015,
which is considered the ‘Chip Olympics’, the most competitive conference in the field of chip design.
The 6 papers from UM were "A 5.5mW 6b 5GS/s 4-times
Interleaved 3b/cycle SAR ADC in 65nm CMOS", "A Multi-
Step Multi-Sample µNMR Relaxometer Using Inside-Magnet
Digital Microfluidics and a Butterfly-Coil-Input CMOS
Transceiver", "A 12b 180MS/s 0.068mm 2 Full-Calibration-
Integrated Pipelined-SAR ADC", "A 123-Phase DC-DC
Converter-Ring with Fast-DVS for Microprocessors", "A
0.028mm 2 11mW Single-Mixing Blocker-Tolerant Receiver
with Double-RF N-Path Filtering, S 11 Centering, +13dBm
OB-IIP 3 and 1.5-to-2.9dB NF", and "A 2-/3-Phase Fully-
Integrated Switched-Capacitor DC-DC Converter in Bulk-
CMOS for Energy-Efficient Digital Circuits With 14% Efficiency
Improvement". There included 2 Pre-Doctoral
Achievement Awards and 2 Student Research Previews.
UM’s 1st book in
Power Electronics
UM PhD graduates to join the world’s No 1 mobile chip maker and Asia’s largest
fabless IC design company
Four PhD graduates from SKL AMS-VLSI recently
passed their oral defenses, with external examiners
unanimously praising their works for
reaching world-class standards. The 4 new doctors
are Un Ka-Fai, Yan Zushu, Lin Zhicheng,
and Lin Fujian. Two of them have received job
contracts from Qualcomm in the United States,
which is the world’s No 1 mobile chip maker. One
has joined Mediatek in Singapore, which is
Asia’s largest fabless IC design company and
ranks No 4 in the world. The last has decided to
stay at UM as a post-doctoral researcher.
US Patents granted in 2014
1. C. Shi, M. K. Law and A. Bermak, “Method and Apparatus for Energy Harvesting using CMOS Sensor”, US
Patent, US8629386 B2, Jan. 14, 2014.
2. Chi-Hang Chan, Yan Zhu, U-Fat Chio, Sai-Weng Sin, Seng-Pan U and Martins, R.P., "Comparator and
Calibration Thereof", US Patent, US8829942 B2, Sept. 9, 2014.

Selected works from each research line
In ESSCIRC 2014
An 11b 900 MS/s Time-Interleaved Sub-ranging Pipelined-SAR ADC
[Best Paper Award]
Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui P. Martins
From Data Conversion and Signal Processing research line
Motivation
The highly Time-Interleaved(TI) SAR ADC with
timing-calibration obtains the best power efficiency
for the GHz speed goal, which removes
the power and accuracy trade-off in the clock
generator. However, the calibration sensitivity is
limited by the type of input signal or the other
non-idealities among sub-SAR ADCs such as
reference noise, offset and gain mismatches.
The skew calibration achieves better than 63dB
SFDR in a TI-SAR ADC with GHz sampling rate
and 10b resolution, while the calibration power
from offset, gain and timing occupies near 50%
total ADC power. This paper presents an 11b TI
-sub-ranging pipelined-SAR ADC that achieves
a maximum 1.1GS/s sampling rate with competitive
power-efficiency as compared with the
timing-calibrated TI-SAR ADCs. We propose the
optimization Based on ADC’s sampling frontend
for better SFDR by using the proposed
channel-selection-embedded bootstrap rather
than timing-calibration.
Architecture
Channel Selection Embedded (CSE)
Bootstrap Circuit
Φ 1(Φ 2)
ΦM
Φ1
Vin
Φ2
Vdd
2 Main S/H
channels
CSE
Bootstrap
A1
CSE
Bootstrap
A2
CF
CF
Vin
6 Sub-S/H channels
Φ1,1
Φ1,2
Φ1,3
Φ2,1
Φ2,2
Φ2,3
VB1(B2)
DAC
DAC
DAC
DAC
DAC
DAC
Bootstraped
switch
M4
A1(A2) M3
V dd
M1
Φ P1(Φ P2)
M2
Φ s(Φ s)
Φ M
System Implementation
Power (dB)
System Implementation
Gain Mismatches offset Mismatches
0
fs=900MS/s, fin=11MHz
HD3
HD2
HD4
HD5 HD8
-100
Verification
Power (dB)
0 0.1 0.2 0.3 0.4 0.5
Normalized Frequency (fin / fs)(decimate by 25)
Skew/Gain Mismatches offset Mismatches
0
SNR = 51.7 dB, SNDR = 51.5 dB, fs=900MS/s, fin=431MHz
SFDR = 65.9 dB, THD = -64.3 dB
HD3
HD8 HD2
-100
0 0.1 0.2 0.3 0.4 0.5
Normalized Frequency (fin / fs)(decimate by 25)
SNDR & SFDR (dB)
70
68
66
64
62
60
58
56
54
52
50
SFDR
SNR
SNDR
CLK Jitter 650fs
10 100 200 300 400 500
Input frequency (MHz) @f s=900MS/s
Verification
[1]
[2]
[3]
[8]
ISSCC’14 ISSCC’14 JSSCC’13 VLSI’13
This Work
Architecture
Technology (nm)
TI-SAR
40
TI-SAR
65
TI-SAR
65
Pipeline
65
TI-Pipelined-SAR
65
Resolution (bit)
Sampling Rate (MS/s)
Supply Voltage (V)
10
1.62
1.1
10
1
1
10
2.8
1
10
0.8
1.2
11
0.9
1.2/1.2
11
1.1
1.2/1.3
Input Swing (Vp-p)
1
N/A N/A
1.8 1.2 1.2
SNDR @DC (dB)
SNDR @Nyq. (dB)
51
48
53.5
51.2
53.5
51.2
51
48
57.6
51.5
56.2
50.7
SFDR @Nyq. (dB) 62 60 55
N/A 65.9 64
DNL/INL (LSB)
N/A 0.1/0.1 N/A 0.7/1.8 0.66/1.5 0.69/1.6
Area (mm 2 )
0.83
0.78
1.7
0.18
0.15
Power (mW)
71
19.8
44.6
19 15.5 18
FoM @DC (fJ/conv.step) 150
51 56
53 28 32
FoM @Nyq. (fJ/conv.step) 210
62 78
71 56 58
Require Timing Correction Yes Yes Yes No No
Calibration (on-chip)
Offset, gain,
time
Offset Offset, time No Offset

Normalized Power-delay product
In TVLSI 2015
Energy Optimized Sub-threshold VLSI Logic Family with Unbalanced
Pull-up/down Network and Inverse-Narrow-Width Techniques
Ming-Zhong Li, Chio-In Ieong, Man-Kay Law, Pui-In Mak, Mang-I Vai, Sio-Hang Pun and Rui P.
Martins
From Biomedical IC research line
(Accepted in 2014)
Motivation
Ultra-low-energy biomedical applications have
urged the development of a sub-threshold VLSI
logic family in standard CMOS. Instead of the
traditionally preferred balanced pull-up (PU) and
pull-down (PD) network approach in logic cell
design, this work proposes an unbalanced pullup/down
network together with an inversenarrow-width
technique to improve the operating
speed of the individual logic cell. Effective logical
efforts save both power and die area in the process
of device sizing and topology optimization.
Three experimental 14-tap 8-bit finite impulse
response (FIR) filters optimized for ultra-lowvoltage
operation were fabricated in 0.18-μm
CMOS. Measurements show that the optimized
0.45-V and 0.6-V libraries achieve minimum energy
operations at 100 kHz, with a Figure-of-
Merit (FoM) of 0.365 (at 0.31 V) and 0.4632 (at
0.39 V), respectively. They correspond to
35.96% and 18.74% improvements, and the
overall performances are well comparable with
the state-of-the-art.
Power-delay product (J)
10 -17
10 -18
10 -19
Architecture
10 -15 Operating
with balancing
w/o balancing
frequency limit
10 -16 difference
(unbalanced)
40%
30%
20%
10%
0%
10 3 10 4 10 5 10 6
Frequency (Hz)
10 7
Difference in power-delay product
4.0
3.2
2.4
1.6
WNMOS = 0.88 mm
WNMOS = 0.66 mm
WNMOS = 0.44 mm
WNMOS = 0.22 mm
0.8
0.2 0.4 0.6 0.8 1 1.2 1.4
PMOS Width (mm)
Power-delay product of an inverter (FO4 loading) with balanced (P/N ratio =
5/1) and unbalanced (P/N ratio = 2/1) PU/PD network vs. operating frequency
at 0.3 V (left); Normalized power-delay product of a FO4 inverter at various
NMOS/PMOS widths at 0.3 V (right).
0.5
NMOS VT (V)
Minimum
PMOS |VT|
-0.41
PMOS VT (V)
0.5
Minimum PMOS
|VT| interval @
400 – 590 nm
-0.46
Minimum
Minimum
NMOS VT
NMOS VT
@ 220 nm
0.42
-0.49 0.42
-0.5
0 0.5 1 1.5 2 2.5
0.1 0.5 0.9 1.3 1.7 2.1 2.5
Transistor Length (mm)
Transistor Width (mm)
NMOS/PMOS VT vs. transistor length (left); Transistor width (right)
at VDD = 0.3 V.
NMOS VT (V)
INW
PMOS VT (V)
System Implementation
Verification
Normalized Energy/Cycle
1.0
0.6
0.2
Circuit with 0.30-V .lib
Circuit with 0.45-V .lib
Circuit with 0.60-V .lib
0.32V
0.44V
0.34V
0
0.25 0.35 0.45 0.55
Power Supply Voltage (V)
Normalized Energy/Cycle
Circuit with 0.30-V .lib
Circuit with 0.45-V .lib
1.0
Circuit with 0.60-V .lib
0.6
0.28V
0.39V
0.2 0.31V
0
0.25 0.35 0.45 0.55
Power Supply Voltage (V)
0.35 mm
0.3 V liberty
file (.lib)
based FIR
0.33 mm
0.2 mm
0.265 mm
0.45 V liberty
file (.lib)
based FIR
0.25 mm
0.196 mm
0.6 V liberty
file (.lib)
based FIR
Die micrographs of the 0.18-µm sub-threshold FIR test chips using the 0.3V,
0.45V and 0.6V liberty file.
Die micrographs of the 0.18-µm sub-threshold FIR test chips using the 0.3V,
0.45V and 0.6V liberty file.
Number of Chips
5
4
3
2
1
σ = 0.0678 pJ
μ = 0.3829 pJ
0
0 0.33 0.37 0.41 0.45 0.49 0.53 0.60
Energy/Cycle (pJ)
Number of Chips
4
3
2
1
σ = 0.0543 pJ
μ = 0.4995 pJ
0
0 0.41 0.45 0.49 0.53 0.57 0.63
Energy/Cycle (pJ)
Die micrographs of the 0.18-µm sub-threshold FIR test chips using the 0.3V,
0.45V and 0.6V liberty file.

Voltage
Voltage
In American Institute of Physics – Advances 2014
Natural Discharge after Pulse and Cooperative Electrodes to
Enhance Droplet Velocity in Digital Microfluidics
Tianlan Chen, Cheng Dong, Jie Gao, Yanwei Jia, Pui-In Mak, Mang-I Vai, and Rui P. Martins
From Multidisciplinary Research Area
Motivation
Architecture
Digital Microfluidics (DMF) is a promising technology
for biological/chemical micro-reactions
due to its distinct droplet manageability via electronic
automation, but the limited velocity of
droplet transportation has hindered DMF from
utilization in high throughput applications.
In this paper, by adaptively fitting the actuation
voltages to the dynamic motions of droplet
movement under real-time feedback monitoring,
two control-engaged electrode-driving techniques:
Natural Discharge after Pulse (NDAP)
and Cooperative Electrodes (CE) are proposed.
They together lead to, for the first time, enhanced
droplet velocity with lower root mean
square voltage value.
uα
uβ
uβ’
0
uα
uβ
uβ’
0
HV period
tα’
LV period
tβ
tα
1 st electrode
tthc
tths
tths
Time
NDAP
2 nd electrode
NDAP + CE
(a)
(b)
uα
0
uα
0
Sketches of four possible electrode-driving schemes for droplet movements
over two electrodes: (a) Natural Discharge after Pulse (NDAP): The highvoltage
(HV) period lasts shorter, while the low-voltage (LV) under natural
discharge lasts longer with short pulse recharging periodically. (b) DC signal.
(c) NDAP with cooperative electrodes (CE) overlaps the charging time of
neighboring electrodes. (d) DC plus CE driving. (e) Droplet moving toward
two target electrodes and location of the two thresholds on the first target
electrode. The electrode was grounded when the charging was done in all
schemes.
tthc
tths
tths
Time
DC
DC + CE
(c)
(d)
thc
ths
1st
2nd
(e)
Result I
Result II
(a) Velocity comparison of NDAP signals with different and DC. NDAP with
13-ms to 100-ms has average velocities higher than DC signal. (b) Video
frames of a droplet actuated by NDAP and DC crossing 2 electrodes
(Multimedia view). Video was captured by a high speed camera (Nikon V2),
which has a maximum frame rate up to 1200 frames/second (resolution 320
x 120 pixels). A LED light was set in the same frame to light on when the
electrode was being charged. Individual frames extracted from the videos
were analyzed by the image processing software Image J to obtain the
v droplet.
Comparison between the proposed (NDAP + CE and high-speed feedback)
and classical (DC) schemes for droplet movements in a long run of 3 s: (a)
Droplet successfully moved across 12 electrodes when it was controlled by
the proposed scheme. The path of the droplet’s center had been shortened
at electrode No. 6 by CE, which charged electrode No. 7 before the droplet
reached electrode No. 6, resulting in an upward move of droplet in advance.
The whole droplet transportation was recorded in video (Multimedia view).
(b) Droplet failed to complete movement in 3 s due to its lower speed. The
moving path was close to the right angle at the two corners. The whole
droplet transportation was recorded in video (Multimedia view). (c) Instantaneous
velocity of the droplet moving across the electrodes. As expected,
droplet controlled by the proposed scheme moved across electrode No. 6-7-
8 using a much shorter time than that of the classical procedure.

In Royal Society of Chemistry - Analyst 2014
NMR-DMF: A Modular Nuclear Magnetic Resonance–Digital
Microfluidics System for Biological Assays
Ka-Meng Lei, Pui-In Mak, Man-Kay Law, and Rui P. Martins
From Multidisciplinary Research Area
Motivation
Architecture I
We present a modular nuclear magnetic resonance–digital
microfluidics (NMR-DMF) system
as a portable diagnostic platform for miniaturized
biological assays.
With increasing numbers of combination between
designed probes and a specific target,
NMR becomes an accurate and rapid assay tool
capable of detecting particular kinds of proteins,
DNAs, bacteria and cells with a customized
probe quantitatively.
Traditional sample operation (e.g., manipulation
and mixing) relied heavily on human efforts. We
herein propose a modular NMR-DMF system to
allow electronic automation of multi-step reaction-screening
protocols.
The overall schematics and operations of the NMR-DMF system. (a) The
placement of the DMF chip, magnet, RF coil and PCB board in 3D view. Benefit
from the plane-parallel magnetic field generated by the figure-8 shaped coil,
the NMR system can be effectively integrated into the DMF system; (b) Schematics
of the NMR Electronics. The transmitter which is formed by the digital
logics such as flip flops is used to excite the hydrogen atom. On the receiver
part, the capacitor together with the RF-coil (fabricated figure-8 shaped coil)
forms a LC tank to provide passive gain enhancing of the system’s sensitivity.
The signal is then amplified and down converted to f IF (intermediate frequency)
and fed to the external filters and oscilloscope; (c) The filtered results from the
PCB are captured by the oscilloscope for easier demonstration purpose.
Waveforms are then analysed and the spin-spin relaxation time (T 2) is fitted by
the algorithm written in MATLAB; (d) The photograph of the DMF chip and
structure of the DMF platform. The droplets are squeezed between the top and
bottom planes and surrounded by silicone oil; (e) The detection mechanism of
the NMR-DMF system. The target-specific magnetic nanoparticles, which act
as probes, are placed on the sensing site initially (in purple). The samples at
other electrodes (in cyan) will be transported to the sensing site and mixed with
the probes to perform NMR assays automatically by applying voltage on corresponding
electrodes. Without the target, the probes stay monodispersed and
will have a longer T 2. Otherwise, the target and probes will form clusters by
forming bonds between each other and the T 2 will be decreased.
Architecture II
Result
(a) Plot of unit magnetic field in y-direction of the 14-turn figure-8 shaped coil
along z-axis. The magnetic field is stronger on the coil surface (1.8 mT) and
starts to decrease above the coil. Inset shows the photograph of the 14-turn
figure-8 shaped coil; (b) The magnetic flux lines of the simulated 14-turn
figure-8 shaped coil. The magnetic fluxes are still pointing in the z-direction
at the centres of each coil. However, between the two coils, the magnetic
flux is pointing in the y-direction, generating plane-parallel magnetic flux. (c)
Plane-parallel magnetic flux density map of the 14-turn figure-8 shaped coil
at z = 0.6 mm (depth of the ITO glass). The sensing region, which is defined
as the area have a plane-parallel magnetic flux density larger than 50% its
peak value (1.43 mT) is located between the centers of two coils and has a
shape of circle with diameter around 4.2 mm.
(a) Illustration of droplets mixing. The droplets at electrode no. 1 (samples)
and no. 8 (probe) were driven to electrode no.7 and mixed together. (b) The
NMR assay results from the mixed droplets. Biotinylated magnetic nanoparticles
acted as a probe. If the samples do not contain avidin, the nanoparticles
will stay monodispersed and a longer T 2 will be obtained (181.5 ms). If
avidin is with the samples, avidin and biotin will combine to form rigid bond
and clusters will be presented. In consequence, T 2 will be decreased by the
perturbation of the magnetic nanoparticle clusters (86.13 ms). This shows
that the system is capable of detecting the existence of protein in the samples
in a fully-automated way.

In ISSCC 2014 and JSSC 2014
A 0.5V 1.15mW 0.2mm 2 Sub-GHz ZigBee Receiver Supporting
433/860/915/960MHz ISM Bands with Zero External Components
[ISSCC 2014 Highlight]
Zhicheng Lin, Pui-In Mak and Rui P. Martins
From Wireless IC research line
Motivation
Architecture
The rapid proliferation of Internet of Things
has urged the development of ultra-low-power
(ULP) radios at the lowest possible cost, while
being universal for worldwide markets.
This work is a single-0.5V ULP receiver for
sub-GHz ZigBee (IEEE 802.15.4c/d) products.
With 1.15mW of power and 0.2mm 2 of area,
the receiver shows 8.1-dB NF and –20.5dBm
IIP 3 over the 433/860/915/960MHz ISM bands
apt for China, Europe, North America and Japan,
respectively, with zero external component.
System Implementation
Verification

A 123-Phase DC-DC Converter-Ring with Fast-DVS for
Microprocessors
Yan Lu, Junmin Jiang, Wing-Hung Ki, C. Patrick Yue, Sai-Weng Sin, Seng-Pan U, and Rui P.
Martins
From Integrated Power research line
In ISSCC 2015
(Accepted in 2014)
Motivation
Inspired by The Square of Vatican City, a fully-integrated
step-down switched-capacitor DC-DC converter-ring with
100+ phases is designed with a fast-DVS (dynamic voltage
scaling) feature for the microprocessor in portable/
wearable devices.
Switched-capacitor power converters (SCPCs) are preferred
for full integration because the capacitor density
has increased significantly in nm processes. Multiphase
architecture for ripple reduction can be easily built into the
SCPC with little power and area overheads.
This symmetrical ring-shaped converter surrounds its load
in the square and supplies the on-chip power grid, such
that a good quality power supply can be easily accessed
at any point of the chip edges. There are 30 phases on
the top edge and 31 phases on each of the other 3 edges,
making 123 phases in total. The phase number and unit
cell dimensions of this architecture can easily be modified
to fit the floor plan of the load.
By using the proposed VDD-controlled oscillator (V DD CO)
the frequency of which is controlled by varying its supply
voltage, a hitherto unexplored feature of the multiphase
DC-DC architecture is exposed: the control-loop unity
gain frequency (UGF) could be designed to be higher
than the switching frequency.
Architecture
For the conventional PFM topology that uses a centralized
current-starved (CS) voltage-controlled oscillator (VCO) and
distributed clock phases, the upper limit on phase number is
due to the matching of phases and routings; and its dominant
pole is usually set at the VCTL node.
For the proposed topology, the error amplifier (EA) with
NMOS source follower buffer stage drives the VDDCO which
is distributed and localized to every phase that makes it free
of matching and routing problems. Now, VDDC is a lowimpedance
node and the associated pole is located at high
frequencies; and the output pole becomes the dominant pole
and the bandwidth is extended.
System Implementation
Verification

Events and Visits
Visit by Mr. Ma Chi Ngai Frederico, President of FDCT
Visit by Prof. Bai Chun Li, President of Chinese
Academy of Sciences
Distinguished Lectures on Microelectronics and Biomedical Engineering
IEEE Solid-State Circuits Society 2014 Distinguished Lecture Workshop -
Macau by Prof. Jan Van der Spiegel, University of Pennsylvania, Prof. Tzi
-Dar Chiueh, National Taiwan University, Prof. Howard Luong, HKUST
2-Day Workshop on Integrated Power and Energy in Semiconductor
by Prof. LEO LORENZ, IEEE Fellow, Member of German National Academy
of Sciences, President of European Center of Power Electronics (ECPE)
A/D Converter Circuit and Architecture Design for High-speed
Data Communication by
Prof. Boris MURMANN, Stanford University, USA
Biosensors - Playing at the Crossroads of Engineering and the Sciences
by
Dr. M. Jamal Deen FRSC, McMaster University, Canada
Two New Academics Joined SKL AMS-VLSI
Dr. Jun Yin received the B.Sc. and the M.Sc. degrees in Microelectronics from Peking University, Beijing, China, in 2004 and 2007,
respectively, and the Ph.D. degree in Electronic and Computer Engineering (ECE) from Hong Kong University of Science and Technology
(HKUST), Hong Kong, China, in 2013.
Research Interests: CMOS RF and mm-Wave integrated circuits for wireless communication and wireless sensing systems.
Dr. Yan Lu received the B.Eng. and M.Sc. degrees in Microelectronic Engineering from South China University of Technology, Guangzhou,
China, in 2006 and 2009, respectively; and the Ph.D. degree in Electronic and Computer Engineering from the Hong Kong University
of Science and Technology, Hong Kong, China, in 2013. He was a Visiting Scholar at University of Twente, the Netherlands, in
2013 for four months.
Research interests: Wireless power transfer systems, fully-integrated DC-DC converters, low-dropout regulators and RF energy harvesting.

SCI Journals – 20 Papers
▓ Hugo Horta, R. P. Martins, "The start-up, evolution and impact of a research group in a university developing its knowledge base",
Tertiary Education and Management, Taylor & Francis, vol. 20, No.4, pp. 280-293, Dec. 2014
▓ Zhicheng Lin, Pui-In Mak, R. P. Martins, "A Sub-GHz Multi-ISM-Band ZigBee Receiver Using Function-Reuse and Gain-Boosted N-Path
Techniques for IoT Applications", IEEE Journal of Solid-State Circuits, vol. 49, Issue 12, pp. 2990 - 3004, Dec. 2014
▓ Fujian Lin, Pui-In Mak, R. P. Martins, "An RF-to-BB-Current-Reuse Wideband Receiver with Parallel N-Path Active/Passive Mixers and a
Single-MOS Pole-Zero LPF", IEEE Journal of Solid-State Circuits, vol. 49, Nov. 2014
▓ D. G. Chen, F. Tang, M. K. Law, X. Zhong and A. Bermak, "A 64-fJ/step 9-bit SAR ADC Array with Forward Error Correction and mixed
-signal CDS for CMOS Image Sensors," IEEE Transactions on Circuits and Systems-I, vol. 61, issue 11, pp. 3085-3093, Nov.
2014
▓ Md.Tawfiq Amin, Pui-In Mak and R. P. Martins, "A 0.137-mm 2 9-GHz Hybrid Class-B/C QVCO with Output Buffering in 65-nm CMOS,"
IEEE Microwave and Wireless Components Letters, vol. 24, pp. 716-718, Oct. 2014
▓ Zhicheng Lin, Pui-In Mak, R. P. Martins, "Analysis and Modeling of a Gain-Boosted N-Path Switched-Capacitor Bandpass Filter", IEEE
Transactions on Circuits and Systems – I, vol. 9, pp. 2560-2568, Sept. 2014
▓ NingYi Dai, Chi-Seng Lam, WenChen Zhang, “Multifunctional voltage source inverter for renewable energy integration and power
quality conditioning”, The Scientific World Journal, vol. 2014, Aug. 2014
▓ K. M. Lei, P. I. Mak, M. K. Law and R. P. Martins, “NMR-DMF: A Modular Nuclear Magnetic Resonance-Digital Microfluidics System for
Biological Assays,” RSC Analyst, 2014, 139, 6204-6213, Aug. 2014
▓ Zhicheng Lin, Pui-In Mak, R. P. Martins, "A 0.14-mm 2 , 1.4-mW, 59.4 dB-SFDR, 2.4-GHz ZigBee/WPAN Receiver Exploiting a Split-LNTA
+ 50% LO Topology in 65-nm CMOS", IEEE Transactions on Microwave Theory and Techniques, vol. 62, pp. 1525-1534 , Jul.
2014
▓ Zhicheng Lin, Pui-In Mak, R. P. Martins, "A 2.4-GHz ZigBee Receiver Exploiting an RF-to-BB-Current-Reuse Blixer + Hybrid Filter
Topology in 65-nm CMOS", IEEE Journal of Solid-State Circuits, vol. 49, pp. 1333-1344, Jun. 2014
▓ Pui-In Mak, Miao Liu, Yaohua Zhao, R. P. Martins, "Enhancing the Performances of Recycling Folded Cascode OpAmp in Nanoscale
CMOS through Voltage Supply Doubling and Design for Reliability", Wiley International Journal of Circuit Theory and Applications,
vol. 42, pp. 605-619, Jun. 2014
▓ Yan Lu, Wing-Hung Ki, “A 13.56 MHz CMOS Active Rectifier with Switched-Offset and Compensated Biasing for Biomedical Wireless
Power Transfer Systems”, IEEE Transactions on Biomedical Circuits and Systems, vol. 8, pp.334-344, Jun. 2014
▓ C. H. Chen, S. H. Pun, P. U. Mak, M. I. Vai, A. Klug, et al., "Circuit Models and Experimental Noise Measurements of Micropipette
Amplifiers for Extracellular Neural Recordings from Live Animals," BioMed Research International, vol. 2014, p. 14, Jun. 2014
▓ Chi-Seng Lam, Man-Chung Wong, Wai-Hei Choi, Xiao-Xi Cui, Hong-Ming Mei, Jian-Zheng Liu, “Design and Performance of an adaptive
low dc voltage controlled LC-hybrid active power filter with a neutral inductor in three-phase four-wire power systems”, IEEE
Transactions on Industrial Electronics, vol. 61, no. 6, pp. 2635-2647, Jun. 2014
▓ D. G. Chen, F. Tang, M. K. Law and A. Bermak, “A 12 pJ/pixel Analog-to-Information Converter based 816 x 640 Pixel CMOS Image
Sensor”, IEEE Journal of Solid-State Circuits, vol. 49, issue 5, pp. 1210-1222, May 2014
▓ Ning-Yi Dai, Man-Chung Wong, Keng-Weng Lao, Chi-Kong Wong, “Modelling and control of a railway power conditioner in co-phase
traction power system under partial compensation”, IET Power Electronics, vol. 7, no. 5, pp. 1044 - 1054, May 2014
▓ Tianlan Chen, Cheng Dong, Jie Gao, Yanwei Jia, Pui-In Mak, Mang-I Vai and R. P. Martins, “Natural Discharge after Pulse and Cooperative
Electrodes to Enhance Droplet Velocity in Digital Microfluidics,” AIP Advances, Apr. 2014
▓ Fujian Lin, Pui-In Mak, R. P. Martins, "A Sine-LO Square-Law Harmonic-Rejection Mixer – Theory, Implementation and Application",
IEEE Transactions on Microwave Theory and Techniques, vol. 62, pp. 313-322, Feb. 2014
▓ B. Wang, M. K. Law, A. Bermak and H. C. Luong, “A Passive RFID Tag Embedded Temperature Sensor With Improved Process Spreads
Immunity for a -30 o C to 60 o C Sensing Range”, IEEE Transactions on Circuits and Systems I, pp. 337 – 346, Feb. 2014
▓ Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P. Martins, F. Maloberti, "Split-SAR ADCs: Improved Linearity With
Power and Speed Optimization," IEEE Transactions on Very Large Scale Integration Systems, vol.22, no.2, pp.372,383, Feb.
2014
Conferences – 23 Papers
Major solid-state circuits conferences
International Solid-State Circuits Conference (ISSCC) 2014, San Francisco, CA, USA, Feb. 2014
▓ “A 0.0013mm 2 3.6µW Nested-Current-Mirror Single-Stage Amplifier Driving 0.15-to-15nF Capacitive Loads with >62° Phase Margin”
[Pre-Doctoral Achievement Award]
▓ "An RF-to-BB current-reuse wideband receiver with parallel N-path active/passive mixers and a single-MOS pole-zero LPF"
▓ "A 0.5V 1.15mW 0.2mm 2 Sub-GHz ZigBee receiver supporting 433/860/915/960MHz ISM bands with zero external components"
▓ "Circuit Techniques for Switched-Capacitor Filters" [Student Research Preview]
European Solid-State Circuits Conference (ESSCIRC) 2014, Venice, Italy, Sept. 2014
▓ “An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC” [Best Paper Award]
Other conferences:
APPEEC 2014, Hong Kong, China, Dec. 2014
▓ “An adaptive hysteresis band PWM control for hybrid active power filters in fixed frequency”
ISIC 2014, Singapore, Dec. 2014
▓ “A 0.3-V 37.5-nW 1.5~6.5-Input-Range Supply Voltage Tolerant Capacitive Sensor Readout”
BMEiCON 2014, Fukuoka, Japan, Nov. 2014
▓ “Investigation on Error Performance for Galvanic-type Intra-body Communication with Experiment”
APCCAS 2014, Okinawa, Japan, Nov. 2014
▓ “A Low-Dropout Regulator with Power Supply Rejection Improvement by Bandwidth-Zero Tracking”
▓ “Analysis of Two-Phase on-Chip Step-Down Switched Capacitor Power Converter”
▓ “Co-Design of a Low-Noise Receiver Front-End and its Exciting-Sensing Coil for Portable NMR-Screening of Chemical/Biological Droplets”
▓ “A 104μW EMI-Resisting Bandgap Voltage Reference Achieving –20dB PSRR, and 5% DC Shift under a 4dBm EMI Level”
Lab-on-a-Chip Asia 2014, Singapore, Nov. 2014
▓ “Time-Regulated Actuation Signal for Enhancement of Droplet Transportation in Digital Microfluidics”
▓ “Electrical Actuation on Digital Microfluidics with a Ta2O5 Insulating Layer: a Comparison Study”
GCBME 2014 & APCMBE 2014, Tainan, Taiwan, Oct. 2014
▓ “Initial Design of the Capacitive Micromachined Ultrasonic Transducers (CMUT) with Helmholtz Resonance Aperture”
ECCE 2014, Pittsburgh, PA, USA, Sept. 2014
▓ “Hybrid railway power conditioner with partial compensation for rating optimization”
IC-TEMS 2014, ZhuHai, GuangDong, China, Jul. 2014
▓ “The Fabrication and Application of a Robust and Intelligent Digital Microfluidics”
ICIEA 2014, Hangzhou, China, Jun. 2014
▓ “Modeling of novel single flow zinc-nickel battery for energy storage system”
ISCAS 2014, Melbourne, Australia, Jun. 2014
▓ “A High Voltage Zero-Static Current Voltage Scaling ADC Interface Circuit for Micro-Stimulator”
▓ “Micropower Two-Stage Amplifier Employing Recycling Current-Buffer Miller Compensation”
EDSSC 2014, Chengdu, China, Jun. 2014
▓ “A 26.3 dBm 2.5 to 6 GHz Wideband Class-D Switched-Capacitor Power Amplifier with 40% Peak PAE ”
ICBME 2013, Singapore, Dec. 2013
▓ “Effect of Transmitter and Receiver Electrodes Configurations on the Capacitive Intrabody Communication Channel from 100 kHz to 100 MHz”
▓ ”Channel Modeling and Simulation for Galvanic Coupling Intra-body Communication”
State Key Laboratory of Analog and Mixed-Signal VLSI / UM
http://www.amsv.umac.mo