Micron ® PISMO ™ Module Data Sheet
Micron ® PISMO ™ Module Data Sheet
Micron ® PISMO ™ Module Data Sheet
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Advance ‡<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Introduction<br />
<strong>Micron</strong> <strong>®</strong> <strong>PISMO</strong> <strong>Module</strong> <strong>Data</strong> <strong>Sheet</strong><br />
<strong>PISMO</strong>2-00001: Mobile DDR SDRAM + NAND Flash<br />
Introduction<br />
Features<br />
The <strong>PISMO</strong> (Platform Independent Storage MOdule) specification provides a standard<br />
external interface to ease memory performance evaluation. This document<br />
describes the mechanical and functional features, configuration options, and design<br />
specifications of a <strong>Micron</strong> <strong>®</strong> <strong>PISMO</strong>2-compliant module. This small, stackable module<br />
features a combination of Mobile DDR SDRAM and NAND Flash memory, as described<br />
in Table 1. The board includes:<br />
Three memory chip footprints (only two are in use at once)<br />
Bottom connector to the host system (J2)<br />
Top connector (J1, for stacking multiple boards)<br />
64Kb serial EEPROM for configuration and presence detection<br />
<strong>PISMO</strong>2-00001 options and part markings are described in Figure 12 on page 21. Reference<br />
documents and data sheets are listed in Table 9 on page 21.<br />
Physical <strong>Module</strong> Mechanics<br />
Stackable memory module (up to four active modules)<br />
Plain rectangular PCB (60mm x 50mm)<br />
Stacking height: 7mm (other stacking heights will become available later)<br />
Supports additional debugging tools (for example, a logic analyzer adapter)<br />
Supports spacers with or without screw option<br />
Supported Memory Interfaces<br />
Dynamic memory: 128Mb, 256Mb, 512Mb, and 1Gb; x32; 1.8V <strong>Micron</strong> Mobile DDR<br />
SDRAM MT46HxxM32LF<br />
NAND memory: 1Gb; x8 or x16; 1.8V NAND Flash memory MT29F1G08BB or<br />
MT29F1G16AB<br />
Serial EEPROM for presence detection: 64Kb<br />
PDF: 09005aef827fda9b/Source: 09005aef827fda71 <strong>Micron</strong> Technology, Inc., reserves the right to change products or specifications without notice.<br />
<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 1 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by<br />
<strong>Micron</strong> without notice. Products are only warranted by <strong>Micron</strong> to meet <strong>Micron</strong>’s production data sheet specifications.
Table 1: <strong>PISMO</strong>2-00001 <strong>Module</strong> Memory Technologies<br />
Advance<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Features<br />
Technology Density Voltage <strong>Data</strong> Bus Package<br />
Mobile DDR SDRAM 128Mb to 1Gb 1.8V 32-bit 90-ball VFBGA<br />
NAND Flash 1Gb 1.8V 8- or 16-bit,<br />
multiplexed<br />
63-ball FBGA<br />
Figure 1: <strong>Micron</strong> Mobile DDR SDRAM and NAND <strong>PISMO</strong>2 <strong>Module</strong> (<strong>PISMO</strong>2-00001)<br />
Top side<br />
(Lock)<br />
J5<br />
<strong>Micron</strong> Part-Specific Features<br />
C14<br />
C3<br />
C4 C34<br />
C15<br />
J1<br />
Mobile<br />
DDR<br />
U3<br />
Bottom side<br />
NAND<br />
(x16)<br />
U10 (x16)<br />
NAND<br />
(x8)<br />
U11 (x8)<br />
For part-specific features, refer to the data sheets listed on any of the following <strong>Micron</strong><br />
product pages:<br />
Mobile DDR SDRAM—www.micron.com/products/mobiledram/ddrsdram<br />
NAND Flash—www.micron.com/products/nand<br />
PDF: 09005aef827fda9b/Source: 09005aef827fda71 <strong>Micron</strong> Technology, Inc., reserves the right to change products or specifications without notice.<br />
<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 2 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
J2<br />
C35<br />
(CS)<br />
(PWR)<br />
R12<br />
R11<br />
U9<br />
C36<br />
C6<br />
C29<br />
C13<br />
R20 1.8<br />
R19 3.3<br />
RN8<br />
RN7<br />
R14<br />
RN6<br />
RN5<br />
RN4<br />
RN3<br />
R8<br />
RN2<br />
RN1<br />
R7<br />
C18<br />
C2<br />
R6 R3<br />
C31<br />
C33<br />
C30 C21 C5<br />
C20<br />
C32<br />
C19 C26<br />
C24<br />
C27 C28<br />
C1<br />
C25<br />
C17<br />
C16<br />
C48<br />
R23<br />
(1V8)<br />
R21<br />
C22<br />
C47<br />
C46<br />
R9<br />
R10<br />
R15<br />
(CS)<br />
R18<br />
R16<br />
R17<br />
C41 C40<br />
C43<br />
R22<br />
C42<br />
C39 C38 C37<br />
C44 C45<br />
C23
Pin Assignments and Descriptions<br />
Advance<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Pin Assignments and Descriptions<br />
Table 3 on page 4 and Table 4 on page 5 illustrate the signal locations within the bottom<br />
and top <strong>PISMO</strong>2-00001 connectors, respectively. The meanings of the signal name<br />
prefixes are explained in Table 2.<br />
Table 2: Naming Conventions for <strong>PISMO</strong>2 Specification Signals<br />
Signal Prefix Definition<br />
SM The “SM_” prefix identifies <strong>PISMO</strong>2 static memory interface signals. This<br />
interface supports NOR Flash, DiskOnChip, SRAM and PSRAM memory, and<br />
memory-mapped I/O devices.<br />
DM The “DM_” prefix identifies <strong>PISMO</strong>2 dynamic memory interface signals. This<br />
interface supports single data rate (SDR) or double data rate (DDR) SDRAM<br />
memory.<br />
NA The “NA_” prefix identifies <strong>PISMO</strong>2 NAND memory interface signals. This<br />
interface supports NAND Flash memory.<br />
FS The “FS_” prefix identifies <strong>PISMO</strong>2 serial memory interface signals. This<br />
interface supports serial Flash memory or I/O devices with a serial bus<br />
interface.<br />
AUX The “AUX_” prefix identifies <strong>PISMO</strong>2 module management interface<br />
signals. This interface supports hardware production and testing, module<br />
control functions, and plug-and-play enumeration.<br />
PDF: 09005aef827fda9b/Source: 09005aef827fda71 <strong>Micron</strong> Technology, Inc., reserves the right to change products or specifications without notice.<br />
<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 3 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.
Advance<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Pin Assignments and Descriptions<br />
Table 3: <strong>PISMO</strong>2-00001 Bottom Connector (J2) Pin Assignments<br />
Col. Row A Row B Row C Row D Row E Row F Row G Row H<br />
1 DM_DQS3_DH DM_DQS3_DL DNU11 DM_CS1_N VSS46 FS_SCK FS_SO FS_RESET_N<br />
2 DM_D26 DM_D24 DM_BA2 DM_A15 DM_A4 VSS45 FS_SI FS_HOLD_N<br />
3 DM_D27 DM_D25 DM_RESET_N DM_A7 DM_A6 FS_V33_0 DNU9 FS_CS3_N<br />
4 DM_D29 DM_D28 DM_ODT1 DM_A11 DM_A9 VSS44 FS_VIO_1 FS_CS2_N<br />
5 DM_D30 DM_D31 DM_ODT0 DM_CKE1 DM_CKE0 VSS43 FS_VIO_0 FS_CS1_N<br />
6 DM_DQS1_DH DM_DQS1_DL DM_VREF DM_A14 DM_DQM3 VSS42 FS_V18_0 FS_CS0_N<br />
7 DM_D8 DM_D9 DM_VIO_9 DM_A8 DM_A12 VSS41 FS_WP_N AUX_SA2<br />
8 DM_D10 DM_D11 DM_VIO_3 DM_DQM1 DM_A5 VSS40 AUX_SCL AUX_SA1<br />
9 DM_D12 DM_D13 DM_VIO_6 VSS37 VSS38 VSS39 AUX_SDA AUX_SA0<br />
10 DM_D15 DM_D14 DM_VIO_5 DM_CLK1_DH DM_CLK1_DL VSS36 AUX_TDI AUX_TDO<br />
11 DM_D1 DM_D0 DM_VIO_8 VSS34 VSS35 AUX_V33_1 AUX_TCK AUX_TMS<br />
12 DM_D3 DM_D2 DM_VIO_4 DM_CLK0_DH DM_CLK0_DL VSS33 DNU13 AUX_PRESENT_N<br />
13 DM_D5 DM_D4 DM_VCC_3 VSS31 VSS32 AUX_V33_0 AUX_POR_N AUX_HMR_N<br />
14 DM_D6 DM_D7 DM_VIO_2 DM_A10 DM_A2 VSS30 AUX_V33_2 AUX_STANDBY_N<br />
15 DM_DQS0_DH DM_DQS0_DL DM_VIO_7 DM_WE_N DM_CS0_N VSS29 NA_RY_3 NA_LCK<br />
16 DM_D16 DM_D17 DM_VCC_2 DM_DQM0 DM_A13 NA_VIO_2 NA_IO15 NA_IO7<br />
17 DM_D19 DM_D18 DM_VCC_1 DM_RAS_N DM_CAS_N VSS28 NA_IO14 NA_IO6<br />
18 DM_D22 DM_D20 DM_VIO_1 DM_BA1 DM_BA0 VSS27 NA_IO13 NA_IO5<br />
19 DM_D23 DM_D21 DM_VIO_0 DM_A1 DM_A0 VSS26 NA_IO12 NA_IO4<br />
20 DM_DQS2_DH DM_DQS2_DL DM_VCC_0 DM_DQM2 DM_A3 VSS25 NA_IO11 NA_IO3<br />
21 VSS20 VSS21 VSS22 VSS23 VSS24 NA_VIO_1 NA_IO10 NA_IO2<br />
22 SM_D23 SM_D31 SM_V33_2 SM_A30 SM_A31 VSS19 NA_IO9 NA_IO1<br />
23 SM_D22 SM_D30 SM_V33_1 SM_A28 SM_A29 VSS18 NA_IO8 NA_IO0<br />
24 SM_D21 SM_D29 SM_V33_0 SM_A26 SM_A27 VSS17 DNU12 NA_PRE<br />
25 SM_D20 SM_D28 SM_VIO_8 SM_A24 SM_A25 VSS16 NA_RY_0 NA_RE_N<br />
26 SM_D19 SM_D27 SM_VIO_7 SM_A22 SM_A23 NA_VIO_0 NA_CS2_N NA_CS3_N<br />
27 SM_D18 SM_D26 SM_VIO_6 SM_A20 SM_A21 NA_V33_0 NA_CS1_N NA_CS0_N<br />
28 SM_D17 SM_D25 SM_VIO_5 SM_A18 SM_A19 NA_V18_0 NA_CLE NA_ALE<br />
29 SM_D16 SM_D24 SM_CLK3 SM_A16 SM_A17 VSS15 NA_WE_N NA_WP_N<br />
30 DNU16 VSS12 SM_CLK2 VSS13 SM_BE2 VSS14 NA_RY_1 NA_RY_2<br />
31 DNU17 VSS9 SM_CLK1 VSS10 SM_BE3 SM_OE_N VSS11 DNU4<br />
32 SM_D7 SM_D15 SM_CLK0 SM_A14 SM_A15 SM_WE_N VSS8 DNU3<br />
33 SM_D6 SM_D14 SM_VIO_4 SM_A12 SM_A13 SM_LBA_N VSS7 SM_WP_N<br />
34 SM_D5 SM_D13 SM_VIO_3 SM_A10 SM_A11 SM_BUSY_N_0 VSS6 SM_RESET_N<br />
35 SM_D4 SM_D12 SM_VIO_2 SM_A8 SM_A9 SM_BWAIT_N VSS5 SM_PD<br />
36 SM_D3 SM_D11 SM_VIO_1 SM_A6 SM_A7 VSS4 SM_BUSY_N_2 SM_BUSY_N_3<br />
37 SM_D2 SM_D10 SM_VIO_0 SM_A4 SM_A5 VSS3 SM_IRQ_N SM_CS3_N<br />
38 SM_D1 SM_D9 SM_V18_2 SM_A2 SM_A3 VSS2 SM_CRE SM_CS2_N<br />
39 SM_D0 SM_D8 SM_V18_1 SM_A0 SM_A1 VSS1 SM_DMARQ_N SM_CS1_N<br />
40 DNU14 DNU15 SM_V18_0 SM_BE0 SM_BE1 VSS0 SM_BUSY_N_1 SM_CS0_N<br />
PDF: 09005aef827fda9b/Source: 09005aef827fda71 <strong>Micron</strong> Technology, Inc., reserves the right to change products or specifications without notice.<br />
<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 4 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.
Table 4: <strong>PISMO</strong>2-00001 Top Connector (J1) Pin Assignments<br />
Advance<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Pin Assignments and Descriptions<br />
Col. Row A Row B Row C Row D Row E Row F Row G Row H<br />
1 DM_DQS3_DH DM_DQS3_DL DNU11 DM_VIO VSS46 FS_SCK FS_SO FS_RESET_N<br />
2 DM_D26 DM_D24 DM_BA2 DM_A15 DM_A4 VSS45 FS_SI FS_HOLD_N<br />
3 DM_D27 DM_D25 DM_RESET_N DM_A7 DM_A6 FS_V33_0 DNU9 FS_CS3_N<br />
4 DM_D29 DM_D28 DM_ODT1 DM_A11 DM_A9 VSS44 FS_VIO_1 FS_CS2_N<br />
5 DM_D30 DM_D31 DM_ODT0 DM_CKE1 DM_CKE0 VSS43 FS_VIO_0 FS_CS1_N<br />
6 DM_DQS1_DH DM_DQS1_DL DM_VREF DM_A14 DM_DQM3 VSS42 FS_V18_0 FS_CS0_N<br />
7 DM_D8 DM_D9 DM_VIO_9 DM_A8 DM_A12 VSS41 FS_WP_N AUX_SA1<br />
8 DM_D10 DM_D11 DM_VIO_3 DM_DQM1 DM_A5 VSS40 AUX_SCL AUX_SA0<br />
9 DM_D12 DM_D13 DM_VIO_6 VSS37 VSS38 VSS39 AUX_SDA AUX_V33<br />
10 DM_D15 DM_D14 DM_VIO_5 DM_CLK1_DH DM_CLK1_DL VSS36 AUX_TDI AUX_TDO<br />
11 DM_D1 DM_D0 DM_VIO_8 VSS34 VSS35 AUX_V33_1 AUX_TCK AUX_TMS<br />
12 DM_D3 DM_D2 DM_VIO_4 DM_CLK0_DH DM_CLK0_DL VSS33 DNU13 AUX_PRESENT_N<br />
13 DM_D5 DM_D4 DM_VCC_3 VSS31 VSS32 AUX_V33_0 AUX_POR_N AUX_HMR_N<br />
14 DM_D6 DM_D7 DM_VIO_2 DM_A10 DM_A2 VSS30 AUX_V33_2 AUX_STANDBY_N<br />
15 DM_DQS0_DH DM_DQS0_DL DM_VIO_7 DM_WE_N DM_CS1_N VSS29 NA_RY_3 NA_LCK<br />
16 DM_D16 DM_D17 DM_VCC_2 DM_DQM0 DM_A13 NA_VIO_2 NA_IO15 NA_IO7<br />
17 DM_D19 DM_D18 DM_VCC_1 DM_RAS_N DM_CAS_N VSS28 NA_IO14 NA_IO6<br />
18 DM_D22 DM_D20 DM_VIO_1 DM_BA1 DM_BA0 VSS27 NA_IO13 NA_IO5<br />
19 DM_D23 DM_D21 DM_VIO_0 DM_A1 DM_A0 VSS26 NA_IO12 NA_IO4<br />
20 DM_DQS2_DH DM_DQS2_DL DM_VCC_0 DM_DQM2 DM_A3 VSS25 NA_IO11 NA_IO3<br />
21 VSS20 VSS21 VSS22 VSS23 VSS24 NA_VIO_1 NA_IO10 NA_IO2<br />
22 SM_D23 SM_D31 SM_V33_2 SM_A30 SM_A31 VSS19 NA_IO9 NA_IO1<br />
23 SM_D22 SM_D30 SM_V33_1 SM_A28 SM_A29 VSS18 NA_IO8 NA_IO0<br />
24 SM_D21 SM_D29 SM_V33_0 SM_A26 SM_A27 VSS17 DNU12 NA_PRE<br />
25 SM_D20 SM_D28 SM_VIO_8 SM_A24 SM_A25 VSS16 NA_RY_0 NA_RE_N<br />
26 SM_D19 SM_D27 SM_VIO_7 SM_A22 SM_A23 NA_VIO_0 NA_CS3_N NA_VIO<br />
27 SM_D18 SM_D26 SM_VIO_6 SM_A20 SM_A21 NA_V33_0 NA_CS2_N NA_CS1_N<br />
28 SM_D17 SM_D25 SM_VIO_5 SM_A18 SM_A19 NA_V18_0 NA_CLE NA_ALE<br />
29 SM_D16 SM_D24 SM_CLK3 SM_A16 SM_A17 VSS15 NA_WE_N NA_WP_N<br />
30 DNU16 VSS12 SM_CLK2 VSS13 SM_BE2 VSS14 NA_RY_1 NA_RY_2<br />
31 DNU17 VSS9 SM_CLK1 VSS10 SM_BE3 SM_OE_N VSS11 DNU4<br />
32 SM_D7 SM_D15 SM_CLK0 SM_A14 SM_A15 SM_WE_N VSS8 DNU3<br />
33 SM_D6 SM_D14 SM_VIO_4 SM_A12 SM_A13 SM_LBA_N VSS7 SM_WP_N<br />
34 SM_D5 SM_D13 SM_VIO_3 SM_A10 SM_A11 SM_BUSY_N_0 VSS6 SM_RESET_N<br />
35 SM_D4 SM_D12 SM_VIO_2 SM_A8 SM_A9 SM_BWAIT_N VSS5 SM_PD<br />
36 SM_D3 SM_D11 SM_VIO_1 SM_A6 SM_A7 VSS4 SM_BUSY_N_2 SM_BUSY_N_3<br />
37 SM_D2 SM_D10 SM_VIO_0 SM_A4 SM_A5 VSS3 SM_IRQ_N SM_CS3_N<br />
38 SM_D1 SM_D9 SM_V18_2 SM_A2 SM_A3 VSS2 SM_CRE SM_CS2_N<br />
39 SM_D0 SM_D8 SM_V18_1 SM_A0 SM_A1 VSS1 SM_DMARQ_N SM_CS1_N<br />
40 DNU14 DNU15 SM_V18_0 SM_BE0 SM_BE1 VSS0 SM_BUSY_N_1 SM_CS0_N<br />
Table 5 on page 6 lists and briefly describes all (and only) the signals that are routed to<br />
and from the memory devices installed on the <strong>PISMO</strong>2-00001 with reference to the<br />
corresponding bottom connector ball.<br />
PDF: 09005aef827fda9b/Source: 09005aef827fda71 <strong>Micron</strong> Technology, Inc., reserves the right to change products or specifications without notice.<br />
<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 5 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.
Advance<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Pin Assignments and Descriptions<br />
Table 5: <strong>PISMO</strong>2-00001 Ball Descriptions (Referenced to the Bottom Connector)<br />
Ball No. (Bottom) Symbol Type Description<br />
DRAM Section<br />
D12, E12 DM_CLK0_DH Input System clock: DM_CLK_DH and DM_CLK_DL are differential<br />
DM_CLK0_DL<br />
clock inputs. All address and control input signals are sampled<br />
on the positive edge of DM_CLK_DH and the negative edge of<br />
DM_CLK_DL. Output (read) data is referenced to both edges of<br />
DM_CLK. Internal clock signals are derived from DM_CLK_DH/<br />
DM_CLK_DL. SDRAM and Mobile SDRAM only use<br />
DM_CLK_DH. Both DM_CLK_DH and DM_CLK_DL apply to<br />
DDR, Mobile DDR, and DDR2 SDRAM.<br />
E5 DM_CKE0 Input Clock enable: DM_CKE HIGH activates, and DM_CKE LOW<br />
deactivates, internal clock signals and device input buffers and<br />
output drivers. Taking DM_CKE LOW provides PRECHARGE,<br />
POWER-DOWN, and SELF REFRESH operation (all banks idle) or<br />
active power-down (row active in any bank). DM_CKE is<br />
synchronous for power-down entry and exit and for self<br />
refresh entry. DM_CKE is asynchronous for self refresh exit.<br />
E15 DM_CS0_N Input Chip select: DM_CS_N enables (registered LOW) and disables<br />
(registered HIGH) the command decoder. All commands are<br />
masked when DM_CS_N is registered HIGH. DM_CS_N provides<br />
external bank selection on multibank systems. DM_CS_N is<br />
considered part of the command code.<br />
D17 DM_RAS_N Input Row address strobe: Latches row addresses on the positive<br />
edge of the DM_CLK with DM_RAS_N LOW. Enables row access<br />
and precharge.<br />
E17 DM_CAS_N Input Column address strobe: Latches column addresses on the<br />
positive edge of the DM_CLK with DM_CAS_N LOW. Enables<br />
column access.<br />
D15 DM_WE_N Input Write enable: Enables WRITE operation and row precharge.<br />
Latches data in starting from DM_CAS_N, DM_WE_N active.<br />
D16, D8, D20, E6 DM_DQM0 to<br />
DM_DQM3<br />
E18, D18 DM_BA0,<br />
DM_BA1<br />
E19, D19, E14, E20, E2, E8,<br />
E3, D3, D7, E4, D14, D4, E7<br />
B11, A11, B12, A12, B13,<br />
A13, A14, B14, A7, B7, A8,<br />
B8, A9, B9, B10, A10, A16,<br />
B16, B17, A17, B18, B19,<br />
A18, A19, B2, B3, A2, A3,<br />
B4, A4, A5, B5<br />
DM_A0 to<br />
DM_A12<br />
DM_D0 to<br />
DM_D31<br />
A15, A6, A20, A1 DM_DQS0_DH<br />
to<br />
DM_DQS3_DH<br />
C19, C18, C14, C8, C12,<br />
C10, C9, C15, C11, C7<br />
DM_VIO_0 to<br />
DM_VIO_9<br />
Input <strong>Data</strong> input/output mask: Makes data output High-Z, t SHZ after<br />
the clock and masks the output. Blocks data input when<br />
DM_DQM active.<br />
Input Bank select address: DM_BA0 and DM_BA1 define to which<br />
bank an ACTIVE, READ, WRITE, or PRECHARGE command is<br />
applied. Bank address also determines whether the mode<br />
register or extended mode register is to be accessed during an<br />
MRS or EMRS cycle.<br />
Input Address: Row/column addresses are multiplexed on the same<br />
pins.<br />
I/O <strong>Data</strong> input/output: <strong>Data</strong> inputs/outputs are multiplexed on the<br />
same pins.<br />
I/O <strong>Data</strong> strobes: Output with read data, input with write data.<br />
Edge-aligned with read data, center-aligned with write data.<br />
Only applicable to DDR and DDR2 SDRAM.<br />
Supply <strong>Data</strong> output power: Isolates the output buffer power supply to<br />
provide improved noise immunity.<br />
PDF: 09005aef827fda9b/Source: 09005aef827fda71 <strong>Micron</strong> Technology, Inc., reserves the right to change products or specifications without notice.<br />
<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 6 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.
Advance<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Pin Assignments and Descriptions<br />
Table 5: <strong>PISMO</strong>2-00001 Ball Descriptions (Referenced to the Bottom Connector) (continued)<br />
Ball No. (Bottom) Symbol Type Description<br />
C20, C17, C16, C13 DM_VCC_0 to<br />
DM_VCC_3<br />
Supply Power supply: Power for the core logic.<br />
E16 DM_A13 Input Upgrade address input for future devices (selected via R5).<br />
NAND Section<br />
H28 NA_ALE Input Address latch enable: Controls the address registers. When<br />
active (HIGH), an address is latched from NA_IO0–NA_IO7 into<br />
the address registers with the rising edge of the write enable<br />
signal. When addresses are not being loaded, NA_ALE is driven<br />
LOW.<br />
H27 NA_CS0_N Input Chip enable (active-LOW signal): These device select control<br />
signals are active (LOW) and are ignored during any of the<br />
busy states. The NAND devices go into a low-power standby<br />
mode when driven HIGH during ready states. The host should<br />
implement as many chip-select signals as supported by the<br />
host CPU, starting at NA_CS0_N and pull up all remaining<br />
NA_CSN_N signals to NA_VIO.<br />
G28 NA_CLE Input Command latch enable: Controls the command register. When<br />
active (HIGH), commands are latched from NA_IO0–NA_IO7<br />
into the register with the rising edge of the write enable<br />
signal. When a command is not being loaded, this signal is<br />
driven LOW.<br />
H25 NA_RE_N Input Read enable (active-LOW signal): Initiates the transfer of<br />
information from the device to the host and increments the<br />
internal column counter by one. Information is valid when it is<br />
active (LOW) and is driven HIGH when information is not being<br />
transferred.<br />
G29 NA_WE_N Input Write enable (active-LOW signal): Initiates the transfer of<br />
information from the host to the device. Command, address,<br />
and data are latched with the rising edge, and WE is driven<br />
HIGH when information is not being transferred.<br />
H29 NA_WP_N Input Write protect (active-LOW signal): Provides a hardware<br />
method for protecting NAND memory contents. LOW means<br />
write-protected.<br />
H23, H22, H21, H20, H19,<br />
H18, H17, H16, G23, G22,<br />
G21, G20, G19, G18, G17,<br />
G16<br />
NA_IO0 to<br />
NA_IO15<br />
I/O <strong>Data</strong> inputs and outputs: These bidirectional signals are used<br />
to input command and address. They can input data during<br />
WRITE operation and output data during READ operation. All<br />
signals are inputs during non-READ operations.<br />
H15 NA_LCK Input When NA_LCK is HIGH during power-up, the BLOCK LOCK<br />
function is enabled. To disable the BLOCK LOCK, connect<br />
NA_LCK to VSS during power-up, or leave it unconnected<br />
(internal pull-down).<br />
G25 NA_RY Output Ready/Busy: Indicates the operating condition of the device. It<br />
is busy, active (LOW) during PROGRAM, ERASE, and READ<br />
operation and returns to ready, active (HIGH) after completing<br />
the operation. This signal is an open-drain output buffer on<br />
memory modules. The host must implement a pull-up resistor<br />
to NA_VIO. The value of this pull-up resistor determines the<br />
rise time of the NA_RY signal and should be calculated as<br />
specified in the NAND Flash memory data sheets.<br />
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<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 7 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.
Advance<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Pin Assignments and Descriptions<br />
Table 5: <strong>PISMO</strong>2-00001 Ball Descriptions (Referenced to the Bottom Connector) (continued)<br />
Ball No. (Bottom) Symbol Type Description<br />
F28<br />
EEPROM Section<br />
NA_V18_0 Supply 1.8V power supply: The host implementation supplies 1.8V DC<br />
on this pin, independent of the I/O voltage. This power supply<br />
is used as memory core voltage.<br />
H9, H8, H7 AUX_SA0 to<br />
AUX_SA2<br />
Input Used by the EEPROM for multiple device operation. The levels<br />
on these inputs are compared with the corresponding bits in<br />
the slave address. The chip is selected if the comparison is true.<br />
Up to eight devices may be connected to the same bus by<br />
using different chip-select bit combinations.<br />
G8 AUX_SCL Input Synchronizes data transfer to and from the device.<br />
G9 AUX_SDA I/O This bidirectional pin transfers addresses and data into and<br />
data out of the device. It is an open-drain terminal; therefore,<br />
the SDA bus requires a pull-up resistor to VCC (typical 10kΩ for<br />
100 kHz, 2kΩ for 400 kHz). For normal data transfer, SDA is<br />
allowed to change only during SCL LOW. Changes during SCL<br />
HIGH are reserved for indicating start and stop conditions.<br />
F13, F11, G14 AUX_V33_0 to<br />
AUX_V33_2<br />
Supply +1.8V to 5.5V power supply.<br />
Ground Pins<br />
F40, F39, F38, F37, F36,<br />
G35, G34, G33, G32, B31,<br />
D31, G31, B30, D30, F30,<br />
F29, F25, F24, F23, F22,<br />
A21, B21, C21, D21, E21,<br />
F20, F19, F18, F17, F15,<br />
F14, D13, E13, F12, D11,<br />
E11, F10, D9, E9, F9, F8, F7,<br />
F6, F5, F4, F2, E1<br />
VSS0 to VSS46 Supply Ground.<br />
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<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 8 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.
Functional Block Diagram<br />
Advance<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Functional Block Diagram<br />
Figure 2 illustrates the connections among the host system, the <strong>PISMO</strong>2-00001 DRAM<br />
and NAND interface, and the <strong>Micron</strong> DRAM and NAND devices. All NAND and DRAM<br />
interface signals are also connected straight through from bottom to top on the <strong>PISMO</strong>2<br />
connector except NA_CS[3:0] and DM_CS[1:0], which are connected as shown in“Chip-<br />
Select Routing” on page 10. The STATIC and FAST SERIAL interface signals are only<br />
“routed through” (no devices are connected).<br />
For clarity, in Figure 2, the NAND and DRAM interface signal connections between the<br />
top and bottom connectors have been omitted.<br />
Figure 2: <strong>PISMO</strong>2-00001 Functional Block Diagram<br />
CPU <strong>PISMO</strong>2-00001<br />
DRAM Controller<br />
DRAM<br />
Interface<br />
NAND Controller<br />
NAND<br />
Interface<br />
Auxiliary Signals<br />
Controller<br />
Auxiliary<br />
Interface<br />
DRAM<br />
Interface<br />
DM_ BUS<br />
NAND<br />
Interface<br />
NA_ BUS<br />
Auxiliary<br />
Signals<br />
Interface<br />
AUX_ BUS<br />
Mobile DDR<br />
SDRAM<br />
MT46H16M32LF<br />
1.8V NAND Flash<br />
MT29F1G16AB<br />
Microchip<br />
24AA64-I/ST I2C<br />
Serial EEPROM<br />
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<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 9 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.
Chip-Select Routing<br />
Design for Testability<br />
Advance<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Chip-Select Routing<br />
The <strong>PISMO</strong>2 specification enables the DRAM interface to support up to two memory<br />
banks, adopting the same signaling, whereas up to four memory banks can be<br />
connected to the NAND interface. The <strong>Micron</strong> <strong>PISMO</strong>2-00001 memory module uses one<br />
DRAM and one NAND bank. Table 6 clarifies the chip-select routing scheme adopted for<br />
this implementation. This method automatically maps host controller chip-select<br />
signals to the NAND memory banks installed within a <strong>PISMO</strong>2 memory module stack.<br />
If the number of stacked memory banks exceeds host controller support, only the first<br />
two DRAM and the first four NAND banks (starting at the bottommost module) are used.<br />
All remaining banks are forced inactive.<br />
Table 6: <strong>PISMO</strong>2-00001 DRAM and NAND Interface Chip-Select Routing<br />
Memory Interface<br />
DRAM interface:<br />
– 1 device installed<br />
– 1 CS_N used<br />
NAND interface:<br />
– 1 device installed<br />
– 1 CS_N used<br />
Chip-Select Connections<br />
Bottom Side Top Side<br />
DM_CS0_N<br />
DM_CS1_N<br />
DM_VIO<br />
NA_CS0_N<br />
NA_CS1_N<br />
NA_CS2_N<br />
NA_CS3_N<br />
NA_VIO<br />
To Mobile DDR<br />
DM_CS0_N<br />
DM_CS1_N<br />
To NAND<br />
NA_CS0_N<br />
NA_CS1_N<br />
NA_CS2_N<br />
NA_CS3_N<br />
To the<br />
NAND<br />
device<br />
Top connector<br />
To the<br />
DRAM<br />
device<br />
Chip-Select Routing<br />
DM_CS0_N<br />
DM_CS0_N<br />
Bottom connector<br />
Top connector<br />
DM_CS1_N<br />
DM_CS1_N<br />
DM_VIO<br />
NA_CS0# NA_CS1# NA_CS2# NA_CS3#<br />
NA_CS0# NA_CS1# NA_CS2# NA_CS3#<br />
Bottom connector<br />
NA_VIO<br />
Although the <strong>PISMO</strong>2 specification prohibits routing used chip selects back to the top<br />
connector, the <strong>PISMO</strong>2-00001 board features a configuration option that enables the<br />
user to scope CS# with the <strong>Micron</strong> <strong>PISMO</strong>2-P6960 logic state analyzer adapter (LSA) tile.<br />
Every chip-select signal that is connected to an installed memory chip can be routed<br />
back to the higher CS# position available for the bank on the top connector, just by<br />
moving a configuration resistor. (For example, the NA_CS0_N ball of the bottom<br />
connector is routed back to NA_CS3_N position of the top connector by R10.) Configuration<br />
options are listed in Table 7 on page 11. See the <strong>PISMO</strong>2-P6960 data sheet for more<br />
information.<br />
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<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 10 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.
Table 7: <strong>PISMO</strong>2-00001 CS# Feedback Configurations<br />
Serial Presence-Detect<br />
Advance<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Serial Presence-Detect<br />
Configuration<br />
Resistor Signal<br />
Top Connector<br />
Position Notes<br />
R11 DM_VIO D1 If R11 is installed, the board is compliant<br />
with the <strong>PISMO</strong>2 specification.<br />
R12 DM_CS0_N D1 If R12 is installed, the CS is routed back<br />
to the top connector.<br />
R9 NA_POWER H26 If R9 is installed, the board is compliant<br />
with the <strong>PISMO</strong>2 specification.<br />
R10 NA_CS0_N H26 If R10 is installed, the CS is routed back<br />
to the top connector.<br />
The <strong>Micron</strong> <strong>PISMO</strong>2-00001 module features serial presence-detect (SPD). The SPD<br />
function is implemented using a 64Kb serial EEPROM compliant with the <strong>PISMO</strong>2 specification.<br />
This nonvolatile storage device contains 8KB. System READ/WRITE operations<br />
between the master (host system) and the slave EEPROM device occur via a standard I 2 C<br />
bus using the <strong>PISMO</strong>2-00001 AUX_SCL (clock) and AUX_SDA (data) signals, together<br />
with AUX_SA[2:0], which provide eight unique <strong>PISMO</strong>2/EEPROM addresses. The<br />
memory write protect pin (WP#) is tied to ground on the module, permanently disabling<br />
hardware write protect. All these signals are in the AUX_V33 I/O voltage domain, which<br />
is fixed at 3.3V.<br />
The configuration EEPROM contains information about the memory module itself, such<br />
as vendor, complete part number, and serial number. It also contains information about<br />
the memory devices installed on the module. The operating system or the application<br />
running on the host system processor can use the data from the configuration EEPROM<br />
to perform the following tasks:<br />
Initialize the memory space<br />
Identify the <strong>PISMO</strong>2 memory card vendors, model, and revision<br />
Validate system configurations<br />
Query product names of installed memory devices in terms of speed grade, data bus<br />
width, density of memory chip, and addressing scheme<br />
Query key memory device parameters, such as timing and voltage options<br />
Optimize host controller settings according to detected memory parameters<br />
Select optimized programming algorithms<br />
Select software drivers based on identified memory modules<br />
Obtain additional vendor-specific information<br />
The <strong>Micron</strong> <strong>PISMO</strong>2-00001 board complies with the <strong>PISMO</strong> 2.0 specification, which<br />
defines a scheme for automatically assigning two-wire addresses to two-wire devices on<br />
the memory module. As shown in Figure 3 on page 12, the <strong>PISMO</strong>2-00001 module automatically<br />
assigns two-wire device addresses by module location in the stack. No additional<br />
logic is required for this function.<br />
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<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 11 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.
Advance<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Serial EEPROM <strong>Data</strong> Structure<br />
Figure 3: <strong>PISMO</strong>2-00001 Two-Wire Address Generation Scheme<br />
Table 8: EEPROM Addresses<br />
Serial EEPROM <strong>Data</strong> Structure<br />
Host Memory <strong>Module</strong> A Memory <strong>Module</strong> B<br />
The connections shown in Figure 3 result in the two-wire device address assignments<br />
shown in Table 8.<br />
Memory <strong>Module</strong> Stack Location EEPROM Address (Hexadecimal)<br />
1 st memory module (bottommost) 0xA0 (WRITE), 0xA1 (READ)<br />
2nd memory module 0xA2 (WRITE), 0xA3 (READ)<br />
3rd memory module 0xA6 (WRITE), 0xA7 (READ)<br />
4 th memory module (topmost) 0xAE (WRITE), 0xAF (READ)<br />
TBD<br />
AUX_V33 AUX_V33<br />
AUX_SCL<br />
AUX_SDA<br />
AUX_SA0<br />
AUX_SA1<br />
AUX_SA2<br />
Bottom Top Bottom<br />
AUX_SCL<br />
AUX_SDA<br />
AUX_SA0<br />
AUX_SA1<br />
AUX_SA2<br />
Two-wire address(es):<br />
AUX_SCL<br />
AUX_SDA<br />
AUX_SA0<br />
AUX_SA1<br />
AUX_SA2<br />
On-board<br />
two-wire device(s)<br />
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<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 12 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
SCL<br />
SDA<br />
A0<br />
A1<br />
A2<br />
A6 A5 A4 A3 0 0 0 R/W<br />
AUX_SCL<br />
AUX_SDA<br />
AUX_SA0<br />
AUX_SA1<br />
AUX_SA2<br />
AUX_V33<br />
Two-wire address(es):<br />
2 nd module: xxxx001x<br />
3 rd module: xxxx011x<br />
4 th module: xxxx111x
Mechanical Specifications<br />
Connector Description<br />
Figure 4: <strong>PISMO</strong>2 Connectors<br />
For clarity, some contacts are not shown<br />
Advance<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Mechanical Specifications<br />
The <strong>PISMO</strong>2-00001 board/host system connection is provided by a Samtec SE (singleended)<br />
array connector system designed for high-speed/high-density applications<br />
where high pin-count flexibility, space savings, and routability are critical. The Edge<br />
Rate blade and beam interface was designed to provide maximum signal integrity at<br />
50Ω on a popular 0.050in x 0.050in grid. The SE array connector has been tested up to<br />
4 GHz (single-ended) and 9 GHz (differentially) at the 7mm mated height.<br />
Connector Specifications<br />
Male P/N: SEAM-40-02.0-SM-8-2-A-K<br />
Female P/N: SEAF-40-05.0-SM-8-2-A-K<br />
Black liquid crystal polymer<br />
320 positions (8 x 40 grid)<br />
1.27mm (0.050in) pitch<br />
7mm mated height<br />
30 microinch Au duplex contact plating<br />
Copper alloy contact material<br />
–55°C to +125°C operating temperature range<br />
Pb-free solder<br />
Memory <strong>Module</strong><br />
SEAF (female) connector SEAM (male) connector<br />
Figure 5 on page 14 illustrates the mechanical construction of the <strong>PISMO</strong>2-00001<br />
memory module. The A1 mark denotes the location of the A1 pin on both connectors.<br />
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<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 13 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.
Figure 5: <strong>PISMO</strong>2-00001 Memory <strong>Module</strong> Dimensions<br />
Advance<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Mechanical Specifications<br />
Top view Bottom view<br />
Side views<br />
11.2<br />
1.5<br />
26.0<br />
60.0<br />
30.0<br />
26.0<br />
A1<br />
The bottom side is used as the primary assembly side. The top side carries module documentation,<br />
such as the label.<br />
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<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 14 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
39.0<br />
7.0<br />
50.0<br />
SEAF (female/top)<br />
SEAM (male/bottom)<br />
A1
Vertical Space<br />
Advance<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Mechanical Specifications<br />
The connectors chosen for <strong>PISMO</strong>2 use a 7mm stacked height. This means that a 7mm<br />
vertical space exists between the host system and the first memory module PCBs and<br />
also between the PCBs of the two neighboring memory modules. The <strong>PISMO</strong>2 specification<br />
defines requirements for vertical space assignments on <strong>PISMO</strong>2 memory modules<br />
and host controllers. Because <strong>Micron</strong>’s <strong>PISMO</strong>2-00001 complies with this requirement, it<br />
can be plugged into any <strong>PISMO</strong>2 host controller or on top of any other memory module.<br />
Figure 6 illustrates the <strong>PISMO</strong>2 vertical space requirements.<br />
Figure 6: <strong>PISMO</strong>2-00001 Vertical Space Requirements<br />
SEAF<br />
SEAM<br />
Top side<br />
Maximum component height: 2mm<br />
Label<br />
Ø8.0 Ø8.0<br />
Bottom (assembly side)<br />
Maximum component height: 4mm<br />
No components in keep-out areas<br />
around mounting holes<br />
Ø8.0 Ø8.0<br />
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<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 15 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
Label<br />
Assembly side
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<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 16 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
Schematics<br />
Figure 7: Bottom Connector Schematic<br />
5<br />
5<br />
4<br />
4<br />
3<br />
SM_A[0..31] J2B<br />
SM_D[0..31]<br />
SM_A[0..31] SEAM-40-02.0-S-08-2-A-K SM_D[0..31]<br />
D<br />
C<br />
B<br />
DM_DQM[0..3]<br />
DM_DQM[0..3]<br />
DM_D[0..31]<br />
DM_D[0..31]<br />
DM_A[0..15]<br />
DM_A[0..15]<br />
DM_A0<br />
DM_D0<br />
DM_A1<br />
DM_D1<br />
DM_A2<br />
DM_D2<br />
DM_A3<br />
DM_D3<br />
DM_A4<br />
DM_D4<br />
DM_A5<br />
DM_D5<br />
DM_A6<br />
DM_D6<br />
DM_A7<br />
DM_D7<br />
DM_A8<br />
DM_D8<br />
DM_A9<br />
DM_D9<br />
DM_A10<br />
DM_D10<br />
DM_A11<br />
DM_D11<br />
DM_A12<br />
DM_D12<br />
DM_A13<br />
DM_D13<br />
DM_A14<br />
DM_D14<br />
DM_A15<br />
DM_D15<br />
DM_D16<br />
DM_BA0<br />
DM_D17<br />
DM_BA0<br />
DM_BA1<br />
DM_D18<br />
DM_BA1<br />
DM_BA2<br />
DM_D19<br />
DM_BA2<br />
DM_D20<br />
DM_DQM0<br />
DM_D21<br />
DM_DQM1<br />
DM_D22<br />
DM_DQM2<br />
DM_D23<br />
DM_DQM3<br />
DM_D24<br />
DM_D25<br />
DM_CLK0_DL<br />
DM_D26<br />
DM_CLK0_DL<br />
DM_CLK0_DH<br />
DM_D27<br />
DM_CLK0_DH<br />
DM_CKE0<br />
DM_D28<br />
DM_CKE0<br />
DM_D29<br />
DM_CLK1_DL<br />
DM_D30<br />
DM_CLK1_DL<br />
DM_CLK1_DH<br />
DM_D31<br />
DM_CLK1_DH<br />
DM_CKE1<br />
DM_CKE1<br />
DM_DQS0_DL<br />
DM_RAS_N<br />
DM_DQS0_DH<br />
DM_RAS_N<br />
DM_CAS_N<br />
DM_CAS_N<br />
DM_WE_N<br />
DM_DQS1_DL<br />
DM_WE_N<br />
DM_DQS1_DH<br />
DM_CS0_N<br />
DM_CS0_N<br />
DM_CS1_N_BOT<br />
DM_DQS2_DL<br />
DM_CS1_N_BOT<br />
DM_DQS2_DH<br />
DM_RESET_N<br />
DM_RESET_N<br />
DM_DQS3_DL<br />
DM_ODT0<br />
DM_DQS3_DH<br />
DM_ODT0<br />
DM_ODT1<br />
DM_ODT1<br />
NA_IO[0..15]<br />
NA_IO[0..15]<br />
AUX_3V3<br />
SM_VIO<br />
SM_3V3<br />
SM_1V8<br />
DM_POWER<br />
DM_DQS0_DL<br />
DM_DQS0_DH<br />
DM_DQS1_DL<br />
DM_DQS1_DH<br />
FS_VIO<br />
DM_DQS2_DL<br />
DM_DQS2_DHVref<br />
FS_3V3<br />
DM_DQS3_DL FS_1V8<br />
DM_DQS3_DH<br />
NA_1V8<br />
NA_3V3<br />
STATIC MEMORY INTERFACE<br />
SM_A0<br />
D39<br />
SM_A1<br />
SM_A0<br />
SM_D0<br />
E39<br />
SM_A2<br />
SM_A1<br />
D38<br />
SM_A3<br />
SM_A2<br />
E38<br />
SM_A4<br />
SM_A3<br />
D37<br />
SM_A5<br />
SM_A4<br />
E37<br />
SM_A6<br />
SM_A5<br />
D36<br />
SM_A7<br />
SM_A6<br />
E36<br />
SM_A8<br />
SM_A7<br />
D35<br />
SM_A9<br />
SM_A8<br />
E35<br />
SM_A10<br />
SM_A9<br />
D34<br />
SM_A11<br />
SM_A10<br />
E34<br />
SM_A12<br />
SM_A11<br />
D33<br />
SM_A13<br />
SM_A12<br />
E33<br />
SM_A14<br />
SM_A13<br />
D32<br />
SM_A15<br />
SM_A14<br />
E32<br />
SM_A16<br />
SM_A15<br />
D29<br />
SM_A17<br />
SM_A16<br />
E29<br />
SM_A18<br />
SM_A17<br />
D28<br />
SM_A19<br />
SM_A18<br />
E28<br />
SM_A20<br />
SM_A19<br />
D27<br />
SM_A21<br />
SM_A20<br />
E27<br />
SM_A22<br />
SM_A21<br />
D26<br />
SM_A23<br />
SM_A22<br />
E26<br />
SM_A24<br />
SM_A23<br />
D25<br />
SM_A25<br />
SM_A24<br />
E25<br />
SM_A26<br />
SM_A25<br />
D24<br />
SM_A27<br />
SM_A26<br />
E24<br />
SM_A28<br />
SM_A27<br />
D23<br />
SM_A29<br />
SM_A28<br />
E23<br />
SM_A30<br />
SM_A29<br />
D22<br />
SM_A31<br />
SM_A30<br />
E22<br />
SM_A31<br />
SM_BE0<br />
SM_BE0<br />
SM_BE1<br />
SM_BE1<br />
SM_BE2<br />
SM_BE2<br />
SM_BE3<br />
SM_BE3<br />
SM_CLK0<br />
SM_CLK0<br />
SM_CLK1<br />
SM_CLK1<br />
SM_CLK2<br />
SM_CLK2<br />
SM_CLK3<br />
SM_CLK3<br />
SM_CS0_N<br />
SM_CS0_N<br />
SM_CS1_N<br />
SM_CS1_N<br />
SM_CS2_N<br />
SM_CS2_N<br />
SM_CS3_N<br />
SM_CS3_N<br />
SM_WE_N<br />
SM_WE_N<br />
SM_OE_N<br />
SM_OE_N<br />
SM_LBA_N<br />
SM_LBA_N<br />
SM_WP_N<br />
SM_WP_N<br />
SM_RESET_N<br />
SM_RESET_N<br />
SM_CRE_N<br />
SM_CRE_N<br />
SM_PD_N<br />
SM_PD_N<br />
FS_SI<br />
FS_SI<br />
FS_SCK<br />
FS_SCK<br />
FS_WP_N<br />
FS_WP_N<br />
FS_RESET<br />
FS_RESET<br />
FS_CS0_N<br />
FS_CS0_N<br />
FS_CS1_N<br />
FS_CS1_N<br />
FS_CS2_N<br />
FS_CS2_N<br />
FS_CS3_N<br />
FS_CS3_N<br />
SM_D0<br />
SM_D1<br />
SM_D2<br />
SM_D3<br />
SM_D4<br />
SM_D5<br />
SM_D6<br />
SM_D7<br />
SM_D8<br />
SM_D9<br />
SM_D10<br />
SM_D11<br />
SM_D12<br />
SM_D13<br />
SM_D14<br />
SM_D15<br />
SM_D16<br />
SM_D17<br />
SM_D18<br />
SM_D19<br />
SM_D20<br />
SM_D21<br />
SM_D22<br />
SM_D23<br />
SM_D24<br />
SM_D25<br />
SM_D26<br />
SM_D27<br />
SM_D28<br />
SM_D29<br />
SM_D30<br />
SM_D31<br />
SM_BUSY_N_0<br />
SM_BUSY_N_1 SM_BUSY_N_0<br />
SM_BUSY_N_2 SM_BUSY_N_1<br />
SM_BUSY_N_3 SM_BUSY_N_2<br />
SM_BUSY_N_3<br />
SM_IRQ_N<br />
SM_IRQ_N<br />
SM_BWAIT_N<br />
SM_BWAIT_N<br />
SM_DMARQ_N<br />
SM_DMARQ_N<br />
FS_SO<br />
FS_HOLD_N FS_SO<br />
FS_HOLD_N<br />
D<br />
C<br />
B<br />
A<br />
NA_CLE<br />
NA_ALE<br />
NA_RE_N<br />
NA_WE_N<br />
NA_PRE<br />
NA_WP_N<br />
NA_CS0_N<br />
NA_CS1_N_BOT<br />
NA_CS2_N_BOT<br />
NA_CS3_N_BOT<br />
NA_CLE<br />
NA_ALE<br />
NA_RE_N<br />
NA_WE_N<br />
NA_PRE<br />
NA_WP_N<br />
NA_CS0_N<br />
NA_CS1_N_BOT<br />
NA_CS2_N_BOT<br />
NA_CS3_N_BOT<br />
NA_IO0<br />
NA_IO1<br />
NA_IO2<br />
NA_IO3<br />
NA_IO4<br />
NA_IO5<br />
NA_IO6<br />
NA_IO7<br />
NA_IO8<br />
NA_IO9<br />
NA_IO10<br />
NA_IO11<br />
NA_IO12<br />
NA_IO13<br />
NA_IO14<br />
NA_IO15<br />
AUX_SDA<br />
AUX_SCL<br />
AUX_SA0_BOT<br />
AUX_SA1_BOT<br />
AUX_SA2_BOT<br />
AUX_TDI<br />
AUX_TCK<br />
AUX_TMS<br />
AUX_STANDBY_N<br />
AUX_POR_N<br />
AUX_HMR_N<br />
AUX_SDA<br />
AUX_SCL<br />
AUX_SA0_BOT<br />
AUX_SA1_BOT<br />
AUX_SA2_BOT<br />
AUX_TDI<br />
AUX_TCK<br />
AUX_TMS<br />
AUX_STANDBY_N<br />
AUX_POR_N<br />
AUX_HMR_N<br />
AUX_TDO<br />
AUX_TDO<br />
Title<br />
BOTTOM CONNECTOR<br />
D o c u m e n t N u m b e r<br />
<strong>Micron</strong> Technology<br />
Systems Engineering<br />
via A. Pacinotti, 7<br />
67051, Avezzano<br />
ITALY<br />
R e v i s i o n<br />
Size<br />
A<br />
NA_LCK<br />
NA_LCK<br />
NA_RY0<br />
NA_RY1<br />
NA_RY2<br />
NA_RY3<br />
NA_RY0<br />
NA_RY1<br />
NA_RY2<br />
NA_RY3<br />
M I C R O N - P I S M O 2 - 0 0 0 0 1<br />
4 . 0<br />
CONFIDENTIAL AND PROPRIETARY INFORMATION<br />
The information contained herein is proprietary of <strong>Micron</strong> Technology. Any reproduction, in whole or in part,<br />
disclosure, or use of this drawing is expressly prohibited except as specified in writing by <strong>Micron</strong> Technology.<br />
A-3<br />
A39<br />
SM_D1 A38<br />
SM_D2 A37<br />
SM_D3 A36<br />
SM_D4 A35<br />
SM_D5 A34<br />
SM_D6 A33<br />
SM_D7 A32<br />
SM_D8 B39<br />
SM_D9 B38<br />
SM_D10 B37<br />
SM_D11 B36<br />
SM_D12 B35<br />
SM_D13 B34<br />
SM_D14 B33<br />
SM_D15 B32<br />
SM_D16 A29<br />
SM_D17 A28<br />
SM_D18 A27<br />
SM_D19 A26<br />
SM_D20 A25<br />
SM_D21 A24<br />
SM_D22 A23<br />
SM_D23 A22<br />
SM_D24 B29<br />
SM_D25 B28<br />
SM_D26 B27<br />
SM_D27 B26<br />
SM_D28 B25<br />
SM_D29 B24<br />
SM_D30 B23<br />
SM_D31 B22<br />
D40<br />
SM_BE0<br />
E40<br />
SM_BE1<br />
E30<br />
SM_BE2<br />
E31<br />
SM_BE3<br />
C32<br />
SM_CLK0<br />
C31<br />
SM_CLK1<br />
C30<br />
SM_CLK2<br />
C29<br />
SM_CLK3<br />
H40<br />
SM_CS0_N<br />
H39<br />
SM_CS1_N<br />
H38<br />
SM_CS2_N<br />
H37<br />
SM_CS3_N<br />
F32<br />
SM_WE_N<br />
F31<br />
SM_OE_N<br />
SM_IRQ_N<br />
F33<br />
SM_LBA_N<br />
H33<br />
SM_WP_N<br />
H34<br />
SM_RESET_N<br />
G38<br />
SM_CRE_N<br />
H35<br />
SM_PD_N<br />
G37<br />
SM_BWAIT_N F35<br />
SM_BUSY_N_0<br />
SM_DMARQ_N<br />
F34<br />
G39<br />
SM_BUSY_N_1 G40<br />
SM_BUSY_N_2 G36<br />
SM_BUSY_N_3 H36<br />
J2C<br />
SEAM-40-02.0-S-08-2-A-K<br />
FAST SERIAL<br />
MEMORY<br />
INTERFACE<br />
FS_SO G1<br />
FS_HOLD_N H2<br />
J2F<br />
SEAM-40-02.0-S-08-2-A-K<br />
POWER<br />
F13<br />
AUX_V33_0<br />
F11<br />
AUX<br />
AUX_V33_1<br />
G14<br />
AUX_V33_2<br />
C37<br />
SM_VIO_0<br />
C36<br />
SM_VIO_1<br />
C35<br />
STATIC MEMORY<br />
SM_VIO_2<br />
VSS1<br />
C34<br />
SM_VIO_3<br />
VSS2<br />
C33<br />
SM_VIO_4<br />
VSS3<br />
C28<br />
SM_VIO_5<br />
VSS4<br />
C27<br />
SM_VIO_6<br />
VSS5<br />
C26<br />
SM_VIO_7<br />
C25<br />
SM_VIO_8<br />
C24<br />
SM_V33_0<br />
C23<br />
SM_V33_1<br />
C22<br />
SM_V33_2<br />
C40<br />
SM_V18_0<br />
C39<br />
SM_V18_1<br />
C38<br />
SM_V18_2<br />
C19<br />
DM_VIO_0<br />
C18<br />
DM_VIO_1<br />
C14<br />
DM_VIO_2<br />
C8<br />
DM_VIO_3<br />
C12<br />
DM_VIO_4<br />
C10<br />
DM_VIO_5<br />
C9<br />
DYNAMIC<br />
DM_VIO_6<br />
C15<br />
MEMORY<br />
DM_VIO_7<br />
C11<br />
DM_VIO_8<br />
C7<br />
DM_VIO_9<br />
C20<br />
DM_VCC_0<br />
C17<br />
DM_VCC_1<br />
C16<br />
DM_VCC_2<br />
C13<br />
DM_VCC_3<br />
G5<br />
FS_VIO_0<br />
G4<br />
FAST SERIAL<br />
FS_VIO_1<br />
F3<br />
MEMORY<br />
FS_V33_0<br />
G6<br />
FS_V18_0<br />
F26<br />
NA_VIO_0<br />
F21<br />
NAND<br />
NA_VIO_1<br />
F16<br />
MEMORY<br />
NA_VIO_2<br />
F27<br />
NA_V33_0<br />
F28<br />
NA_V18_0<br />
F39<br />
F38<br />
F37<br />
F36<br />
G2<br />
FS_SI<br />
F1<br />
FS_SCK<br />
G7<br />
FS_WP_N<br />
H1<br />
FS_RESET_N<br />
H6<br />
FS_CS0_N<br />
H5<br />
FS_CS1_N<br />
H4<br />
FS_CS2_N<br />
H3<br />
FS_CS3_N<br />
G35<br />
VSS6 G34<br />
VSS7 G33<br />
VSS8 G32<br />
VSS9 B31<br />
VSS10 D31<br />
VSS11 G31<br />
VSS12 B30<br />
VSS13 D30<br />
VSS14<br />
VSS15<br />
VSS16<br />
VSS17<br />
VSS18<br />
VSS19<br />
VSS20<br />
F30<br />
F29<br />
F25<br />
F24<br />
F23<br />
F22<br />
A21<br />
VSS21 B21<br />
VSS22 C21<br />
VSS23 D21<br />
VSS24 E21<br />
VSS25<br />
VSS26<br />
VSS27<br />
VSS28<br />
VSS29<br />
VSS30<br />
VSS31<br />
F20<br />
F19<br />
F18<br />
F17<br />
F15<br />
F14<br />
D13<br />
VSS32 E13<br />
VSS33<br />
VSS34<br />
F12<br />
D11<br />
VSS35 E11<br />
VSS36<br />
VSS37<br />
F10<br />
D9<br />
VSS38 E9<br />
VSS0<br />
VSS39<br />
VSS40<br />
VSS41<br />
VSS42<br />
VSS43<br />
VSS44<br />
VSS45<br />
VSS46<br />
F40<br />
F9<br />
F8<br />
F7<br />
F6<br />
F5<br />
F4<br />
F2<br />
E1<br />
J2D<br />
SEAM-40-02.0-S-08-2-A-K<br />
NAND MEMORY<br />
INTERFACE<br />
NA_IO0 H23<br />
G28<br />
NA_CLE NA_IO1 H22<br />
NA_IO2 H21<br />
NA_IO3 H20<br />
NA_IO4 H19<br />
NA_IO5 H18<br />
NA_IO6 H17<br />
NA_IO7 H16<br />
NA_IO8 G23<br />
NA_IO9 G22<br />
NA_IO10 G21<br />
NA_IO11 G20<br />
NA_IO12 G19<br />
NA_IO13 G18<br />
NA_IO14 G17<br />
NA_IO15 G16<br />
NA_RY0 G25<br />
H28<br />
H25<br />
G29<br />
H24<br />
H29<br />
H27<br />
G27<br />
G26<br />
H26<br />
NA_ALE<br />
NA_RE_N<br />
NA_WE_N<br />
NA_PRE<br />
NA_WP_N<br />
NA_CS0_N<br />
NA_CS1_N<br />
NA_CS2_N<br />
NA_CS3_N<br />
NA_RY1 G30<br />
NA_RY2 H30<br />
NA_RY3 G15<br />
J2E<br />
SEAM-40-02.0-S-08-2-A-K<br />
AUX<br />
2-wire CONFIG<br />
JTAG<br />
AUX_TDO<br />
H15<br />
NA_LCK<br />
H10<br />
AUX_PRESENT H12<br />
J2G<br />
SEAM-40-02.0-S-08-2-A-K<br />
DNU<br />
DNU2<br />
G9<br />
G8<br />
H9<br />
H8<br />
H7<br />
G10<br />
G11<br />
H11<br />
H14<br />
G13<br />
H13<br />
AUX_SDA<br />
AUX_SCL<br />
AUX_SA0<br />
AUX_SA1<br />
AUX_SA2<br />
AUX_TDI<br />
AUX_TCK<br />
AUX_TMS<br />
AUX_STANDBY_N<br />
AUX_POR_N<br />
AUX_HMR_N<br />
H32<br />
DNU4 H31<br />
DNU8 G3<br />
DNU9 C1<br />
DNU0 A40<br />
DNU1 B40<br />
DNU5 A30<br />
DNU3 A31<br />
DNU6 G24<br />
DNU7 G12<br />
J2A<br />
SEAM-40-02.0-S-08-2-A-K<br />
DYNAMIC MEMORY INTERFACE<br />
DM_D0 B11<br />
DM_D1 A11<br />
DM_D2 B12<br />
DM_D3 A12<br />
DM_D4 B13<br />
DM_D5 A13<br />
DM_D6 A14<br />
DM_D7 B14<br />
DM_D8 A7<br />
DM_D9 B7<br />
DM_D10 A8<br />
DM_D11 B8<br />
DM_D12 A9<br />
DM_D13 B9<br />
DM_D14 B10<br />
DM_D15 A10<br />
DM_D16 A16<br />
DM_D17 B16<br />
DM_D18 B17<br />
DM_D19 A17<br />
DM_D20 B18<br />
DM_D21 B19<br />
DM_D22 A18<br />
DM_D23 A19<br />
DM_D24 B2<br />
DM_D25 B3<br />
DM_D26 A2<br />
DM_D27 A3<br />
DM_D28 B4<br />
DM_D29 A4<br />
DM_D30 A5<br />
DM_D31 B5<br />
DM_DQS0_DL B15<br />
DM_DQS0_DH A15<br />
DM_DQS1_DL B6<br />
DM_DQS1_DH A6<br />
DM_DQS2_DL B20<br />
DM_DQS2_DH A20<br />
DM_DQS3_DL B1<br />
DM_DQS3_DH A1<br />
E19<br />
DM_A0<br />
D19<br />
DM_A1<br />
E14<br />
DM_A2<br />
E20<br />
DM_A3<br />
E2<br />
DM_A4<br />
E8<br />
DM_A5<br />
E3<br />
DM_A6<br />
D3<br />
DM_A7<br />
D7<br />
DM_A8<br />
E4<br />
DM_A9<br />
D14<br />
DM_A10<br />
D4<br />
DM_A11<br />
E7<br />
DM_A12<br />
E16<br />
DM_A13<br />
D6<br />
DM_A14<br />
D2<br />
DM_A15<br />
E18<br />
DM_BA0<br />
D18<br />
DM_BA1<br />
D16<br />
DM_DQM0<br />
D8<br />
DM_DQM1<br />
D20<br />
DM_DQM2<br />
E6<br />
DM_DQM3<br />
E12<br />
DM_CLK0_DL<br />
D12<br />
DM_CLK0_DH<br />
E5<br />
DM_CKE0<br />
E10<br />
DM_CLK1_DL<br />
D10<br />
DM_CLK1_DH<br />
D5<br />
DM_CKE1<br />
D17<br />
DM_RAS_N<br />
E17<br />
DM_CAS_N<br />
D15<br />
DM_WE_N<br />
E15<br />
DM_CS0_N<br />
D1<br />
DM_CS1_N<br />
C3<br />
DM_RESET_N<br />
C5<br />
DM_ODT0<br />
C4<br />
DM_ODT1<br />
DM_VREF C6<br />
C2<br />
DM_BA2<br />
3<br />
2<br />
2<br />
Date: Tuesday, April 03, 2007<br />
<strong>Sheet</strong> 2 of 6<br />
1<br />
1<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Mechanical Specifications<br />
Advance
PDF: 09005aef827fda9b/Source: 09005aef827fda71 <strong>Micron</strong> Technology, Inc., reserves the right to change products or specifications without notice.<br />
<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 17 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
Figure 8: Top Connector Schematic<br />
5<br />
5<br />
4<br />
4<br />
3<br />
SM_A[0..31]<br />
SM_D[0..31]<br />
D<br />
C<br />
DM_DQM[0..3]<br />
DM_DQM[0..3]<br />
DM_D[0..31]<br />
DM_D[0..31]<br />
DM_A[0..15]<br />
DM_A[0..15]<br />
DM_A0<br />
DM_D0<br />
DM_A1<br />
DM_D1<br />
DM_A2<br />
DM_D2<br />
DM_A3<br />
DM_D3<br />
DM_A4<br />
DM_D4<br />
DM_A5<br />
DM_D5<br />
DM_A6<br />
DM_D6<br />
DM_A7<br />
DM_D7<br />
DM_A8<br />
DM_D8<br />
DM_A9<br />
DM_D9<br />
DM_A10<br />
DM_D10<br />
DM_A11<br />
DM_D11<br />
DM_A12<br />
DM_D12<br />
DM_A13<br />
DM_D13<br />
DM_A14<br />
DM_D14<br />
DM_A15<br />
DM_D15<br />
DM_D16<br />
DM_BA0<br />
DM_D17<br />
DM_BA0<br />
DM_BA1<br />
DM_D18<br />
DM_BA1<br />
DM_BA2<br />
DM_D19<br />
DM_BA2<br />
DM_D20<br />
DM_DQM0<br />
DM_D21<br />
DM_DQM1<br />
DM_D22<br />
DM_DQM2<br />
DM_D23<br />
DM_DQM3<br />
DM_D24<br />
DM_D25<br />
DM_CLK0_DL<br />
DM_D26<br />
DM_CLK0_DL<br />
DM_CLK0_DH<br />
DM_D27<br />
DM_CLK0_DH<br />
DM_CKE0<br />
DM_D28<br />
DM_CKE0<br />
DM_D29<br />
DM_CLK1_DL<br />
DM_D30<br />
DM_CLK1_DL<br />
DM_CLK1_DH<br />
DM_D31<br />
DM_CLK1_DH<br />
DM_CKE1<br />
DM_CKE1<br />
DM_DQS0_DL<br />
DM_RAS_N<br />
DM_DQS0_DH<br />
DM_RAS_N<br />
DM_CAS_N<br />
DM_CAS_N<br />
DM_WE_N<br />
DM_DQS1_DL<br />
DM_WE_N<br />
DM_DQS1_DH<br />
DM_CS1_N_BOT<br />
DM_CS1_N_BOT<br />
DM_CS_FDBK<br />
DM_DQS2_DL<br />
DM_DQS2_DH<br />
DM_RESET_N<br />
DM_RESET_N<br />
DM_DQS3_DL<br />
DM_ODT0<br />
DM_DQS3_DH<br />
DM_ODT0<br />
DM_ODT1<br />
DM_ODT1<br />
J1G<br />
DM_POWER<br />
SEAF-40-05.0-S-08-2-A-K<br />
AUX_3V3<br />
SM_VIO<br />
SM_3V3<br />
SM_1V8<br />
DM_POWER<br />
DM_DQS0_DL<br />
DM_DQS0_DH<br />
FS_VIO<br />
DM_DQS1_DL<br />
DM_DQS1_DH<br />
FS_3V3<br />
DM_DQS2_DL FS_1V8<br />
DM_DQS2_DH<br />
Vref<br />
DM_DQS3_DL<br />
DM_DQS3_DH<br />
NA_1V8<br />
NA_3V3<br />
SM_A[0..31]<br />
SM_A0<br />
SM_A1<br />
SM_A2<br />
SM_A3<br />
SM_A4<br />
SM_A5<br />
SM_A6<br />
SM_A7<br />
SM_A8<br />
SM_A9<br />
SM_A10<br />
SM_A11<br />
SM_A12<br />
SM_A13<br />
SM_A14<br />
SM_A15<br />
SM_A16<br />
SM_A17<br />
SM_A18<br />
SM_A19<br />
SM_A20<br />
SM_A21<br />
SM_A22<br />
SM_A23<br />
SM_A24<br />
SM_A25<br />
SM_A26<br />
SM_A27<br />
SM_A28<br />
SM_A29<br />
SM_A30<br />
SM_A31<br />
SM_BE0<br />
SM_BE0<br />
SM_BE1<br />
SM_BE1<br />
SM_BE2<br />
SM_BE2<br />
SM_BE3<br />
SM_BE3<br />
SM_CLK0<br />
SM_CLK0<br />
SM_CLK1<br />
SM_CLK1<br />
SM_CLK2<br />
SM_CLK2<br />
SM_CLK3<br />
SM_CLK3<br />
SM_CS0_N<br />
SM_CS0_N<br />
SM_CS1_N<br />
SM_CS1_N<br />
SM_CS2_N<br />
SM_CS2_N<br />
SM_CS3_N<br />
SM_CS3_N<br />
SM_WE_N<br />
SM_WE_N<br />
SM_OE_N<br />
SM_OE_N<br />
SM_LBA_N<br />
SM_LBA_N<br />
SM_WP_N<br />
SM_WP_N<br />
SM_RESET_N<br />
SM_RESET_N<br />
SM_CRE_N<br />
SM_CRE_N<br />
SM_PD_N<br />
SM_PD_N<br />
SM_D[0..31]<br />
SM_D0<br />
SM_D1<br />
SM_D2<br />
SM_D3<br />
D<br />
SM_D4<br />
SM_D5<br />
SM_D6<br />
SM_D7<br />
SM_D8<br />
SM_D9<br />
SM_D10<br />
SM_D11<br />
SM_D12<br />
SM_D13<br />
SM_D14<br />
SM_D15<br />
SM_D16<br />
SM_D17<br />
SM_D18<br />
SM_D19<br />
SM_D20<br />
SM_D21<br />
SM_D22<br />
SM_D23<br />
SM_D24<br />
SM_D25<br />
SM_D26<br />
SM_D27<br />
SM_D28<br />
SM_D29<br />
SM_D30<br />
SM_D31<br />
C<br />
SM_BUSY_N_0<br />
SM_BUSY_N_1 SM_BUSY_N_0<br />
SM_BUSY_N_2 SM_BUSY_N_1<br />
SM_BUSY_N_3 SM_BUSY_N_2<br />
SM_BUSY_N_3<br />
SM_IRQ_N<br />
SM_IRQ_N<br />
SM_BWAIT_N<br />
SM_BWAIT_N<br />
SM_DMARQ_N<br />
SM_DMARQ_N<br />
B DNU<br />
DNI<br />
DM_CS_FDBK<br />
B<br />
A<br />
NA_1V8<br />
DNI<br />
NA_CS0_N<br />
DNU0<br />
NA_CLE<br />
NA_ALE<br />
NA_RE_N<br />
NA_WE_N<br />
NA_PRE<br />
NA_WP_N<br />
NA_CS1_N_BOT<br />
NA_CS2_N_BOT<br />
NA_CS3_N_BOT<br />
NA_LCK<br />
DM_CS0_N<br />
NA_IO[0..15]<br />
NA_CLE<br />
NA_ALE<br />
NA_RE_N<br />
NA_WE_N<br />
NA_PRE<br />
NA_WP_N<br />
NA_LCK<br />
NA_IO[0..15]<br />
NA_IO0<br />
NA_IO1<br />
NA_IO2<br />
NA_IO3<br />
NA_IO4<br />
NA_IO5<br />
NA_IO6<br />
NA_IO7<br />
NA_IO8<br />
NA_IO9<br />
NA_IO10<br />
NA_IO11<br />
NA_IO12<br />
NA_IO13<br />
NA_IO14<br />
NA_IO15<br />
NA_RY0<br />
NA_RY1<br />
NA_RY2<br />
NA_RY3<br />
NA_RY0<br />
NA_RY1<br />
NA_RY2<br />
NA_RY3<br />
AUX_3V3<br />
AUX_SDA<br />
AUX_SCL<br />
AUX_SA0_BOT<br />
AUX_SA1_BOT<br />
AUX_TDI<br />
AUX_TCK<br />
AUX_TMS<br />
AUX_STANDBY_N<br />
AUX_POR_N<br />
AUX_HMR_N<br />
AUX_SDA<br />
AUX_SCL<br />
AUX_TDI<br />
AUX_TCK<br />
AUX_TMS<br />
AUX_STANDBY_N<br />
AUX_POR_N<br />
AUX_HMR_N<br />
FS_SI<br />
FS_SCK<br />
FS_WP_N<br />
FS_RESET<br />
FS_CS0_N<br />
FS_CS1_N<br />
FS_CS2_N<br />
FS_CS3_N<br />
AUX_TDO<br />
FS_SI<br />
FS_SCK<br />
FS_WP_N<br />
FS_RESET<br />
FS_CS0_N<br />
FS_CS1_N<br />
FS_CS2_N<br />
FS_CS3_N<br />
AUX_TDO<br />
FS_SO<br />
FS_HOLD_N FS_SO<br />
FS_HOLD_N<br />
<strong>Micron</strong> Technology<br />
Systems Engineering<br />
via A. Pacinotti, 7<br />
67051, Avezzano<br />
ITALY<br />
A<br />
Title<br />
TOP CONNECTOR<br />
D o c u m e n t N u m b e r<br />
R e v i s i o n<br />
Size<br />
M I C R O N - P I S M O 2 - 0 0 0 0 1<br />
4 . 0<br />
A-3<br />
CONFIDENTIAL AND PROPRIETARY INFORMATION<br />
The information contained herein is proprietary of <strong>Micron</strong> Technology. Any reproduction, in whole or in part,<br />
disclosure, or use of this drawing is expressly prohibited except as specified in writing by <strong>Micron</strong> Technology.<br />
A40<br />
DNU1 B40<br />
DNU2 H32<br />
DNU3 A31<br />
DNU4 H31<br />
DNU5 A30<br />
DNU6 G24<br />
DNU7 G12<br />
DNU8 G3<br />
DNU9 C1<br />
J1E<br />
SEAF-40-05.0-S-08-2-A-K<br />
AUX<br />
2-wire CONFIG<br />
JTAG<br />
AUX_TDO H10<br />
AUX_PRESENT H12<br />
J1A<br />
SEAF-40-05.0-S-08-2-A-K<br />
DYNAMIC MEMORY INTERFACE<br />
DM_DQS0_DL<br />
DM_POWER<br />
TP4<br />
G9<br />
AUX_SDA<br />
G8<br />
AUX_SCL<br />
H9<br />
AUX_SA0<br />
H8<br />
AUX_SA1<br />
H7<br />
AUX_SA2<br />
G10<br />
AUX_TDI<br />
G11<br />
AUX_TCK<br />
H11<br />
AUX_TMS<br />
H14<br />
AUX_STANDBY_N<br />
G13<br />
AUX_POR_N<br />
H13<br />
AUX_HMR_N<br />
B15<br />
DM_DQS0_DH A15<br />
DM_DQS1_DL B6<br />
DM_DQS1_DH A6<br />
DM_DQS2_DL B20<br />
DM_DQS2_DH A20<br />
DM_DQS3_DL B1<br />
DM_DQS3_DH A1<br />
E15<br />
DM_CS0_N<br />
D1<br />
DM_CS1_N<br />
C3<br />
DM_RESET_N<br />
C5<br />
DM_ODT0<br />
C4<br />
DM_ODT1<br />
DM_VREF C6<br />
DM_D0 B11<br />
DM_D1 A11<br />
DM_D2 B12<br />
DM_D3 A12<br />
DM_D4 B13<br />
DM_D5 A13<br />
DM_D6 A14<br />
DM_D7 B14<br />
DM_D8 A7<br />
DM_D9 B7<br />
DM_D10 A8<br />
DM_D11 B8<br />
DM_D12 A9<br />
DM_D13 B9<br />
DM_D14 B10<br />
DM_D15 A10<br />
DM_D16 A16<br />
DM_D17 B16<br />
DM_D18 B17<br />
DM_D19 A17<br />
DM_D20 B18<br />
DM_D21 B19<br />
DM_D22 A18<br />
DM_D23 A19<br />
DM_D24 B2<br />
DM_D25 B3<br />
DM_D26 A2<br />
DM_D27 A3<br />
DM_D28 B4<br />
DM_D29 A4<br />
DM_D30 A5<br />
DM_D31 B5<br />
J1F<br />
SEAF-40-05.0-S-08-2-A-K<br />
E19<br />
DM_A0<br />
D19<br />
DM_A1<br />
E14<br />
DM_A2<br />
E20<br />
DM_A3<br />
E2<br />
DM_A4<br />
E8<br />
DM_A5<br />
E3<br />
DM_A6<br />
D3<br />
DM_A7<br />
D7<br />
DM_A8<br />
E4<br />
DM_A9<br />
D14<br />
DM_A10<br />
D4<br />
DM_A11<br />
E7<br />
DM_A12<br />
E16<br />
DM_A13<br />
D6<br />
DM_A14<br />
D2<br />
DM_A15<br />
E18<br />
DM_BA0<br />
D18<br />
DM_BA1<br />
C2<br />
DM_BA2<br />
D16<br />
DM_DQM0<br />
D8<br />
DM_DQM1<br />
D20<br />
DM_DQM2<br />
E6<br />
DM_DQM3<br />
E12<br />
DM_CLK0_DL<br />
D12<br />
DM_CLK0_DH<br />
E5<br />
DM_CKE0<br />
E10<br />
DM_CLK1_DL<br />
D10<br />
DM_CLK1_DH<br />
D5<br />
DM_CKE1<br />
D17<br />
DM_RAS_N<br />
E17<br />
DM_CAS_N<br />
D15<br />
DM_WE_N<br />
C24 +<br />
10U<br />
POWER<br />
AUX<br />
STATIC MEMORY<br />
VSS1<br />
VSS2<br />
VSS3<br />
VSS4<br />
VSS5<br />
DYNAMIC<br />
MEMORY<br />
FAST SERIAL<br />
MEMORY<br />
NAND<br />
MEMORY<br />
F39<br />
F38<br />
F37<br />
F36<br />
R11 0<br />
R12 0<br />
G35<br />
VSS6 G34<br />
VSS7 G33<br />
VSS8 G32<br />
VSS9 B31<br />
VSS10 D31<br />
VSS11 G31<br />
VSS12 B30<br />
VSS13 D30<br />
VSS14<br />
VSS15<br />
VSS16<br />
VSS17<br />
VSS18<br />
VSS19<br />
VSS20<br />
F30<br />
F29<br />
F25<br />
F24<br />
F23<br />
F22<br />
A21<br />
VSS21 B21<br />
VSS22 C21<br />
VSS23 D21<br />
VSS24 E21<br />
VSS25<br />
VSS26<br />
VSS27<br />
VSS28<br />
VSS29<br />
VSS30<br />
VSS31<br />
F20<br />
F19<br />
F18<br />
F17<br />
F15<br />
F14<br />
D13<br />
VSS32 E13<br />
VSS33<br />
VSS34<br />
F12<br />
D11<br />
VSS35 E11<br />
VSS36<br />
VSS37<br />
F10<br />
D9<br />
VSS38 E9<br />
VSS39<br />
VSS40<br />
VSS41<br />
VSS42<br />
VSS43<br />
VSS44<br />
VSS45<br />
VSS46<br />
F9<br />
F8<br />
F7<br />
F6<br />
F5<br />
F4<br />
F2<br />
E1<br />
C22 +<br />
10u<br />
NA_1V8<br />
TP1<br />
F13<br />
F11<br />
G14<br />
C37<br />
C36<br />
C35<br />
C34<br />
C33<br />
C28<br />
C27<br />
C26<br />
C25<br />
C24<br />
C23<br />
C22<br />
C40<br />
C39<br />
C38<br />
C19<br />
C18<br />
C14<br />
C8<br />
C12<br />
C10<br />
C9<br />
C15<br />
C11<br />
C7<br />
C20<br />
C17<br />
C16<br />
C13<br />
G5<br />
G4<br />
F3<br />
G6<br />
F26<br />
F21<br />
F16<br />
F27<br />
F28<br />
AUX_V33_0<br />
AUX_V33_1<br />
AUX_V33_2<br />
SM_VIO_0<br />
SM_VIO_1<br />
SM_VIO_2<br />
SM_VIO_3<br />
SM_VIO_4<br />
SM_VIO_5<br />
SM_VIO_6<br />
SM_VIO_7<br />
SM_VIO_8<br />
SM_V33_0<br />
SM_V33_1<br />
SM_V33_2<br />
SM_V18_0<br />
SM_V18_1<br />
SM_V18_2<br />
DM_VIO_0<br />
DM_VIO_1<br />
DM_VIO_2<br />
DM_VIO_3<br />
DM_VIO_4<br />
DM_VIO_5<br />
DM_VIO_6<br />
DM_VIO_7<br />
DM_VIO_8<br />
DM_VIO_9<br />
DM_VCC_0<br />
DM_VCC_1<br />
DM_VCC_2<br />
DM_VCC_3<br />
FS_VIO_0<br />
FS_VIO_1<br />
FS_V33_0<br />
FS_V18_0<br />
NA_VIO_0<br />
NA_VIO_1<br />
NA_VIO_2<br />
NA_V33_0<br />
NA_V18_0<br />
VSS0<br />
F40<br />
GND<br />
J1D<br />
SEAF-40-05.0-S-08-2-A-K<br />
NAND MEMORY<br />
INTERFACE<br />
NA_RY0<br />
TP7<br />
G25<br />
NA_IO0 H23<br />
NA_IO1 H22<br />
NA_IO2 H21<br />
NA_IO3 H20<br />
NA_IO4 H19<br />
NA_IO5 H18<br />
NA_IO6 H17<br />
NA_IO7 H16<br />
NA_IO8 G23<br />
NA_IO9 G22<br />
NA_IO10 G21<br />
NA_IO11 G20<br />
NA_IO12 G19<br />
NA_IO13 G18<br />
NA_IO14 G17<br />
NA_IO15 G16<br />
G28<br />
NA_CLE<br />
H28<br />
NA_ALE<br />
H25<br />
NA_RE_N<br />
G29<br />
NA_WE_N<br />
H24<br />
NA_PRE<br />
H29<br />
NA_WP_N<br />
H27<br />
NA_CS0_N<br />
G27<br />
NA_CS1_N<br />
G26<br />
NA_CS2_N<br />
H26<br />
NA_CS3_N<br />
NA_RY1 G30<br />
NA_RY2 H30<br />
NA_RY3 G15<br />
J1C<br />
H15<br />
NA_LCK<br />
SEAF-40-05.0-S-08-2-A-K<br />
FAST SERIAL<br />
MEMORY<br />
INTERFACE<br />
G2<br />
FS_SI<br />
F1<br />
FS_SCK FS_HOLD_N<br />
G7<br />
FS_WP_N<br />
H1<br />
FS_RESET_N<br />
H6<br />
FS_CS0_N<br />
H5<br />
FS_CS1_N<br />
H4<br />
FS_CS2_N<br />
H3<br />
FS_CS3_N<br />
H2<br />
FS_SO G1<br />
J1B<br />
SEAF-40-05.0-S-08-2-A-K<br />
STATIC MEMORY INTERFACE<br />
D40<br />
SM_BE0<br />
E40<br />
SM_BE1<br />
E30<br />
SM_BE2<br />
E31<br />
SM_BE3<br />
C32<br />
SM_CLK0<br />
C31<br />
SM_CLK1<br />
C30<br />
SM_CLK2<br />
C29<br />
SM_CLK3<br />
H40<br />
SM_CS0_N<br />
H39<br />
SM_CS1_N<br />
H38<br />
SM_CS2_N<br />
H37<br />
SM_CS3_N<br />
F32<br />
SM_WE_N<br />
F31<br />
SM_OE_N<br />
SM_IRQ_N<br />
F33<br />
SM_LBA_N<br />
H33<br />
SM_WP_N<br />
H34<br />
SM_RESET_N<br />
G38<br />
SM_CRE_N<br />
H35<br />
SM_PD_N<br />
R9 0<br />
R10 0<br />
G37<br />
SM_BWAIT_N F35<br />
SM_DMARQ_N G39<br />
D39<br />
SM_A0<br />
SM_D0<br />
E39<br />
SM_A1<br />
D38<br />
SM_A2<br />
E38<br />
SM_A3<br />
D37<br />
SM_A4<br />
E37<br />
SM_A5<br />
D36<br />
SM_A6<br />
E36<br />
SM_A7<br />
D35<br />
SM_A8<br />
E35<br />
SM_A9<br />
D34<br />
SM_A10<br />
E34<br />
SM_A11<br />
D33<br />
SM_A12<br />
E33<br />
SM_A13<br />
D32<br />
SM_A14<br />
E32<br />
SM_A15<br />
D29<br />
SM_A16<br />
E29<br />
SM_A17<br />
D28<br />
SM_A18<br />
E28<br />
SM_A19<br />
D27<br />
SM_A20<br />
E27<br />
SM_A21<br />
D26<br />
SM_A22<br />
E26<br />
SM_A23<br />
D25<br />
SM_A24<br />
E25<br />
SM_A25<br />
D24<br />
SM_A26<br />
E24<br />
SM_A27<br />
D23<br />
SM_A28<br />
E23<br />
SM_A29<br />
D22<br />
SM_A30<br />
E22<br />
SM_A31<br />
A39<br />
SM_D1 A38<br />
SM_D2 A37<br />
SM_D3 A36<br />
SM_D4 A35<br />
SM_D5 A34<br />
SM_D6 A33<br />
SM_D7 A32<br />
SM_D8 B39<br />
SM_D9 B38<br />
SM_D10 B37<br />
SM_D11 B36<br />
SM_D12 B35<br />
SM_D13 B34<br />
SM_D14 B33<br />
SM_D15 B32<br />
SM_D16 A29<br />
SM_D17 A28<br />
SM_D18 A27<br />
SM_D19 A26<br />
SM_D20 A25<br />
SM_D21 A24<br />
SM_D22 A23<br />
SM_D23 A22<br />
SM_D24 B29<br />
SM_D25 B28<br />
SM_D26 B27<br />
SM_D27 B26<br />
SM_D28 B25<br />
SM_D29 B24<br />
SM_D30 B23<br />
SM_D31 B22<br />
SM_BUSY_N_0<br />
SM_BUSY_N_1<br />
F34<br />
G40<br />
SM_BUSY_N_2 G36<br />
SM_BUSY_N_3 H36<br />
+ C23<br />
10u<br />
3<br />
2<br />
2<br />
Date: Tuesday, April 03, 2007<br />
<strong>Sheet</strong> 3 of 6<br />
1<br />
1<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Mechanical Specifications<br />
Advance
PDF: 09005aef827fda9b/Source: 09005aef827fda71 <strong>Micron</strong> Technology, Inc., reserves the right to change products or specifications without notice.<br />
<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 18 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
Figure 9: Mobile DDR DRAM Interface Schematic<br />
DM_D[0..31]<br />
5<br />
5<br />
4<br />
4<br />
3<br />
DM_A[0..15]<br />
DM_A[0..15]<br />
D D<br />
TERM_DM_DQS2_DH R21 33 DM_DQS2_DH<br />
DM_DQS2_DH<br />
U3<br />
C<br />
TERM_DM_D23<br />
TERM_DM_D21<br />
TERM_DM_D22<br />
TERM_DM_D20<br />
TERM_DM_D19<br />
TERM_DM_D18<br />
TERM_DM_D16<br />
TERM_DM_D17<br />
TERM_DM_DQS0_DH<br />
TERM_DM_D7<br />
TERM_DM_D6<br />
TERM_DM_D5<br />
TERM_DM_D4<br />
TERM_DM_D3<br />
TERM_DM_D2<br />
TERM_DM_D1<br />
TERM_DM_D0<br />
RN7<br />
8 1<br />
7 2<br />
6 3<br />
5 4<br />
33<br />
R14 33<br />
RN5<br />
8 1<br />
7 2<br />
6 3<br />
5 4<br />
DM_D23<br />
DM_D21<br />
DM_D22<br />
DM_D20<br />
DM_D19<br />
DM_D18<br />
DM_D16<br />
DM_D17<br />
DM_DQS0_DH<br />
DM_DQS0_DH<br />
DM_D7<br />
DM_D6<br />
DM_D5<br />
DM_D4<br />
DM_D3<br />
DM_D2<br />
DM_D1<br />
DM_D0<br />
DM_DQM[0..3]<br />
DM_DQM[0..3]<br />
DM_A0<br />
DM_A1<br />
DM_A2<br />
DM_A3<br />
DM_A4<br />
DM_A5<br />
DM_A6<br />
DM_A7<br />
DM_A8<br />
DM_A9<br />
DM_A10<br />
DM_A11<br />
DM_A12<br />
DM_A13<br />
DM_BA0<br />
DM_BA1<br />
DM_DQM0<br />
DM_DQM1<br />
DM_DQM2<br />
DM_DQM3<br />
TERM_DM_DQS0_DH<br />
TERM_DM_DQS1_DH<br />
TERM_DM_DQS2_DH<br />
TERM_DM_DQS3_DH<br />
DM_CAS_N<br />
DM_RAS_N<br />
DM_WE_N<br />
DM_CS0_N<br />
DM_CKE0<br />
DM_CLK0_DH<br />
C29<br />
0402<br />
J8<br />
J9<br />
K7<br />
K9<br />
K1<br />
K3<br />
J1<br />
J2<br />
J3<br />
H1<br />
J7<br />
H2<br />
H3<br />
H8<br />
H9<br />
K2<br />
G8<br />
A0<br />
A1<br />
A2<br />
A3<br />
A4<br />
A5<br />
A6<br />
A7<br />
A8<br />
A9<br />
A10/AP<br />
A11<br />
NC/A12<br />
BA0<br />
BA1<br />
DM1<br />
CAS<br />
MT46HXXM32LF<br />
TERM_DM_D0<br />
TERM_DM_D1<br />
TERM_DM_D2<br />
TERM_DM_D3<br />
TERM_DM_D4<br />
TERM_DM_D5<br />
TERM_DM_D6<br />
TERM_DM_D7<br />
TERM_DM_D8<br />
TERM_DM_D9<br />
TERM_DM_D10<br />
TERM_DM_D11<br />
TERM_DM_D12<br />
TERM_DM_D13<br />
TERM_DM_D14<br />
TERM_DM_D15<br />
TERM_DM_D16<br />
TERM_DM_D17<br />
TERM_DM_D18<br />
TERM_DM_D19<br />
TERM_DM_D20<br />
TERM_DM_D21<br />
TERM_DM_D22<br />
TERM_DM_D23<br />
TERM_DM_D24<br />
TERM_DM_D25<br />
TERM_DM_D26<br />
TERM_DM_D27<br />
TERM_DM_D28<br />
TERM_DM_D29<br />
TERM_DM_D30<br />
TERM_DM_D31<br />
C<br />
33<br />
1n 0402<br />
0402<br />
TERM_DM_D15<br />
TERM_DM_D14<br />
TERM_DM_D12<br />
TERM_DM_D13<br />
DM_D15<br />
DM_D14<br />
DM_D12<br />
DM_D13<br />
DM_CLK0_DL<br />
DM0<br />
K8<br />
G7<br />
WE<br />
DQ0 R8<br />
DQ1 P7<br />
DQ2 P8<br />
DQ3 N7<br />
DQ4 N8<br />
DQ5 M7<br />
DQ6 M8<br />
DQ7<br />
DQ8<br />
DQ9<br />
L7<br />
L3<br />
M2<br />
DQ10 M3<br />
DQ11 N2<br />
DQ12 N3<br />
DQ13 P2<br />
DQ14 P3<br />
DQ15 R2<br />
F7<br />
G9<br />
H7<br />
G1<br />
G2<br />
G3<br />
NC/A13<br />
RAS<br />
CS<br />
CKE<br />
CLK<br />
CLK<br />
DQ29 B2<br />
DQ16 A8<br />
DQ17 B7<br />
DQ18 B8<br />
DQ19 C7<br />
DQ20 C8<br />
DQ21 D7<br />
DQ22 D8<br />
DQ23 E7<br />
DQ24 E3<br />
DQ25 D2<br />
DQ26 D3<br />
DQ27 C2<br />
DQ28 C3<br />
DQ30 B3<br />
DQ31 A2<br />
F8<br />
F2<br />
E2<br />
DM2<br />
DM3<br />
DQS3<br />
DQS2<br />
E8 DQS1<br />
L2 DQS0<br />
RN8<br />
8 1<br />
7 2<br />
6 3<br />
5 4<br />
33<br />
RN6<br />
8 1<br />
7 2<br />
6 3<br />
5 4<br />
33<br />
R3<br />
49.9<br />
L8<br />
R6<br />
49.9<br />
RN4<br />
8<br />
7<br />
6<br />
5<br />
1<br />
2<br />
3<br />
4<br />
B TERM_DM_D11<br />
TERM_DM_D10<br />
TERM_DM_D9<br />
TERM_DM_D8<br />
RN3<br />
8 1<br />
7 2<br />
6 3<br />
5 4<br />
33<br />
DM_D11<br />
DM_D10<br />
DM_D9<br />
DM_D8<br />
DM_CS0_N<br />
DM_WE_N<br />
DM_CAS_N<br />
DM_CS0_N<br />
DM_WE_N<br />
DM_CAS_N<br />
B<br />
DM_RAS_N<br />
DM_RAS_N<br />
TERM_DM_DQS1_DH<br />
TERM_DM_D30<br />
TERM_DM_D31<br />
TERM_DM_D29<br />
TERM_DM_D28<br />
TERM_DM_D27<br />
TERM_DM_D25<br />
TERM_DM_D26<br />
TERM_DM_D24<br />
33<br />
R8 33<br />
RN2<br />
8<br />
7<br />
6<br />
33<br />
RN1<br />
8<br />
7<br />
6<br />
1<br />
2<br />
3<br />
5 4<br />
1<br />
2<br />
3<br />
5 4<br />
DM_DQS1_DH<br />
DM_D30<br />
DM_D31<br />
DM_D29<br />
DM_D28<br />
DM_D27<br />
DM_D25<br />
DM_D26<br />
DM_D24<br />
DM_DQS1_DH<br />
DM_POWER<br />
C31<br />
100n<br />
DM_POWER<br />
C30<br />
100n<br />
C32<br />
100n<br />
C33<br />
100n<br />
A<br />
33<br />
Title<br />
A<br />
C25 C21 C26 C27 C19 C20 C18 C2 C17 C28 C15 C16<br />
100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n<br />
MOBILE DDR<br />
TERM_DM_DQS3_DH R7 33 DM_DQS3_DH<br />
DM_DQS3_DH<br />
D o c u m e n t N u m b e r<br />
M I C R O N - P I S M O 2 - 0 0 0 0 1<br />
R e v i s i o n<br />
4 . 0<br />
Size<br />
A-3<br />
3<br />
C5<br />
100n<br />
Package 0306<br />
C6<br />
100n<br />
C4<br />
100n<br />
C1<br />
100n<br />
C3<br />
100n<br />
DM_POWER<br />
C34<br />
100n<br />
VddQ_c C9<br />
VddQ_d D1<br />
VddQ_b B1<br />
VddQ_a A7<br />
VddQ_e E9<br />
VddQ_f<br />
L9<br />
VddQ_g M1<br />
VddQ_h N9<br />
VddQ_m P1<br />
VddQ_n R7<br />
128/512 Mb Mobile DDR<br />
4/16Mx32- VFBGA<br />
VssQ_a<br />
VssQ_b<br />
VssQ_c<br />
VssQ_d<br />
VssQ_e<br />
VssQ_f<br />
VssQ_g<br />
VssQ_h<br />
VssQ_m<br />
VssQ_n<br />
A3<br />
B9<br />
C1<br />
D9<br />
E1<br />
L1<br />
M9<br />
N1<br />
P9<br />
R3<br />
C13<br />
100n<br />
2<br />
C14<br />
100n<br />
2<br />
Vdd_a A9<br />
Vdd_b<br />
F1<br />
Vdd_c R9<br />
Vss_a<br />
Vss_b<br />
Vss_c<br />
A1<br />
F9<br />
R1<br />
NC<br />
F3<br />
DM_CKE0<br />
DM_CLK0_DL<br />
DM_CLK0_DH<br />
DM_BA0<br />
DM_BA1<br />
CONFIDENTIAL AND PROPRIETARY INFORMATION<br />
1<br />
DM_CKE0<br />
DM_CLK0_DL<br />
DM_CLK0_DH<br />
DM_BA0<br />
DM_BA1<br />
<strong>Micron</strong> Technology<br />
Systems Engineering<br />
via A. Pacinotti, 7<br />
67051, Avezzano<br />
ITALY<br />
The information contained herein is proprietary of <strong>Micron</strong> Technology. Any reproduction, in whole or in part,<br />
disclosure, or use of this drawing is expressly prohibited except as specified in writing by <strong>Micron</strong> Technology.<br />
Date: Tuesday, April 03, 2007<br />
<strong>Sheet</strong> 4 of 6<br />
1<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Mechanical Specifications<br />
Advance
PDF: 09005aef827fda9b/Source: 09005aef827fda71 <strong>Micron</strong> Technology, Inc., reserves the right to change products or specifications without notice.<br />
<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 19 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
Figure 10: NAND Flash Interface Schematic<br />
5<br />
5<br />
NA_1V8<br />
4<br />
4<br />
3<br />
100n 100n 100n<br />
100n 100n 100n<br />
100n 100n 100n 100n 100n 100n<br />
D D<br />
U10<br />
NA_IO[0..15]<br />
NA_IO[0..15]<br />
C<br />
NA_CS0_N<br />
NAND_WP<br />
NA_RY0<br />
NA_CLE<br />
NA_ALE<br />
NA_RE_N<br />
NA_WE_N<br />
LCK<br />
NA_IO0<br />
NA_IO1<br />
NA_IO2<br />
NA_IO3<br />
NA_IO4<br />
NA_IO5<br />
NA_IO6<br />
NA_IO7<br />
NA_IO[0..15]<br />
NA_IO[0..15]<br />
NA_CS0_N<br />
NAND_WP<br />
NA_RY0<br />
NA_CLE<br />
NA_ALE<br />
NA_RE_N<br />
NA_WE_N<br />
LCK<br />
C6<br />
C3<br />
C8<br />
D5<br />
C4<br />
D4<br />
C7<br />
G5<br />
CE<br />
WP<br />
R/B<br />
CLE<br />
ALE<br />
RE<br />
WE<br />
LOCK<br />
NA_IO0<br />
NA_IO1<br />
NA_IO2<br />
NA_IO3<br />
NA_IO4<br />
NA_IO5<br />
NA_IO6<br />
NA_IO7<br />
NA_IO8<br />
NA_IO9<br />
NA_IO10<br />
NA_IO11<br />
NA_IO12<br />
NA_IO13<br />
NA_IO14<br />
NA_IO15<br />
C<br />
A1<br />
B9<br />
B10<br />
D3<br />
D6<br />
E3<br />
E4<br />
E5<br />
NC_0<br />
NC_5<br />
NC_6<br />
NC_7<br />
NC_8<br />
NC_11<br />
NC_12<br />
NC_13<br />
NC_24<br />
NA_1V8<br />
MT29F1G16AB<br />
B B<br />
G4<br />
NC_23 G3<br />
B1<br />
NC_4<br />
NC_21<br />
NC_22<br />
F7<br />
F8<br />
NC_3<br />
A10 NC_2<br />
A9 NC_1<br />
I/O7<br />
A2<br />
G7<br />
I/O5<br />
I/O6<br />
J7<br />
G6<br />
I/O4 K6<br />
E8<br />
NC_16<br />
NC_15<br />
I/O2<br />
I/O3<br />
J5<br />
D7<br />
D8<br />
E6<br />
E7<br />
NC_9<br />
NC_10<br />
NC_14<br />
K4<br />
I/O1 H4<br />
I/O0<br />
I/O8<br />
J3<br />
NC_17<br />
NC_18<br />
NC_19<br />
NC_20<br />
F3<br />
F4<br />
F5<br />
F6<br />
H3<br />
I/O9<br />
I/O10<br />
J4<br />
H5<br />
I/O11 K5<br />
I/O12 H6<br />
I/O13 K7<br />
I/O14 H7<br />
I/O15<br />
J8<br />
NC_26 G8<br />
NC_27<br />
NC_28<br />
NC_29<br />
NC_30<br />
NC_31<br />
L1<br />
L2<br />
L9<br />
L10<br />
M1<br />
NC_32 M2<br />
NC_33 M9<br />
NC_34 M10<br />
U11<br />
I/O0<br />
MT29F1G08AB<br />
R23<br />
1k<br />
H4<br />
I/O1<br />
I/O2<br />
J4<br />
K4<br />
I/O3 K5<br />
I/O4 K6<br />
I/O5<br />
I/O6<br />
J7<br />
K7<br />
I/O7<br />
J8<br />
NC_27 G8<br />
NC_28 H3<br />
NC_29 H5<br />
NC_30 H6<br />
NC_31 H7<br />
F4<br />
F5<br />
F6<br />
NC_18<br />
NC_19<br />
NC_20<br />
NC_21<br />
NC_22<br />
NC_23<br />
NC_32<br />
NC_33<br />
F7<br />
F8<br />
J3<br />
J5<br />
G3<br />
NC_24 G4<br />
NC_25 G6<br />
NC_26 G7<br />
NC_34<br />
NC_35<br />
NC_36<br />
NC_37<br />
NC_38<br />
L1<br />
L2<br />
L9<br />
L10<br />
M1<br />
NC_39 M2<br />
NC_40 M9<br />
NC_41 M10<br />
C6<br />
C3<br />
C8<br />
D5<br />
C4<br />
D4<br />
C7<br />
G5<br />
CE<br />
WP<br />
R/B<br />
CLE<br />
ALE<br />
RE<br />
WE<br />
LOCK<br />
A1<br />
A2<br />
A9<br />
A10<br />
B1<br />
B9<br />
B10<br />
D3<br />
D6<br />
D7<br />
D8<br />
E3<br />
E4<br />
E5<br />
E6<br />
E7<br />
E8<br />
F3<br />
NC_0<br />
NC_1<br />
NC_2<br />
NC_3<br />
NC_4<br />
NC_5<br />
NC_6<br />
NC_7<br />
NC_8<br />
NC_9<br />
NC_10<br />
NC_11<br />
NC_12<br />
NC_13<br />
NC_14<br />
NC_15<br />
NC_16<br />
NC_17<br />
J5<br />
HE-142 1<br />
2<br />
Place on the<br />
top side<br />
C44<br />
LCK<br />
C43<br />
Package 0306 Package 0306<br />
C45 C46 C47 C48<br />
C38 C37 C39 C40<br />
NA_1V8<br />
NA_1V8<br />
R15<br />
NA_LCK<br />
NA_CS0_N<br />
NA_LCK<br />
NA_CS0_N<br />
R22 0<br />
DNI<br />
1k<br />
NA_RY0<br />
NA_CLE<br />
NA_CLE<br />
NA_RY0<br />
<strong>Micron</strong> Technology<br />
Systems Engineering<br />
NA_ALE<br />
NA_ALE<br />
via A. Pacinotti, 7<br />
67051, Avezzano<br />
A<br />
NA_RE_N<br />
NA_WE_N<br />
NA_RE_N<br />
NA_WE_N<br />
R16<br />
DNI<br />
1k<br />
Title<br />
ITALY<br />
A<br />
NA_WP_N<br />
NA_WP_N<br />
R18 0<br />
NAND_WP<br />
NAND<br />
R17<br />
DNI<br />
D o c u m e n t N u m b e r<br />
M I C R O N - P I S M O 2 - 0 0 0 0 1<br />
R e v i s i o n<br />
4 . 0<br />
Size<br />
A-3<br />
1k<br />
Vcc_1<br />
J6<br />
Vcc_2 H8<br />
FLASH NAND x8 - BGA<br />
Vss_1<br />
Vss_2<br />
Vss_3<br />
K8<br />
C5<br />
K3<br />
3<br />
NA_1V8<br />
2<br />
2<br />
NA_1V8<br />
Vcc_2 H8<br />
Vcc_1<br />
J6<br />
1.8V NAND x16 - BGA<br />
Vss_1<br />
Vss_2<br />
Vss_3<br />
K8<br />
C5<br />
K3<br />
C41<br />
C42<br />
CONFIDENTIAL AND PROPRIETARY INFORMATION<br />
The information contained herein is proprietary of <strong>Micron</strong> Technology. Any reproduction, in whole or in part,<br />
disclosure, or use of this drawing is expressly prohibited except as specified in writing by <strong>Micron</strong> Technology.<br />
Date: Tuesday, April 03, 2007<br />
<strong>Sheet</strong> 5 of 6<br />
1<br />
1<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Mechanical Specifications<br />
Advance
PDF: 09005aef827fda9b/Source: 09005aef827fda71 <strong>Micron</strong> Technology, Inc., reserves the right to change products or specifications without notice.<br />
<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 20 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
Figure 11: EEPROM Interface Schematic<br />
5<br />
5<br />
4<br />
4<br />
3<br />
D D<br />
SERIAL MEMORY (PD)<br />
C DNI<br />
R19<br />
R20<br />
C<br />
0<br />
0<br />
0805<br />
0805<br />
AUX_SA0_BOT<br />
AUX_SA1_BOT<br />
AUX_SA2_BOT<br />
AUX_SA0_BOT<br />
AUX_SA1_BOT<br />
AUX_SA2_BOT<br />
U9<br />
1<br />
A0<br />
2<br />
A1<br />
3<br />
A2<br />
4<br />
VSS<br />
VCC 8<br />
WP 7<br />
SCL<br />
6<br />
SDA 5<br />
24xx64-I/ST<br />
AUX_SCL<br />
AUX_SDA<br />
C35<br />
100n<br />
AUX_3V3 NA_1V8<br />
AUX_SCL<br />
AUX_SDA<br />
C36<br />
100n<br />
B B<br />
<strong>Micron</strong> Technology<br />
Systems Engineering<br />
via A. Pacinotti, 7<br />
67051, Avezzano<br />
ITALY<br />
A A<br />
Title<br />
3<br />
2<br />
2<br />
EEPROM<br />
D o c u m e n t N u m b e r<br />
M I C R O N - P I S M O 2 - 0 0 0 0 1<br />
CONFIDENTIAL AND PROPRIETARY INFORMATION<br />
1<br />
1<br />
R e v i s i o n<br />
4 . 0<br />
The information contained herein is proprietary of <strong>Micron</strong> Technology. Any reproduction, in whole or in part,<br />
disclosure, or use of this drawing is expressly prohibited except as specified in writing by <strong>Micron</strong> Technology.<br />
Date: Tuesday, April 03, 2007<br />
<strong>Sheet</strong> 6 of 6<br />
Size<br />
A-3<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Mechanical Specifications<br />
Advance
Appendix A<br />
Figure 12: <strong>PISMO</strong>2-00001 Part Number Diagram<br />
<strong>Micron</strong> <strong>Module</strong><br />
Part Number<br />
Table 9: Reference Documents<br />
Advance<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Appendix A<br />
Mobile DDR SDRAM Density<br />
D28 = 128Mb<br />
D56 = 256Mb<br />
D12 = 512Mb<br />
D10 = 1Gb<br />
Mobile DDR SDRAM Cycle Timing<br />
C06 = 6ns @ CAS latency = 3<br />
C75 = 7.5ns @ CAS latency = 3<br />
<strong>PISMO</strong>2-00001-D12-C75-N1-X8-B<br />
Document Description Manufacturer Part Numbers<br />
<strong>PISMO</strong>2 specification – –<br />
1Gb NAND Flash data sheet <strong>Micron</strong> MT29F1G8AB MT29F1G16AB<br />
128Mb Mobile DDR SDRAM data sheet <strong>Micron</strong> MT46H4M32LF<br />
256Mb Mobile DDR SDRAM data sheet <strong>Micron</strong> MT46H8M32LF<br />
512Mb Mobile DDR SDRAM data sheet <strong>Micron</strong> MT46H16M32LF<br />
<strong>PISMO</strong>2-P6960 LSA adapter data sheet <strong>Micron</strong> <strong>PISMO</strong>2-P6960<br />
Serial EEPROM data sheet Microchip 24AA64-I/ST I2C<br />
Notes: 1. <strong>Micron</strong> data sheets can be downloaded from www.micron.com.<br />
Operating Temperature Range<br />
Blank = Commercial (0° to +70°C)<br />
IT = Industrial/Extended (–40° to +85°C)<br />
NAND Package<br />
B = 63-ball VFBGA<br />
NAND Bus Width<br />
x8 = 8-bit<br />
x16 = 16-bit<br />
NAND Density<br />
N1 = 1Gb<br />
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900<br />
prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992<br />
<strong>Micron</strong>, the M logo, and the <strong>Micron</strong> logo are trademarks of <strong>Micron</strong> Technology, Inc. All other trademarks are the property of their respective<br />
owners.<br />
Advance: This data sheet contains initial descriptions of products still under development.<br />
PDF: 09005aef827fda9b/Source: 09005aef827fda71 <strong>Micron</strong> Technology, Inc., reserves the right to change products or specifications without notice.<br />
<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 21 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.