DDR3 Advantages Presentation - Micron
DDR3 Advantages Presentation - Micron
DDR3 Advantages Presentation - Micron
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<strong>DDR3</strong> <strong>Advantages</strong><br />
©2009 <strong>Micron</strong> Technology, Inc. All rights reserved. Products are warranted only to meet <strong>Micron</strong>’s production data sheet specifications.<br />
Information, products and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without<br />
warranties of any kind. Dates are estimates only. Drawings not to scale. <strong>Micron</strong> and the <strong>Micron</strong> logo are trademarks of <strong>Micron</strong> Technology, Inc.<br />
All other trademarks are the property of their respective owners.
• Lower power<br />
• Higher speed<br />
• Master reset<br />
• More performance<br />
• Larger densities<br />
4/8/2009 2<br />
©2009 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
<strong>DDR3</strong> <strong>Advantages</strong><br />
• Modules for all applications
4/8/2009 3<br />
©2009 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
Lower Power<br />
• Supply voltage reduced from 1.8V to1.5V<br />
� ~30% reduction in power due to supply voltage alone<br />
• Lower I/O buffer power<br />
� 34 ohm driver vs. 18 ohm driver<br />
Power Relative to DDR2<br />
Estimated<br />
Source: <strong>Micron</strong><br />
DDR2<br />
533<br />
DDR2<br />
667<br />
DDR2<br />
800<br />
<strong>DDR3</strong><br />
800<br />
<strong>DDR3</strong><br />
1067<br />
<strong>DDR3</strong><br />
1333<br />
<strong>DDR3</strong><br />
1600
Designed for HighSpeed<br />
• Improved pinout<br />
• Flyby architecture<br />
• READ and WRITE leveling<br />
• Data calibration through ZQ resistor<br />
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©2009 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
Signaling<br />
• Dynamic ODT for improved WRITE signaling<br />
• 2 DIMMs/channel at <strong>DDR3</strong> frequencies
• Improved power delivery<br />
� More power and ground balls<br />
• Improved signal quality<br />
� Improved signal integrity<br />
� Improved power and ground<br />
distribution<br />
� Improved signal referencing<br />
• Fully populated ball grid<br />
� Improved mechanical reliability<br />
• Improved D/Q array<br />
� Less D/Q skew<br />
� Tighter D/Q timing<br />
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©2009 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
Improved Pinout<br />
<strong>DDR3</strong><br />
DDR2
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©2009 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
Improved Module Layout<br />
• Flyby architecture for C/A, control, clocks<br />
� Improved signal integrity for high speeds<br />
� Onmodule termination<br />
� Used on UDIMM, SODIMM, RDIMM<br />
• Not used on DDR2 –<br />
not needed at lower frequencies
4/8/2009 7<br />
©2009 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
READ/WRITE Leveling<br />
• Allows for controller to determine the time delta for data<br />
command to data output of each DRAM (byte lane)<br />
� Enables controller to capture data for each byte lane<br />
� Enables controller to adjust receiver timing per byte lane
• Improved system stability<br />
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©2009 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
Master Reset<br />
� Eliminates unknown startup<br />
states<br />
� Known initialization and<br />
recovery state<br />
� Cold boot reset<br />
� Warm boot reset<br />
� Removes controller burden to<br />
ensure no illegal commands
4/8/2009 9<br />
©2009 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
Increased Peak Performance<br />
• 2X the bandwidth of DDR2<br />
� Component per pin<br />
� 800 MT/s to 1600 MT/s<br />
� Bus bandwidth<br />
� 6400 MT/s to 12,800 MT/s<br />
• 8 banks vs. 4 banks<br />
� More open banks for<br />
backtoback access<br />
� Hide turnaround time<br />
� Hide t RP<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
1<br />
0<br />
3200<br />
4200<br />
5300<br />
6400<br />
8500<br />
10600<br />
DDR2 <strong>DDR3</strong><br />
12800
• <strong>DDR3</strong> market dynamics<br />
� 512Mb/1Gb crossover<br />
� 1Gb/2Gb crossover<br />
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©2009 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
<strong>DDR3</strong> Market<br />
� <strong>DDR3</strong> life from 2007 through 2014<br />
100%<br />
90%<br />
80%<br />
70%<br />
60%<br />
50%<br />
40%<br />
30%<br />
20%<br />
10%<br />
0%<br />
Source: <strong>Micron</strong> Marketing<br />
2005 2006 2007 2008 2009 2010 2011 2012<br />
512Mb to 1Gb price parity<br />
2H08<br />
1Gb to 2Gb price parity 2H11<br />
4 Gb<br />
2 Gb<br />
1 Gb<br />
512 Mb<br />
256 Mb<br />
128 Mb<br />
64 Mb<br />
16 Mb
100%<br />
90%<br />
80%<br />
70%<br />
60%<br />
50%<br />
40%<br />
30%<br />
20%<br />
10%<br />
0%<br />
DDR2 to <strong>DDR3</strong> Crossover<br />
4/8/2009 11<br />
©2009 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
<strong>DDR3</strong> Ramp<br />
2007 2008 2009 2010 2011 2012<br />
250%<br />
200%<br />
150%<br />
100%<br />
2007 2008 2009 2010<br />
DDR 14% 3% 2% 1%<br />
DDR2 83% 78% 64% 33%<br />
<strong>DDR3</strong> 3% 19% 34% 60%<br />
50%<br />
0%<br />
DDR4<br />
<strong>DDR3</strong><br />
DDR2<br />
DDR<br />
Premium<br />
Source: <strong>Micron</strong> Marketing
Module<br />
Density<br />
Component<br />
Density<br />
DDR2 UDIMM (18)<br />
4/8/2009 12<br />
©2009 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
Maximum* Module Density<br />
SODIMM(16)<br />
RDIMM(36)<br />
FBDIMM(36)<br />
<strong>DDR3</strong> UDIMM (18)<br />
SODIMM(16)<br />
RDIMM(36)<br />
FBDIMM(36)<br />
256Mb 512Mb 1Gb 2Gb 4Gb 8Gb<br />
512MB<br />
512MB<br />
1GB<br />
1 GB<br />
1GB<br />
1GB<br />
2 GB<br />
2GB<br />
n/a 1GB<br />
1GB<br />
2 GB<br />
2 GB<br />
2 GB<br />
2 GB<br />
4GB<br />
4 GB<br />
2 GB<br />
2 GB<br />
4 GB<br />
4 GB<br />
4 GB<br />
4 GB<br />
8 GB<br />
8GB<br />
4 GB<br />
4 GB<br />
8 GB<br />
8GB<br />
*Maximum density requires stacked and/or high component count<br />
planar versions of modules<br />
** 4Gb is a JEDEC standard; <strong>Micron</strong> has no plans to support it<br />
n/a** n/a<br />
8 GB<br />
8 GB<br />
16GB<br />
16GB<br />
16 GB<br />
16 GB<br />
32GB<br />
32GB
Unbuffered DIMM<br />
Desktop<br />
Notebook<br />
Server<br />
Networking<br />
<strong>DDR3</strong> Modules for All Applications<br />
4/8/2009 13<br />
©2009 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
1H07 2H07 1H08 2H08 1H09 2H09<br />
Unbuffered DIMM<br />
Small Outline DIMM<br />
Registered DIMM<br />
Fully Buffered DIMM<br />
Very Low Profile DIMM
4/8/2009 14<br />
©2009 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
Summary<br />
• <strong>DDR3</strong> provides more bandwidth at lower power<br />
• Package, pinout, and signaling improvements for<br />
higherspeed<br />
operation<br />
• Master reset for improved system stability<br />
• Larger densities<br />
• Modules for all applications
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