400 MT/s NAND Interface Solutions - Micron
400 MT/s NAND Interface Solutions - Micron
400 MT/s NAND Interface Solutions - Micron
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Santa Clara, CA August 2011<br />
<strong>400</strong> <strong>MT</strong>/s <strong>NAND</strong> <strong>Interface</strong> <strong>Solutions</strong><br />
Terry Grunzke<br />
<strong>Micron</strong> Technology, Inc.<br />
1
Why <strong>400</strong> <strong>MT</strong>/s <strong>Interface</strong> Speeds?<br />
� <strong>NAND</strong> architectures are moving toward larger data<br />
transfer sizes<br />
� Increased bandwidth<br />
� High-performance computing applications<br />
� Hi High-density h d it SSD SSDs<br />
� USB 3.0<br />
120<br />
� Reduced latency 100<br />
Santa Clara, CA August 2011<br />
MicrooSeconds<br />
80<br />
60<br />
40<br />
20<br />
0<br />
8K page<br />
200 <strong>MT</strong>/s<br />
16K page<br />
200 <strong>MT</strong>/s<br />
8K page<br />
<strong>400</strong> <strong>MT</strong>/s<br />
16K page<br />
<strong>400</strong> <strong>MT</strong>/s<br />
Xfer Time<br />
Array Time<br />
16K page<br />
dual plane<br />
<strong>400</strong> <strong>MT</strong>/s 2
<strong>400</strong> <strong>MT</strong>/s <strong>NAND</strong> <strong>Interface</strong> <strong>Solutions</strong><br />
� ONFI 3.0 NV-DDR2<br />
• Released March 2011<br />
• ONFI 3.0 Webinar: micron.com/ONFI-3<br />
� TToggle l MMode d 22.0 0<br />
• Announced July 2010<br />
�� Work occurring in JEDEC on <strong>400</strong> <strong>MT</strong>/s<br />
� Reduced CIO<br />
• Removes features to reduce loading<br />
Santa Clara, CA August 2011<br />
3
Toggle Mode 22.0 0<br />
• <strong>400</strong> <strong>MT</strong>/s DDR interface<br />
• Compatible with ONFI 3.0 NV-DDR2<br />
• Differential signaling (RE and DQS)<br />
• On-die termination<br />
• External V REFQ<br />
• Reduced signaling (SSTL_18)<br />
• Warm-up cycles<br />
Santa Clara, CA August 2011<br />
4
ONFI 3.0 3 0 NV-DDR2 NV DDR2<br />
• <strong>400</strong> <strong>MT</strong>/s DDR interface<br />
• Superset of Toggle Mode 2.0<br />
• Differential signaling (RE and DQS)<br />
• On-die termination<br />
• External V REFQ<br />
• Reduced signaling (SSTL_18)<br />
• Warm-up cycles<br />
• Matrix on-die termination<br />
• Volume addressing<br />
Santa Clara, CA August 2011<br />
5
Benefits of Termination<br />
Santa Clara, CA August 2011 6
RttPU<br />
DQ<br />
RttPD<br />
Santa Clara, CA August 2011<br />
Power Costs of Termination<br />
To achieve R TT of 50 ohms:<br />
R TTPU = 100 ohms<br />
R TTPD = 100 ohms<br />
With 1.8V VCCQ, each DQ draws<br />
~9mA 9mA<br />
For all terminated signals, this<br />
amounts to ~160mW per channel to<br />
achieve 50 ohms termination with<br />
linear termination<br />
7
Matrix Termination vs. Self<br />
TTermination i i<br />
Self Termination<br />
CE0_n<br />
Target LUN<br />
LUN 0<br />
LUN 1<br />
LUN 0<br />
LUN 1<br />
RttPU<br />
DQ<br />
RttPD<br />
Data ata<br />
Channel<br />
• Target only termination available<br />
• If supported for reads, output drivers cannot be<br />
used dffor ttermination i ti<br />
Santa Clara, CA August 2011<br />
8
Matrix Termination vs. Self<br />
TTermination i i<br />
Matrix Termination<br />
Target<br />
CE0_n<br />
Target LUN<br />
LUN 0<br />
LUN 1<br />
LUN 0<br />
LUN 1<br />
• Target or non-target termination capable<br />
• Supported for reads and writes<br />
Santa Clara, CA August 2011<br />
RttPU<br />
DQ<br />
RttPD<br />
Data ata<br />
Channel<br />
9
Matrix Termination vs. Self<br />
TTermination i i<br />
Matrix Termination<br />
Non-Target<br />
CE0_n<br />
Target LUN<br />
LUN 0<br />
LUN 1<br />
LUN 0<br />
LUN 1<br />
RttPU<br />
DQ<br />
RttPD<br />
Data ata<br />
Channel<br />
• Multiple LUNs can be terminators, providing a<br />
flexible array y of termination values and locations<br />
Santa Clara, CA August 2011<br />
10
Timing Budget Considerations<br />
• With heavy loading and long trace lengths lengths,<br />
slew rates can become very slow.<br />
Santa Clara, CA August 2011<br />
11
Santa Clara, CA August 2011<br />
Topology Considerations<br />
12
Revisit <strong>Micron</strong> <strong>Micron</strong>’s s FMS 2011 presentations at:<br />
www.micron.com/fms<br />
©2011 <strong>Micron</strong> Technology Inc All rights reserved Products are warranted only to meet <strong>Micron</strong>’s production data sheet specifications Information products<br />
©2011 <strong>Micron</strong> Technology, Inc. All rights reserved. Products are warranted only to meet <strong>Micron</strong> s production data sheet specifications. Information, products<br />
and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Dates are estimates only.<br />
Drawings not to scale. <strong>Micron</strong>, Real SSD, and the <strong>Micron</strong> logo are trademarks of <strong>Micron</strong> Technology, Inc. All other trademarks are the property of their respective<br />
owners.
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