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D<br />
8 7 6<br />
5 4 3 2 1<br />
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.<br />
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.<br />
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.<br />
<strong>K24</strong> <strong>MLB</strong> <strong>SCHEMATIC</strong><br />
PVT RELEASE<br />
5/6/2009<br />
REV ZONE ECN<br />
DESCRIPTION OF CHANGE<br />
CK<br />
APPD<br />
DATE<br />
A 0000713283 <strong>K24</strong> <strong>MLB</strong> PVT RELEASE 5/6/09<br />
ENG<br />
APPD<br />
?<br />
DATE<br />
D<br />
C<br />
B<br />
Page (.csa) Contents<br />
Sync<br />
1<br />
1 Table of Contents<br />
T17_<strong>MLB</strong><br />
2<br />
2 System Block Diagram<br />
T18_<strong>MLB</strong><br />
3<br />
3 Power Block Diagram<br />
DRAGON<br />
4<br />
4 BOM Configuration<br />
M97_<strong>MLB</strong><br />
5<br />
5 Revision History<br />
M97_<strong>MLB</strong><br />
7<br />
6 FUNC TEST<br />
M97_<strong>MLB</strong><br />
8<br />
7 Power Aliases<br />
BEN<br />
9<br />
8 SIGNAL ALIAS<br />
M97_<strong>MLB</strong><br />
10<br />
9 CPU FSB<br />
T18_<strong>MLB</strong><br />
11<br />
10 CPU Power & Ground<br />
T18_<strong>MLB</strong><br />
12<br />
11 CPU Decoupling<br />
RAYMOND<br />
13<br />
12<br />
eXtended Debug Port(MiniXDP)<br />
K19_<strong>MLB</strong><br />
12/12/2007<br />
03/13/2008<br />
04/21/2008<br />
12/12/2007<br />
12/12/2007<br />
03/31/2008<br />
11/07/2008<br />
14<br />
04/04/2008<br />
13 MCP CPU Interface<br />
T18_<strong>MLB</strong><br />
15<br />
04/04/2008<br />
14 MCP Memory Interface<br />
T18_<strong>MLB</strong><br />
16<br />
04/04/2008<br />
15 MCP Memory Misc<br />
T18_<strong>MLB</strong><br />
17<br />
04/04/2008<br />
16 MCP PCIe Interfaces<br />
T18_<strong>MLB</strong><br />
18<br />
04/04/2008<br />
17 MCP Ethernet & Graphics<br />
T18_<strong>MLB</strong><br />
19<br />
04/04/2008<br />
18 MCP PCI & LPC<br />
T18_<strong>MLB</strong><br />
20<br />
04/04/2008<br />
19 MCP SATA & USB<br />
T18_<strong>MLB</strong><br />
21<br />
06/26/2008<br />
20 MCP HDA & MISC<br />
T18_<strong>MLB</strong><br />
22<br />
04/04/2008<br />
21 MCP Power & Ground<br />
T18_<strong>MLB</strong><br />
25<br />
04/04/2008<br />
22 MCP Standard Decoupling<br />
T18_<strong>MLB</strong><br />
26<br />
12/12/2007<br />
23 MCP Graphics Support<br />
T18_<strong>MLB</strong><br />
28<br />
04/05/2008<br />
24 SB Misc<br />
RAYMOND<br />
29<br />
03/31/2008<br />
25 FSB/DDR3 Vref Margining<br />
BEN<br />
31<br />
06/30/2008<br />
26 DDR3 SO-DIMM Connector A<br />
BEN<br />
32<br />
05/09/2008<br />
27 DDR3 SO-DIMM Connector B<br />
BEN<br />
33<br />
04/04/2008<br />
28 DDR3 Support<br />
T18_<strong>MLB</strong><br />
34<br />
04/22/2008<br />
29 Right Clutch Connector<br />
YITE<br />
35<br />
01/30/2009<br />
30 SECUREDIGITAL CARD READER<br />
VEMURI<br />
37<br />
05/23/2008<br />
31 Ethernet PHY (RTL8211CL)<br />
SUMA<br />
38<br />
07/01/2008<br />
32 Ethernet & AirPort Support<br />
SUMA<br />
39<br />
04/04/2008<br />
33 ETHERNET CONNECTOR<br />
SUMA<br />
41<br />
11/02/2008<br />
34 FireWire LLC/PHY (FW643)<br />
K19_<strong>MLB</strong><br />
42<br />
12/22/2008<br />
35 FireWire Port Power<br />
YUN_K19_<strong>MLB</strong><br />
(.csa)<br />
Page<br />
Contents<br />
Date<br />
Sync Page (.csa)<br />
Contents<br />
Date<br />
Sync<br />
Date<br />
08/22/2007<br />
36<br />
37<br />
38<br />
39<br />
40<br />
41<br />
42<br />
43<br />
44<br />
45<br />
46<br />
47<br />
48<br />
49<br />
50<br />
51<br />
52<br />
53<br />
54<br />
55<br />
56<br />
57<br />
58<br />
59<br />
60<br />
61<br />
62<br />
63<br />
64<br />
65<br />
66<br />
67<br />
68<br />
69<br />
70<br />
43<br />
45<br />
46<br />
48<br />
49<br />
50<br />
51<br />
52<br />
53<br />
54<br />
55<br />
56<br />
57<br />
58<br />
59<br />
61<br />
62<br />
63<br />
65<br />
66<br />
67<br />
68<br />
69<br />
70<br />
72<br />
73<br />
74<br />
75<br />
76<br />
77<br />
78<br />
79<br />
90<br />
93<br />
94<br />
FireWire Ports<br />
SATA Connectors<br />
External USB Connectors<br />
Front Flex Support<br />
SMC<br />
SMC Support<br />
LPC+SPI Debug Connector<br />
<strong>K24</strong> SMBUS CONNECTIONS<br />
VOLTAGE SENSING<br />
Current Sensing<br />
Thermal Sensors<br />
Fan<br />
WELLSPRING 1<br />
WELLSPRING 2<br />
SMS<br />
SPI ROM<br />
AUDIO: CODEC/REGULATOR<br />
AUDIO: LINE INPUT FILTER<br />
AUDIO: HEADPHONE FILTER<br />
AUDI0: SPEAKER AMP<br />
AUDIO: JACK<br />
AUDIO: JACK TRANSLATORS<br />
DC-In & Battery Connectors<br />
PBUS Supply/Battery Charger<br />
5V/3.3V SUPPLY<br />
1.5V/0.75V DDR3 SUPPLY<br />
IMVP6 CPU VCore Regulator<br />
MCP CORE REGULATOR<br />
CPU VTT(1.05V) SUPPLY<br />
MISC POWER SUPPLIES<br />
POWER SEQUENCING<br />
POWER FETS<br />
LVDS CONNECTOR<br />
DISPLAYPORT SUPPORT<br />
DisplayPort Connector<br />
K19_<strong>MLB</strong><br />
K19_<strong>MLB</strong><br />
YUAN.MA<br />
YUAN.MA<br />
T18_<strong>MLB</strong><br />
YUAN.MA<br />
CHANGZHANG<br />
BEN<br />
YUNWU<br />
YUNWU<br />
YUNWU<br />
CHANGZHANG<br />
YUAN.MA<br />
YUAN.MA<br />
YUNWU<br />
CHANGZHANG<br />
AUDIO<br />
AUDIO<br />
AUDIO<br />
AUDIO<br />
AUDIO<br />
AUDIO<br />
YUNWU<br />
RAYMOND<br />
RAYMOND<br />
RAYMOND<br />
RAYMOND<br />
K19_<strong>MLB</strong><br />
RAYMOND<br />
RAYMOND<br />
YUAN.MA<br />
YUAN.MA<br />
NMARTIN<br />
AMASON<br />
AMASON<br />
11/02/2008<br />
12/04/2008<br />
01/18/2008<br />
05/28/2008<br />
06/26/2008<br />
05/28/2008<br />
05/09/2008<br />
04/21/2008<br />
02/04/2008<br />
12/17/2008<br />
03/20/2008<br />
01/18/2008<br />
04/22/2008<br />
05/09/2008<br />
06/26/2008<br />
05/02/2008<br />
03/04/2009<br />
01/31/2009<br />
02/03/2009<br />
12/18/2008<br />
03/20/2009<br />
03/20/2009<br />
12/11/2008<br />
01/31/2008<br />
02/08/2008<br />
01/31/2008<br />
01/31/2008<br />
12/10/2008<br />
02/08/2008<br />
01/23/2008<br />
12/11/2008<br />
12/11/2008<br />
04/04/2008<br />
04/18/2008<br />
06/30/2008<br />
97<br />
71 LCD BACKLIGHT DRIVER<br />
98<br />
72 LCD Backlight Support<br />
100<br />
73 CPU/FSB Constraints<br />
101<br />
74 Memory Constraints<br />
102<br />
75 MCP Constraints 1<br />
103<br />
76 MCP Constraints 2<br />
104<br />
77 Ethernet Constraints<br />
105<br />
78 FireWire Constraints<br />
106<br />
79 SMC Constraints<br />
107<br />
80 <strong>K24</strong> SPECIAL CONSTRAINTS<br />
109<br />
81 <strong>K24</strong> RULE DEFINITIONS<br />
KIRAN<br />
YITE<br />
T18_<strong>MLB</strong><br />
T18_<strong>MLB</strong><br />
T18_<strong>MLB</strong><br />
T18_<strong>MLB</strong><br />
T18_<strong>MLB</strong><br />
K19_<strong>MLB</strong><br />
T18_<strong>MLB</strong><br />
M97_<strong>MLB</strong><br />
M97_<strong>MLB</strong><br />
12/05/2008<br />
06/30/2008<br />
01/04/2008<br />
01/04/2008<br />
01/04/2008<br />
12/14/2007<br />
03/19/2008<br />
12/01/2008<br />
01/04/2008<br />
C<br />
B<br />
A<br />
Schematic / PCB #’s<br />
PART NUMBER<br />
QTY<br />
DESCRIPTION REFERENCE DES CRITICAL BOM OPTION<br />
051-7898 1 SCHEM,<strong>MLB</strong>,<strong>K24</strong><br />
SCH<br />
820-2530 1<br />
PCBF,<strong>MLB</strong>,<strong>K24</strong><br />
PCB<br />
CRITICAL<br />
CRITICAL<br />
DIMENSIONS ARE IN MILLIMETERS<br />
THIRD ANGLE PROJECTION<br />
DESIGNER<br />
APPLE INC.<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
8 7 6 5 4 3 2 1<br />
XX<br />
X.XX<br />
X.XXX<br />
ANGLES<br />
DO NOT SCALE DRAWING<br />
DRAFTER<br />
ENG APPD<br />
QA APPD<br />
RELEASE<br />
METRIC<br />
MATERIAL/FINISH<br />
NOTED AS<br />
APPLICABLE<br />
DESIGN CK<br />
MFG APPD<br />
SCALE<br />
NONE<br />
SIZE<br />
D<br />
TITLE<br />
DRAWING NUMBER<br />
SCHEM,<strong>MLB</strong>,<strong>K24</strong><br />
051-7898<br />
SHT<br />
REV.<br />
1<br />
OF<br />
A<br />
81<br />
A
8 7 6 5 4 3 2 1<br />
U1000<br />
INTEL CPU<br />
2.X OR 3.X GHZ<br />
PENRYN<br />
U1300<br />
XDP CONN<br />
PG 12<br />
PG 9<br />
D<br />
FSB<br />
64-Bit<br />
800/1067/1333 MHz<br />
J6950<br />
D<br />
PG 13<br />
DC/BATT<br />
POWER SUPPLY<br />
J2900<br />
PG 60<br />
GPIOs<br />
FSB INTERFACE<br />
MAIN<br />
MEMORY<br />
PG 14<br />
2 UDIMMs<br />
DDR2-800MHZ<br />
DDR3-1067/1333MHZ<br />
DIMM<br />
U4900<br />
PG 25,26<br />
TEMP SENSOR<br />
J4510<br />
SATA<br />
Conn<br />
1.05V/3GHZ.<br />
CLK<br />
SYNTH<br />
Misc<br />
PG 24<br />
SPI<br />
PG 20<br />
U6100<br />
SPI<br />
Boot ROM<br />
PG 52<br />
PG 41<br />
POWER SENSE<br />
PG 45<br />
J5650,5600,5610,5611,5660,5720,5730,5750<br />
FAN CONN AND CONTROL<br />
PG 48,49<br />
C<br />
J4520<br />
HD<br />
SATA<br />
Conn<br />
ODD<br />
PG 38<br />
PG 38<br />
1.05V/3GHZ.<br />
SATA<br />
PG 19<br />
NVIDIA<br />
MCP79<br />
U1400<br />
LPC<br />
PG 18<br />
J4900<br />
B,0<br />
BSB<br />
SMC<br />
PG 41<br />
ADC<br />
Fan<br />
Ser<br />
Prt<br />
J5100<br />
LPC Conn<br />
Port80,serial<br />
PG 43<br />
C<br />
J9000<br />
LVDS<br />
PWR<br />
CONN<br />
LVDS OUT<br />
CTRL<br />
PG 71<br />
RGB OUT<br />
J3500<br />
J4720<br />
J4700<br />
J4710<br />
J4710<br />
J3900,4635,4655<br />
B<br />
J9400<br />
DISPLAY PORT<br />
CONN<br />
J4310<br />
PG 71<br />
FIREWIRE PORT<br />
FW643<br />
CONN<br />
PG 34<br />
PG 34<br />
DP OUT<br />
HDMI OUT<br />
DVI OUT<br />
TMDS OUT<br />
PG 17<br />
PG 16<br />
PCI-E<br />
UP TO 20 LANES3<br />
USB<br />
PG 19<br />
(UP TO 12 DEVICES)<br />
SMB<br />
PG 20<br />
0 1 2 3 4 5 6 7 11<br />
SD CARD READER<br />
PG 30<br />
Bluetooth<br />
PG 40<br />
TRACKPAD/<br />
KEYBOARD<br />
PG 40<br />
SMB<br />
IR<br />
PG 40<br />
CAMERA<br />
PG 40<br />
EXTERNAL<br />
USB<br />
Connectors<br />
PG 39<br />
B<br />
PG 34<br />
CONN<br />
RGMII<br />
PG 17<br />
PCI<br />
(UP TO FOUR PORTS)<br />
PG 18<br />
HDA<br />
PG 20<br />
DIMM’s<br />
PG 44<br />
J3400<br />
Mini PCI-E<br />
AirPort<br />
PG 28<br />
U6200<br />
Audio<br />
Codec<br />
PG 53<br />
A<br />
U3700<br />
GB<br />
E-NET<br />
RTL8211CL<br />
PG 31<br />
U6301<br />
Line In<br />
Amp<br />
PG 54<br />
U6400<br />
HEADPHONE<br />
Amp<br />
PG 55<br />
U6500<br />
Line Out<br />
Amp<br />
PG 56<br />
U6600,6605,6610,6620<br />
Speaker<br />
Amps<br />
PG 57<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
System Block Diagram<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
SYNC_DATE=12/12/2007<br />
A<br />
U3900<br />
II NOT TO REPRODUCE OR COPY IT<br />
E-NET<br />
Conn<br />
PG 33<br />
J6800,6801,6802,6803<br />
Audio<br />
Conns<br />
PG 56<br />
APPLE INC.<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
2<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
8 7 6 5 4 3 2 1
D<br />
C<br />
B<br />
3S2P<br />
(9 TO 12.6V)<br />
15-1<br />
8 7 6 5 4 3 2 1<br />
F6905<br />
6A FUSE<br />
AC DCIN(16.5V)<br />
ADAPTER<br />
IN<br />
PCI_RESET0#<br />
J6950<br />
MCP79<br />
PM_SLP_S4_L<br />
11<br />
PPBUS_G3H<br />
U5403<br />
SMC_BATT_ISENSE<br />
15<br />
SLP_S3#<br />
11-3<br />
U4900 04<br />
P5VRTS0_EN_L<br />
U1400 RC<br />
DDRREG_EN<br />
SMC_PM_G2_EN<br />
P60<br />
DELAY<br />
(S5)<br />
Q7800 05<br />
P3V3S5_EN_L<br />
15<br />
Q3801<br />
PM_SLP_S3_L<br />
BATT_POS_F<br />
11-1<br />
11-2<br />
RC<br />
DELAY<br />
PM_ENET_EN_L<br />
16<br />
01<br />
Q7050<br />
ENABLES<br />
P3V3S3_EN<br />
CHGR_EN<br />
(S5)<br />
VOUT<br />
PBUS SUPPLY/<br />
BATTERY CHARGER<br />
CHGR_BGATE<br />
P5VLTS3_EN<br />
PP18V5_DCIN_CONN<br />
VIN<br />
ISL6258A<br />
U7000<br />
PPVBAT_G3H_CHGR_OUT<br />
SMC<br />
BKLT_EN<br />
P16<br />
<strong>K24</strong> POWER SYSTEM ARCHITECTURE<br />
7A FUSE<br />
PPVBAT_G3H_CHGR_REG<br />
02<br />
01<br />
A<br />
VIN<br />
LP8543<br />
U9701<br />
ENA<br />
VOUT<br />
D6905<br />
D6905<br />
RC<br />
DELAY<br />
F7000<br />
02<br />
IMVP_VR_ON<br />
25<br />
06<br />
SMC_PM_G2_EN<br />
PPVOUT_S0_LCDBKLT<br />
PPVIN_G3H_P3V42G3H<br />
PPBUS_G3H<br />
CPU VCORE<br />
VOUT<br />
VIN<br />
ISL9504B<br />
VR_ON<br />
P1V05_S5_EN<br />
PGOOD<br />
U7400<br />
VIN<br />
EN1<br />
EN2<br />
02<br />
5V PP5V_S3_REG<br />
(RT) VOUT1<br />
(4A MAX CURRENT)<br />
PP3V3_S5_REG<br />
VOUT2<br />
3.3V (4A MAX CURRENT)<br />
TPS51125<br />
U7200<br />
PGOOD1,2<br />
PBUS_VSENSE<br />
CPUVTTS0_EN<br />
(S0)<br />
CPUVTTS0_PGOOD<br />
06<br />
P1V05ENET_EN 1.05V SO<br />
PP1V05_ENET_FET<br />
CPU<br />
FETS<br />
22<br />
(Q3841)<br />
4.5V AUDIO<br />
PWRGOOD<br />
1.05V (S5)<br />
VIN TPS7174S<br />
PP4V5_AUDIO_ANALOG<br />
U6200<br />
EN<br />
VOUT<br />
RESET*<br />
ISL8009<br />
PP1V05_S5_REG<br />
U1000<br />
U7750 VOUT<br />
VREG3<br />
P5V3V3_PGOOD<br />
V<br />
02<br />
Q5315<br />
ENABLE<br />
3.425V G3HOT<br />
LT3470<br />
U6990<br />
23 R5492<br />
PPBUS_G3H_CPU_ISNS_R<br />
PPBUS_G3H_CPU_ISNS<br />
V<br />
02<br />
EN_PSV<br />
VR_PWRGOOD_DELAY<br />
08<br />
VIN<br />
VOUT<br />
VOUT<br />
CPUVTT<br />
(1.05V)<br />
TPS51117<br />
U7600<br />
PGOOD<br />
SMC_CPU_ISENSE<br />
SMC_CPU_VSENSE<br />
28<br />
Q7910<br />
Q7930<br />
Q3810<br />
PP3V42_G3H_REG<br />
03 SMC PWRGD 04<br />
RN5VD30A-F<br />
PP5V_S0_CPUVTTS0<br />
PP1V05_S0<br />
(8A MAX CURRENT)<br />
PPVCORE_S0_CPU<br />
(44A MAX CURRENT)<br />
P3V3S3_EN<br />
P3V3S0_EN<br />
P3V3_ENET_FET<br />
26<br />
PP3V3_S0_FET<br />
U5000<br />
18<br />
PP5V_S3_REG<br />
PP5V_S3<br />
PP3V3_S5<br />
PP3V3_S3_FET<br />
17<br />
07<br />
13<br />
ALL_SYS_PWRGD<br />
09<br />
24<br />
RSMRST_PWRGD<br />
SMC_ONOFF_L<br />
05<br />
MCP79<br />
PWRBTN*<br />
PLTRST*<br />
31<br />
LPC_RESET_L<br />
32<br />
PWRGD(P12) 99ms DLY<br />
IMVP_VR_ON<br />
IMVP_VR_ON(P16)<br />
25<br />
RSMRST_IN(P13)<br />
PLT_RST*<br />
PWR_BUTTON(P90)<br />
PM_PWRBTN_L<br />
P17(BTN_OUT)<br />
RST*<br />
06-1<br />
RSMRST*<br />
MCP_PS_PWRGD<br />
PS_PWRGD<br />
CPU_PWRGD<br />
29<br />
CPUPWRGD(GPIO49)<br />
30<br />
U2850<br />
CPU_RESET#<br />
U1400<br />
Q7940<br />
PP5V_S0_FET<br />
P5VS0_EN<br />
SMC<br />
10<br />
RSMRST_OUT(P15) PM_RSMRST_L<br />
FSB_CPURST_L<br />
SMC_RESET_L<br />
D<br />
C<br />
B<br />
A<br />
RC<br />
DELAY<br />
RC<br />
DELAY<br />
RC<br />
DELAY<br />
RC<br />
DELAY<br />
P1V8S0_EN<br />
MCPDDR_EN<br />
CPUVTTS0_EN<br />
MCPCORES0_EN<br />
PM_SLP_S3_L<br />
16-3<br />
16-2<br />
16-3<br />
16-4<br />
Q3802<br />
WOL_EN<br />
SMC_ADAPTER_EN<br />
P1V05S0_EN<br />
(S0)<br />
P3V3S0_EN<br />
(S0)<br />
PBUSVSENS_EN<br />
(S0)<br />
P5VRTS0_EN_L<br />
(S0)<br />
04-1<br />
16-2<br />
16-2<br />
16-2<br />
16-1<br />
VIN<br />
02<br />
=DDRREG_EN 1.5V<br />
S5<br />
VOUT1<br />
=DDTVTT_EN 14<br />
S3 0.75V<br />
TPS51116<br />
U7300<br />
VOUT2<br />
MCPCORES0_EN<br />
02<br />
S3 TO S0<br />
FETS<br />
(Q7901 & Q7971)<br />
EN2<br />
EN1<br />
MCP_CORE<br />
VIN<br />
ISL6236<br />
U7500<br />
VOUT2<br />
5V (LT)<br />
VOUT1<br />
PP1V5_S0_FET<br />
PP1V5_S3_REG<br />
(12A MAX CURRENT)<br />
PP0V75_S0_REG<br />
(1A MAX CURRENT)<br />
20<br />
PPVCORE_S0_MCP_REG_R<br />
(25A MAX CURRENT)<br />
PP1V5_S0<br />
21<br />
R7572<br />
PPVCORE_S0_MCP<br />
P3V3ENET_EN_L<br />
1.8V LDO<br />
TPS62202<br />
U7760<br />
PP1V8_S0_REG<br />
19-1<br />
PP3V3_S0<br />
PP1V5_S0<br />
PP1V05_S0<br />
P5V_LT_S3_PGOOD<br />
S0PGOOD_PWROK<br />
V1<br />
V2<br />
V3<br />
MCPCORESO_PGOOD<br />
CPUVTTS0_PGOOD<br />
RST*<br />
LTC2909<br />
U7870<br />
P5V3V3_PGOOD<br />
SLP_S5_L<br />
SLP_S4_L<br />
SLP_S3_L<br />
SLP_S5_L(P95)<br />
SLP_S4_L(P94)<br />
SLP_S3_L(P93)<br />
APPLE INC.<br />
U4900<br />
Power Block Diagram<br />
SYNC_MASTER=DRAGON<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
SYNC_DATE=03/13/2008<br />
051-7898<br />
3<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
A<br />
8 7 6 5 4 3 2 1
TABLE_ALT_HEAD<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_BOMGROUP_HEAD<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_HEAD<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
8 7 6 5 4 3 2 1<br />
BOM Variants<br />
BOM NUMBER<br />
BOM NAME<br />
BOM OPTIONS<br />
Bar Code Labels / EEE #’s<br />
PART NUMBER<br />
QTY<br />
DESCRIPTION REFERENCE DES CRITICAL BOM OPTION<br />
630-9923<br />
PCBA,<strong>MLB</strong>,BETTER,<strong>K24</strong><br />
<strong>K24</strong>_COMMON,CPU_2_26GHZ,EEE_6GC,KB_BL<br />
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM<br />
[EEE:6G4] CRITICAL<br />
EEE_6G4<br />
630-9924<br />
PCBA,<strong>MLB</strong>,BEST,<strong>K24</strong><br />
<strong>K24</strong>_COMMON,CPU_2_53GHZ,EEE_6GD,KB_BL<br />
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:6GC] CRITICAL<br />
EEE_6GC<br />
085-0741 <strong>K24</strong> <strong>MLB</strong> DEVELOPMENT BOM<br />
<strong>K24</strong>_DEVEL_PVT<br />
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:6GD] CRITICAL<br />
EEE_6GD<br />
D<br />
BOM Groups<br />
BOM GROUP<br />
BOM OPTIONS<br />
D<br />
<strong>K24</strong>_COMMON<br />
COMMON,ALTERNATE,<strong>K24</strong>_MCP,<strong>K24</strong>_MISC,<strong>K24</strong>_DEBUG_PVT,<strong>K24</strong>_PROGPARTS<br />
<strong>K24</strong>_MCP<br />
<strong>K24</strong>_MISC<br />
<strong>K24</strong>_PROGPARTS<br />
<strong>K24</strong>_DEBUG_ENG<br />
MCP_B03,BOOT_MODE_USER,MCPSEQ_SMC<br />
ONEWIRE_PU,DP_ESD,MIKEY,BKLT_PROD,SUPERCAP_NO,LDO_NO<br />
BOOTROM_PROG,SMC_PROG,IR_PROG,WELLSPRING_PROG<br />
DEVEL_BOM,SMC_DEBUG_YES,XDP<br />
<strong>K24</strong> BOARD STACK-UP<br />
C<br />
<strong>K24</strong>_DEBUG_PVT<br />
<strong>K24</strong>_DEBUG_PROD<br />
DEVEL_BOM,BMON_PROD,SMC_DEBUG_YES,XDP,NO_VREFMRGN<br />
BMON_PROD,SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN<br />
<strong>K24</strong>_DEVEL_ENG<br />
BMON_ENG,XDP_CONN,LPCPLUS,VREFMRGN,FWPHY_WAKE_YES<br />
<strong>K24</strong>_DEVEL_PVT<br />
LPCPLUS<br />
Module Parts<br />
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION<br />
337S3646<br />
1<br />
PDC,SLG8E,PRQ,2.0,25W,1066,M0,3M,BGA<br />
U1000<br />
CRITICAL<br />
CPU_2_0GHZ<br />
337S3704<br />
1<br />
PDC,SLGE2,PRQ,2.26,25W,1066,R0,3M,BGA<br />
U1000<br />
CRITICAL<br />
CPU_2_26GHZ<br />
337S3639<br />
1<br />
PDC,SLB4N,PRQ,2.4,25W,1066,M0,3M,BGA<br />
U1000<br />
CRITICAL<br />
CPU_2_4GHZ<br />
337S3756<br />
1 PDC,SLGFG,PRQ,2.53,25W,1066,R0,3M,BGA<br />
U1000<br />
CRITICAL<br />
CPU_2_53GHZ<br />
337S3761<br />
1<br />
PDC,SLGLA,PRQ,2.66,25W,1066,E0,3M,BGA<br />
U1000<br />
CRITICAL<br />
CPU_2_66GHZ<br />
338S0710 1<br />
IC,GMCP,MCP79,35X35MM,BGA1437,B03<br />
U1400<br />
CRITICAL<br />
MCP_B03<br />
Programmable Parts<br />
338S0563<br />
1<br />
IC,SMC,HS8/2117,9X9MM,TLP,HF<br />
U4900<br />
CRITICAL<br />
SMC_BLANK<br />
341S2445<br />
1<br />
IC,SMC,<strong>K24</strong><br />
U4900<br />
CRITICAL<br />
SMC_PROG<br />
335S0610<br />
1<br />
IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP<br />
U6100<br />
CRITICAL<br />
BOOTROM_BLANK<br />
341S2441<br />
1<br />
IC,PRGRM,EFI BOOTROM,UNLOCK,<strong>K24</strong><br />
U6100<br />
CRITICAL<br />
BOOTROM_PROG<br />
338S0375<br />
1 IC,CY7C63833,ENCORE II,USB CONTROLLER<br />
U4800<br />
CRITICAL<br />
IR_BLANK<br />
Top<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10<br />
11<br />
BOTTOM<br />
SIGNAL<br />
GROUND<br />
SIGNAL(High Speed)<br />
SIGNAL(High Speed)<br />
GROUND<br />
POWER<br />
POWER<br />
GROUND<br />
SIGNAL(High Speed)<br />
SIGNAL(High Speed)<br />
GROUND<br />
SIGNAL<br />
C<br />
341S2093<br />
1<br />
IC,IR CONTROLLER,M97<br />
U4800<br />
CRITICAL<br />
IR_PROG<br />
337S2983<br />
1 IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794<br />
U5701<br />
CRITICAL<br />
WELLSPRING_BLANK<br />
341S2503<br />
1<br />
IC,PRGRM,WELLSPRING CONTROLLER<br />
U5701<br />
CRITICAL<br />
WELLSPRING_PROG<br />
LOCKED BOOTROM APN IS 341S2443<br />
Alternate Parts<br />
B<br />
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:<br />
PART NUMBER<br />
152S0778<br />
152S0796<br />
152S0693<br />
152S0685<br />
ALL<br />
ALL<br />
CYNTEC AS ALTERNATE<br />
CYNTEC AS ALTERNATE<br />
B<br />
157S0058<br />
157S0055<br />
ALL<br />
DELTA AS ALTERNATE<br />
104S0018<br />
104S0023<br />
ALL<br />
DALE/VISHAY AS ALTERNATE<br />
128S0093<br />
128S0218<br />
ALL<br />
KEMET AS ALTERNATE<br />
152S0874<br />
152S0516<br />
ALL<br />
MAGLAYERS AS ALTERNATE<br />
152S0847<br />
152S0586<br />
ALL<br />
MAGLAYERS AS ALTERNATE<br />
516-0213<br />
516-0201<br />
ALL<br />
MOLEX AS ALTERNATE<br />
516S0709<br />
516S0706<br />
ALL<br />
MOLEX AS ALTERNATE<br />
152S1025<br />
152S1024<br />
ALL<br />
TOKO AS ALTERNATE<br />
A<br />
SYNC_MASTER=M97_<strong>MLB</strong><br />
BOM Configuration<br />
NOTICE OF PROPRIETARY PROPERTY<br />
A<br />
DEVELOPMENT BOM<br />
PART NUMBER<br />
QTY<br />
DESCRIPTION REFERENCE DES CRITICAL BOM OPTION<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
085-0741 1<br />
<strong>K24</strong> <strong>MLB</strong> DEVELOPMENT BOM<br />
DEVEL<br />
CRITICAL<br />
DEVEL_BOM<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
4<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
8 7 6 5 4 3 2 1
Revision History<br />
8 7 6 5 4 3 2 1<br />
D<br />
D<br />
C<br />
C<br />
B<br />
B<br />
A<br />
SYNC_MASTER=M97_<strong>MLB</strong><br />
Revision History<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
A<br />
NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.<br />
8 7 6 5 4 3 2 1<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
5<br />
OF<br />
REV.<br />
81<br />
4.7.0
8 7 6 5 4 3 2 1<br />
Functional Test Points<br />
D<br />
C<br />
B<br />
A<br />
I12<br />
I15<br />
I16<br />
I238<br />
I237<br />
I239<br />
I227<br />
I226<br />
I228<br />
I230<br />
I229<br />
I231<br />
I232<br />
I233<br />
I259<br />
I258<br />
I260<br />
I245<br />
I262<br />
I261<br />
I256<br />
I257<br />
I255<br />
I252<br />
I253<br />
I254<br />
I250<br />
I251<br />
I313<br />
I246<br />
I247<br />
I248<br />
I249<br />
I395<br />
I264<br />
I268<br />
I269<br />
I267<br />
I265<br />
I266<br />
I319<br />
I314<br />
I315<br />
I318<br />
I317<br />
I307<br />
I309<br />
I311<br />
I322<br />
I321<br />
I320<br />
I305<br />
Fan Connectors<br />
TRUE PP5V_S0<br />
TRUE FAN_RT_PWM<br />
TRUE FAN_RT_TACH<br />
MIC FUNC_TEST<br />
TRUE<br />
TRUE<br />
TRUE<br />
(NEED TO ADD 3 GND TP)<br />
BI_MIC_LO<br />
BI_MIC_HI<br />
BI_MIC_SHIELD<br />
SPEAKER FUNC_TEST<br />
TRUE SPKRAMP_L_N_OUT<br />
TRUE SPKRAMP_L_P_OUT<br />
TRUE SPKRAMP_R_N_OUT<br />
TRUE SPKRAMP_R_P_OUT<br />
TRUE SPKRAMP_SUB_N_OUT<br />
TRUE SPKRAMP_SUB_P_OUT<br />
THERMAL FUNC_TEST<br />
TRUE MCPTHMSNS_D2_P<br />
TRUE MCPTHMSNS_D2_N<br />
LVDS FUNC_TEST<br />
TRUE PP3V3_LCDVDD_SW_F<br />
TRUE PP3V3_S0_LCD_F<br />
68C3<br />
TRUE PPVOUT_S0_LCDBKLT<br />
TRUE LVDS_IG_DDC_CLK<br />
TRUE LVDS_IG_DDC_DATA<br />
TRUE LVDS_IG_A_DATA_N<br />
TRUE LVDS_IG_A_DATA_P<br />
TRUE LVDS_IG_A_DATA_N<br />
TRUE LVDS_IG_A_DATA_P<br />
TRUE LVDS_IG_A_DATA_N<br />
TRUE LVDS_IG_A_DATA_P<br />
TRUE LVDS_IG_A_CLK_F_N<br />
TRUE LVDS_IG_A_CLK_F_P<br />
TRUE LED_RETURN_1<br />
TRUE LED_RETURN_2<br />
TRUE LED_RETURN_3<br />
TRUE LED_RETURN_4<br />
TRUE LED_RETURN_5<br />
TRUE LED_RETURN_6<br />
TRUE TP_BKL_SYNC<br />
(NEED TO ADD 5 GND TP)<br />
SATA ODD CONN<br />
TRUE PP5V_SW_ODD (NEED 4 TP)<br />
TRUE SMC_ODD_DETECT<br />
37C7 40B8<br />
TRUE SATA_ODD_D2R_C_P 37C6 75A3<br />
TRUE SATA_ODD_D2R_C_N 37C6 75A3<br />
TRUE SATA_ODD_R2D_P<br />
37C6 75A3<br />
TRUE SATA_ODD_R2D_N<br />
(NEED TO ADD 4 GND TP)<br />
SATA HDD/IR/SIL<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
PP5V_S0_HDD_FLT<br />
SATA_HDD_R2D_P<br />
SATA_HDD_R2D_N<br />
SATA_HDD_D2R_C_P<br />
SATA_HDD_D2R_C_N<br />
SYS_LED_ANODE_R<br />
IR_RX_OUT<br />
PP5V_S3_IR_R<br />
(NEED TO ADD 4 GND TP)<br />
(NEED 3 TP)<br />
6D3 7D5<br />
56C2 57B1<br />
56C2 57B1<br />
55C2 56B2<br />
55B2 56B2<br />
55C2 56B2<br />
6C3 68C2<br />
6C3 68B2 71C1<br />
17B3 68C5<br />
17A3 68C5<br />
17B3 68C2 75B3<br />
17B3 68C2 75B3<br />
17B3 68C2 75B3<br />
17B3 68C2 75B3<br />
17B3 68C2 75B3<br />
68B3 71B1<br />
(NEED 4 TP)<br />
BATT POWER CONN<br />
TRUE SMBUS_SMC_BSA_SCL 6A7 43C5 79D3<br />
TRUE SMBUS_SMC_BSA_SDA 43C5 79D3<br />
TRUE SYS_DETECT_L<br />
58A8<br />
TRUE BATT_POS_F<br />
(NEED 3 TP)<br />
(NEED TO ADD 3 GND TP)<br />
47B4<br />
47C4<br />
56C2 57B1<br />
55A2 56B2<br />
55B2 56B2<br />
55C2 56A2<br />
46B5 80D3<br />
46B5 80D3<br />
17B3 68C2 75B3<br />
68C2 75B3<br />
68C2 75B3<br />
68B3 71B1<br />
68B3 71B1<br />
68B3 71B1<br />
68B3 71B1<br />
68B3 71A1<br />
68C2<br />
6A7 37C6 75A3<br />
6C3 37B6<br />
37A5 75A3<br />
37A5 75A3<br />
37B5 75A3<br />
37B5 75A3<br />
37A7<br />
37A7 39D4<br />
37A7<br />
6C3 37D3<br />
58A7 58B8 59A3<br />
I303<br />
I301<br />
I302<br />
I300<br />
I299<br />
I298<br />
I293<br />
I297<br />
I294<br />
I288<br />
I292<br />
I296<br />
I291<br />
I295<br />
I290<br />
I271<br />
I289<br />
I375<br />
I374<br />
I372<br />
I370<br />
I371<br />
I369<br />
I368<br />
I361<br />
I366<br />
I365<br />
I363<br />
I364<br />
I362<br />
I360<br />
I359<br />
I357<br />
I358<br />
I377<br />
I378<br />
I354<br />
I355<br />
I344<br />
I345<br />
I346<br />
I347<br />
I349<br />
I348<br />
I350<br />
I352<br />
I351<br />
I353<br />
I327<br />
I328<br />
I329<br />
I343<br />
I342<br />
I341<br />
I339<br />
I340<br />
I338<br />
I336<br />
I337<br />
I333<br />
I335<br />
I334<br />
I332<br />
I330<br />
I331<br />
I356<br />
I394<br />
RIGHT CLUTCH CONN<br />
TRUE PP5V_S3_BTCAMERA_F 29C7<br />
TRUE PCIE_MINI_D2R_P 16B6 29C7 75D3<br />
TRUE PCIE_MINI_D2R_N 16B6 29C7 75D3<br />
TRUE PCIE_MINI_R2D_P<br />
29C7 75D3<br />
TRUE PCIE_MINI_R2D_N 29C7 75D3<br />
TRUE PCIE_CLK100M_MINI_CONN_P<br />
TRUE PCIE_CLK100M_MINI_CONN_N<br />
TRUE USB_CAMERA_CONN_P 29B7 76C3<br />
TRUE USB_CAMERA_CONN_N 29B7 76C3<br />
TRUE PP5V_WLAN<br />
(NEED 2 TP)<br />
6C3<br />
29C5<br />
TRUE PCIE_WAKE_L<br />
16B6 29C7<br />
TRUE SMBUS_SMC_A_S3_SCL 6C5 43D2 79D3<br />
TRUE SMBUS_SMC_A_S3_SDA 6C5 43D2 79D3<br />
TRUE CONN_USB2_BT_P<br />
29B7 76C3<br />
TRUE CONN_USB2_BT_N<br />
29B7 76B3<br />
TRUE MINI_CLKREQ_Q_L 29C7<br />
TRUE MINI_RESET_CONN_L 29A7<br />
(NEED TO ADD 6 GND TP)<br />
IPD_FLEX_CONN<br />
TRUE PP3V3_S3_LDO<br />
TRUE PP18V5_S3<br />
TRUE Z2_CS_L<br />
TRUE Z2_DEBUG3<br />
TRUE Z2_MOSI<br />
TRUE Z2_MISO<br />
TRUE Z2_SCLK<br />
TRUE Z2_BOOST_EN<br />
TRUE Z2_HOST_INTN<br />
TRUE Z2_CLKIN<br />
TRUE Z2_KEY_ACT_L<br />
TRUE Z2_RESET<br />
TRUE PSOC_MISO<br />
TRUE PSOC_MOSI<br />
TRUE PSOC_SCLK<br />
TRUE SMBUS_SMC_A_S3_SDA<br />
TRUE SMBUS_SMC_A_S3_SCL<br />
TRUE PSOC_F_CS_L<br />
TRUE PICKB_L<br />
KEYBOARD CONN<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
6C3 49B4 49C3<br />
6C3 49C1 49D3<br />
48C8 49C3<br />
48C8 49C3<br />
48C8 49C3<br />
48C8 49C3<br />
48C8 49C3<br />
49C3 49C5<br />
48D8 49C3<br />
48C6 49C3<br />
48C8 49C1<br />
48C8 49C1<br />
48C8 49C1<br />
48C8 49C1<br />
48C8 49C1<br />
6D5 43D2 79D3<br />
6D5 43D2 79D3<br />
48C8 49C1<br />
48D8 49C1<br />
PP3V3_S3<br />
6D3 7D3<br />
PP3V42_G3H<br />
6A7 6D3 7D1<br />
WS_KBD1<br />
48C6 48D2<br />
WS_KBD2<br />
48C6 48D2<br />
WS_KBD3<br />
48C6 48D2<br />
WS_KBD4<br />
48C6 48D2<br />
WS_KBD5<br />
48C6 48D2<br />
WS_KBD6<br />
48C6 48D2<br />
WS_KBD7<br />
48C6 48D2<br />
WS_KBD8<br />
48C6 48D2<br />
WS_KBD9<br />
48C6 48D2<br />
WS_KBD10<br />
48C6 48D2<br />
WS_KBD11<br />
48C6 48D2<br />
WS_KBD12<br />
48C6 48D2<br />
WS_KBD13<br />
48C6 48D2<br />
WS_KBD14<br />
48C2 48C6<br />
WS_KBD15_CAP<br />
48C2<br />
WS_KBD16_NUM<br />
48C2<br />
WS_KBD17<br />
48C2 48D6<br />
WS_KBD18<br />
48C2 48D7<br />
WS_KBD19<br />
48C2 48D7<br />
WS_KBD20<br />
48C2 48D7<br />
WS_KBD21<br />
48C2 48D7<br />
WS_KBD22<br />
48C2 48D7<br />
WS_KBD23<br />
48C2 48D7<br />
WS_KBD_ONOFF_L<br />
48C2<br />
WS_LEFT_SHIFT_KBD<br />
WS_LEFT_OPTION_KBD<br />
WS_CONTROL_KBD<br />
(NEED TO ADD 1 GND TP)<br />
48B3 48B5 48C2<br />
48B3 48B5 48C2<br />
48B3 48B5 48C2<br />
KBD BACKLIGHT CONN<br />
TRUE KBDLED_ANODE (NEED 2 TP)<br />
TRUE SMC_KDBLED_PRESENT_L<br />
49A4 49A6<br />
(NEED TO ADD 2 GND TP)<br />
49A4<br />
29C7 75D3<br />
29C7 75D3<br />
I287<br />
I285<br />
I284<br />
I280<br />
I281<br />
I282<br />
I376<br />
I283<br />
I279<br />
I278<br />
I270<br />
I379<br />
I273<br />
I274<br />
I275<br />
I276<br />
I272<br />
I393<br />
I392<br />
I391<br />
I390<br />
I389<br />
I388<br />
I387<br />
I386<br />
I385<br />
I383<br />
I382<br />
I381<br />
I380<br />
I312<br />
I304<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
DEBUG VOLTAGE<br />
PPVCORE_S0_CPU<br />
7D7<br />
PPVCORE_S0_MCP<br />
7C7<br />
PP0V75_S0<br />
7C7<br />
PP1V05_S0<br />
7D7<br />
PP1V5_S0<br />
7C6<br />
PP1V8_S0<br />
7B6<br />
PP5V_S0<br />
6D7 7D5<br />
PP3V3_S0<br />
7D5<br />
PP1V5_S3<br />
7D3<br />
PP3V3_S3<br />
6B5 7D3<br />
PP5V_S3<br />
7C3<br />
PP1V1R1V05_S5<br />
7B3<br />
PP3V3_S5<br />
7B3<br />
PP3V42_G3H<br />
PPBUS_G3H<br />
7C1<br />
PP3V3_ENET_PHY<br />
7B5<br />
PP1V2R1V05_ENET 7B5<br />
PP3V3_G3_RTC<br />
PP5V_WLAN<br />
6D5 29C5<br />
PP5V_SW_ODD<br />
6B7 37D3<br />
PP5V_S0_HDD_FLT 6B7 37B6<br />
PP3V3_S5_AVREF_SMC<br />
PP18V5_S3<br />
PP3V3_S3_LDO<br />
PP3V3_LCDVDD_SW_F 6C7 68C2<br />
PPVOUT_S0_LCDBKLT<br />
PP4V5_AUDIO_ANALOG<br />
SMC_PM_G2_EN<br />
PM_SLP_S4_L<br />
PM_SLP_S3_L<br />
(NEED TO ADD 4 GND TP)<br />
DC POWER CONN<br />
TRUE PP18V5_DCIN_FUSE<br />
TRUE ADAPTER_SENSE<br />
(NEED TO ADD 4 GND TP)<br />
6A7 6B5 7D1<br />
20C8 21A5 24D4<br />
40D4 41C6<br />
6C5 49C1 49D3<br />
6C5 49B4 49C3<br />
6C7 68B2 71C1<br />
52A5 52D2 52D7<br />
40D5 60C5 66D8<br />
20C3 40C5 41A2 66C8<br />
20C3 32B7 35A5 40C5 66D5 70D8<br />
(NEED 3 TP)<br />
58D7<br />
58D6<br />
SYNC_MASTER=M97_<strong>MLB</strong><br />
FUNC TEST<br />
NOTICE OF PROPRIETARY PROPERTY<br />
D<br />
C<br />
B<br />
A<br />
I326<br />
I323<br />
I324<br />
I325<br />
I308<br />
BATT SIGNAL CONN<br />
(NEED 3 TP)<br />
TRUE PP3V42_G3H<br />
TRUE SMBUS_SMC_BSA_SCL<br />
TRUE SMBUS_SMC_BSA_SCL<br />
TRUE SMC_BIL_BUTTON_L 40C5 58C4<br />
TRUE SMC_LID_R<br />
58C2<br />
(NEED TO ADD 5 GND TP)<br />
6B5 6D3 7D1<br />
6A7 43C5 79D3<br />
6A7 43C5 79D3<br />
APPLE INC.<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
6<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
"S0,S0M" RAILS<br />
"S3" RAILS<br />
"G3H" RAILS<br />
D<br />
C<br />
B<br />
A<br />
62D1<br />
=PPVCORE_S0_CPU_REG<br />
(CPU VCORE PWR)<br />
64C2<br />
=PPCPUVTT_S0_REG<br />
63C7 63C1 63B8<br />
61C8<br />
(MCP VCORE AFTER SENSE RES)<br />
67D1<br />
22D8 7D7<br />
22D6 7D7<br />
=PP0V75_S0_REG<br />
65B1 22C4<br />
=PPMCPCORE_S0_REG<br />
=PP1V5_S0_FET<br />
65C5<br />
206 mA (A01)<br />
=PP1V05_S0_MCP_PEX_DVDD<br />
206 mA (A01)<br />
127 mA (A01)<br />
=PP1V05_S0_MCP_SATA_DVDD<br />
127 mA (A01)<br />
=PP1V8_S0_REG<br />
=PP1V05_S0_MCP_PLL_UF<br />
22D1 PP1V05_S0_MCP_PEX_AVDD<br />
MAKE_BASE=TRUE<br />
22D2 PP1V05_S0_MCP_SATA_AVDD<br />
MAKE_BASE=TRUE<br />
PPVCORE_S0_CPU<br />
MIN_LINE_WIDTH=0.6 MM<br />
MIN_NECK_WIDTH=0.3 MM<br />
VOLTAGE=1.25V<br />
MAKE_BASE=TRUE<br />
=PPVCORE_S0_CPU<br />
=PPVCORE_S0_CPU_VSENSE<br />
PP1V05_S0<br />
MIN_LINE_WIDTH=0.6 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=1.05V<br />
MAKE_BASE=TRUE<br />
=PP1V05_S0_CPU<br />
=PP1V05_S0_MCP_FSB<br />
=PP1V05_S0_SMC_LS<br />
=PP1V05_S0_MCP_PEX_DVDD<br />
=PP1V05_S0_MCP_AVDD_UF<br />
=PP1V05_S0_MCP_SATA_DVDD<br />
=PP1V05_S0_MCP_HDMI_VDD<br />
=PP1V05_S0_VMON<br />
=PP1V05_S0_MCP_PLL_UF_R<br />
=PP1V05_FW_P1V05FWFET<br />
=PP1V05_FWPWRCTL<br />
PPVCORE_S0_MCP<br />
MIN_LINE_WIDTH=0.6 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=1.05V<br />
MAKE_BASE=TRUE<br />
=PPVCORE_S0_MCP<br />
=PPVCORE_S0_MCP_VSENSE<br />
PP0V75_S0<br />
MIN_LINE_WIDTH=0.4 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=0.75V<br />
MAKE_BASE=TRUE<br />
=PPVTT_S0_VTTCLAMP<br />
=PP0V75_S0_MEM_VTT_A<br />
=PP0V75_S0_MEM_VTT_B<br />
PP1V5_S0<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=1.5V<br />
MAKE_BASE=TRUE<br />
=PP1V5_S0_CPU<br />
=PP1V5_S0_VMON<br />
=PP1V8R1V5_S0_MCP_MEM<br />
=PP1V5_S0_MEM_MCP<br />
=PP1V5_S0_MCP_PLL_VLDO<br />
PP1V8_S0<br />
MIN_LINE_WIDTH=0.5 MM<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=1.8V<br />
MAKE_BASE=TRUE<br />
=PP3V3R1V8_S0_MCP_IFP_VDD<br />
=PP1V8_S0_AUDIO<br />
PP1V05_S0_MCP_PLL_UF<br />
MIN_LINE_WIDTH=0.6 MM<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=1.05V<br />
MAKE_BASE=TRUE<br />
PEX & SATA AVDD/DVDD aliases<br />
6D3<br />
10B5 10D6 11D6<br />
44D8<br />
9D5 10C6 11B6 12D6<br />
7A8 22D8<br />
22D4<br />
6D3<br />
7A8 22D6<br />
17A6 23D7<br />
66A8<br />
65B3<br />
35C6<br />
35B4<br />
13A2 13B7 21D3 22C8<br />
6D3<br />
6D3<br />
67B3<br />
26A4<br />
27A4<br />
44D8<br />
6D3<br />
21D5 22D8<br />
10B6 11B6<br />
66A8<br />
15C3 15C7 22C8<br />
27B3<br />
65B6<br />
6D3<br />
17B6 23D7<br />
52D7<br />
32D2<br />
32B2<br />
67B6<br />
67C6<br />
=PP1V05_S0_MCP_PEX_AVDD0<br />
=PP1V05_S0_MCP_PEX_AVDD1<br />
=PP1V05_S0_MCP_PEX_DVDD0<br />
=PP1V05_S0_MCP_PEX_DVDD1<br />
=PP1V05_S0_MCP_SATA_AVDD0<br />
=PP1V05_S0_MCP_SATA_AVDD1<br />
=PP1V05_S0_MCP_SATA_DVDD0<br />
=PP1V05_S0_MCP_SATA_DVDD1<br />
=PP5V_S0_FET<br />
=PP3V3_S0_FET<br />
=PP3V3_ENET_FET<br />
"ENET" RAILS<br />
=PP1V05_ENET_FET<br />
16B3<br />
16A3<br />
16B6<br />
16A6<br />
19B6<br />
19B6<br />
19B6<br />
19B6<br />
206 mA (A01)<br />
57 mA (A01)<br />
127 mA (A01)<br />
43 mA (A01)<br />
PP5V_S0<br />
MIN_LINE_WIDTH=0.6 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=5V<br />
MAKE_BASE=TRUE<br />
=PP5V_S0_HDD<br />
=PP5V_S0_LPCPLUS<br />
=PP5V_S0_FAN_RT<br />
=PP5V_S0_CPU_IMVP<br />
=PP5V_S0_KBDLED<br />
=PP5V_S0_DP_AUX_MUX<br />
=PP5V_S0_CPUVTTS0<br />
=PP5V_S0_BKL<br />
=PP5V_S0_MCPREG<br />
=PP5V_S0_VMON<br />
PP3V3_S0<br />
MIN_LINE_WIDTH=0.6 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
=PP3V3_S0_XDP<br />
=PP3V3_S0_MCP<br />
=PP3V3_S0_MCP_DAC_UF<br />
=PP3V3_S0_MCP_VPLL_UF<br />
=PP3V3_S0_ODD<br />
=PP3V3_S0_SMBUS_SMC_0_S0<br />
=PP3V3_S0_SMBUS_SMC_B_S0<br />
=PP3V3_S0_SMBUS_MCP_0<br />
=PP3V3_S0_FAN_RT<br />
=PP3V3_S0_AUDIO<br />
=PP3V3_S0_IMVP<br />
=PP3V3_S0_LCD<br />
=PP3V3_S0_MCP_GPIO<br />
=PP3V3_S0_MCP_PLL_UF<br />
=PP3V3R1V5_S0_MCP_HDA<br />
=PP3V3_S0_SMC<br />
=PP3V3_S0_MCPTHMSNS<br />
=PP3V3_S0_CPUTHMSNS<br />
=PP3V3_S0_DPCONN<br />
=PPSPD_S0_MEM_A<br />
=PPSPD_S0_MEM_B<br />
=PP3V3_S0_PWRCTL<br />
=PP3V3_S0_VMON<br />
=PP3V3_S0_CPUVTTISNS<br />
=PP3V3_S0_TPAD<br />
=PP3V3_S0_SMBUS_MCP_1<br />
=PP3V3_S0_P1V8S0<br />
=PP3V3_S0_BKL_VDDIO<br />
=PP3V3_S0_MCPDDRISNS<br />
=PP3V3_S0_MCP_PLL_VLDO<br />
=PP3V3_S0_P3V3FWFET<br />
=PP3V3_S0_FWPWRCTL<br />
=PP3V3_ENET_PHY<br />
=PP1V05_ENET_MCP_RMGT<br />
=PP1V05_ENET_PHY<br />
31D2<br />
6D3 6D7<br />
37B3<br />
42D5<br />
47C5<br />
62D8<br />
49A5<br />
69B6<br />
64C8<br />
71D4<br />
63D4<br />
66B5<br />
6D3<br />
12D6<br />
20C2 21B3 22B8<br />
23D4<br />
23C7<br />
37C7 37D6<br />
43D5<br />
43C3<br />
43D8<br />
47C5<br />
62D8<br />
68C5<br />
17C1 18D1 20A4<br />
22B6<br />
41A1 41D3<br />
46B6<br />
46D6<br />
70B8 70C8<br />
26A8<br />
27A8<br />
66A5<br />
66A8<br />
45C7<br />
49A6<br />
43C8<br />
65D8<br />
71C7<br />
45D8<br />
65C6<br />
35D6<br />
35B1 35D2<br />
PP3V3_ENET_PHY<br />
6C3<br />
MIN_LINE_WIDTH=0.4 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
=PP3V3_ENET_MCP_RMGT 17D3 17D7 22A5 22B6<br />
31D7<br />
PP1V2R1V05_ENET 6C3<br />
MIN_LINE_WIDTH=0.4 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=1.05V<br />
MAKE_BASE=TRUE<br />
=PP1V05_ENET_MCP_PLL_MAC 22A8<br />
17D3 22D6<br />
52A8 52D2 56D8 57B8 57D3<br />
20D3 20D8 22A8<br />
67D6<br />
60B8<br />
61D8 25D3<br />
65A5<br />
60B1<br />
61C1<br />
=PP1V5_S3_REG<br />
=PP3V3_S3_FET<br />
=PP5V_S3_REG<br />
=PPVTT_S3_DDR_BUF<br />
=PP1V05_S5_REG<br />
=PP3V3_S5_REG<br />
PP1V5_S3<br />
MIN_LINE_WIDTH=0.6 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=1.5V<br />
MAKE_BASE=TRUE<br />
=PP1V5_S3_P1V5S0FET<br />
=PP1V5_S3_MEM_A<br />
=PP1V5_S3_MEM_B<br />
=PP1V5_S3_MEMRESET<br />
=PP1V5_S3_HDD<br />
PP3V3_S3<br />
MIN_LINE_WIDTH=0.6 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
=PP3V3_S3_SMBUS_SMC_A_S3<br />
=PP3V3_S3_PDCISENS<br />
=PP3V3_S3_SMBUS_SMC_MGMT<br />
=PP3V3_S3_VREFMRGN<br />
=PP3V3_S3_WLAN<br />
=PP3V3_S3_MCP_GPIO<br />
=PP3V3_S3_TPAD<br />
=PP3V3_S3_SMS<br />
=PP3V3_S3_CARDREADER<br />
PP5V_S3<br />
MIN_LINE_WIDTH=0.6 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=5V<br />
MAKE_BASE=TRUE<br />
=PP5V_S3_EXTUSB<br />
=PP5V_S3_IR<br />
=PP5V_S3_BTCAMERA<br />
=PP5V_S3_VTTCLAMP<br />
=PP5V_S3_MCPDDRFET<br />
=PP5V_S3_SYSLED<br />
=PP5V_S3_TPAD<br />
=PP5V_S3_WLAN<br />
=PP5V_S3_1V5S30V75S0<br />
=PP5V_S3_AUDIO<br />
=PP5V_S3_AUDIO_AMP<br />
=PP5V_S3_P5VS0FET<br />
=PP5V_S3_ODD<br />
PPVTT_S3_DDR_BUF<br />
MIN_LINE_WIDTH=0.3 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=0.75V<br />
MAKE_BASE=TRUE<br />
"S5" RAILS<br />
PP1V1R1V05_S5<br />
MIN_LINE_WIDTH=0.6 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=1.05V<br />
MAKE_BASE=TRUE<br />
=PP1V05_S5_MCP_VDD_AUXC<br />
=PP1V05_ENET_P1V05ENETFET<br />
PP3V3_S5<br />
MIN_LINE_WIDTH=0.6 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
=PP3V3_S5_MCP_GPIO<br />
=PP3V3_S5_ROM<br />
=PP3V3_S5_LCD<br />
=PP3V3_S5_MCP<br />
=PP3V3_S5_MCPPWRGD<br />
=PP3V3_S5_PWRCTL<br />
=PP3V3_S5_P1V05ENETFET<br />
=PP3V3_S5_P3V3S3FET<br />
=PP3V3_S5_P3V3S0FET<br />
=PP3V3_S5_P1V05S5<br />
=PP3V3_S5_MEMRESET<br />
=PP3V3_S5_P3V3ENETFET<br />
=PP3V3_S5_DP_PORT_PWR<br />
=PP3V3_FW_LATEVG<br />
=PP3V3_FW_LATEVG_ACTIVE<br />
=PP3V3_S5_P1V05FWFET<br />
37B8<br />
6D3<br />
26D7<br />
27D7<br />
6B5 6D3<br />
43D3<br />
61B3<br />
43B5<br />
25D8<br />
29A6<br />
20A3<br />
48A6 48B5 48C5 48D2<br />
50B7<br />
30D7<br />
6D3<br />
67D3<br />
28C6<br />
38C7<br />
37A8 39D7<br />
29C3<br />
67A3<br />
67D4<br />
41B8<br />
49B6 49D7<br />
29C1<br />
61C5<br />
52A8 52D2 54D5 56B6<br />
55B7 55C7 55D7<br />
67B8<br />
37D5<br />
6D3<br />
21A3 22D8<br />
32C4<br />
6D3<br />
17C7 19C1<br />
42B5 42C7 51C6<br />
68C8<br />
21B3 22B8<br />
24B8<br />
66B3<br />
32C5<br />
67D8<br />
67C8<br />
65B8<br />
28C4<br />
32D5<br />
70D8<br />
36A7<br />
35A8<br />
35C7<br />
58B4<br />
58D1 58C8<br />
59C1<br />
45B7<br />
=PP3V42_G3H_REG<br />
=PP18V5_DCIN_CONN<br />
=PPBUS_G3H<br />
=PPCPUVCORE_VTT_ISNS<br />
(AFTER HIGH SIDE CPU VCORE<br />
& CPU VTT SENSING RES.)<br />
35D4<br />
35B1<br />
35C5<br />
=PP3V3_FW_FET<br />
PPBUS_G3H<br />
6C3<br />
MIN_LINE_WIDTH=0.6 mm<br />
MIN_NECK_WIDTH=0.3 MM<br />
VOLTAGE=12.6V<br />
MAKE_BASE=TRUE<br />
=PPBUS_S0_LCDBKLT<br />
=PPVIN_S0_MCPCORE<br />
=PPVIN_S5_1V5S30V75S0<br />
=PPVIN_S5_3V3S5<br />
=PPVIN_S3_5VS3<br />
=PPBUS_G3HRS5<br />
=PPBUS_S5_FWPWRSW<br />
=PPCPUVCORE_VTT_ISNS_R<br />
(BEFORE HIGH SIDE SENSING RES.)<br />
"FIREWIRE" RAILS<br />
=PPBUS_S5_FW_FET<br />
=PP1V0_FW_FET<br />
SYNC_MASTER=BEN<br />
PP3V42_G3H<br />
MIN_LINE_WIDTH=0.6 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=3.42V<br />
MAKE_BASE=TRUE<br />
=PPVIN_S5_SMCVREF<br />
=PP3V42_G3H_SMBUS_SMC_BSA<br />
=PP3V42_G3H_PWRCTL<br />
=PP3V42_G3H_CHGR<br />
=PP3V42_G3H_SMCUSBMUX<br />
=PP3V42_G3H_TPAD<br />
=PP3V42_G3H_BATT<br />
=PP3V3_S5_SMC<br />
=PP3V3_S5_LPCPLUS<br />
=PP3V42_G3H_RTC_D<br />
=PP3V42_G3H_BMON_ISNS<br />
=PP3V42_G3H_ONEWIRE<br />
=PP3V42_G3H_AUDIO<br />
PP18V5_G3H<br />
MIN_LINE_WIDTH=0.6 MM<br />
MIN_NECK_WIDTH=0.3 MM<br />
VOLTAGE=18.5V<br />
MAKE_BASE=TRUE<br />
=PP18V5_G3H_CHGR<br />
PPBUS_G3H_CPU_ISNS<br />
MIN_LINE_WIDTH=0.6 mm<br />
MIN_NECK_WIDTH=0.3 MM<br />
VOLTAGE=12.6V<br />
MAKE_BASE=TRUE<br />
=PPVIN_S0_CPUVTTS0<br />
=PPVIN_S5_CPU_IMVP<br />
PP3V3_FW<br />
MIN_LINE_WIDTH=0.6 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
=PP3V3_FW_FWPHY<br />
=PP3V3_S0_P1V05FWFET<br />
PPVP_FW<br />
MIN_LINE_WIDTH=0.4 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=12.6V<br />
MAKE_BASE=TRUE<br />
=PPVP_FW_PORT1<br />
=PPVP_FW_PHY_CPS_FET<br />
PP1V05_FW<br />
MIN_LINE_WIDTH=0.6 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=1.05V<br />
MAKE_BASE=TRUE<br />
=PP1V0_FW_FWPHY<br />
Power Aliases<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
6A7 6B5 6D3<br />
41C8<br />
43C5<br />
66B3 66C8 66D8<br />
59A8 59C6 59D5<br />
38B8<br />
48B5 48C2 48C3<br />
48C5<br />
58C2 58C4<br />
40D4 41C1<br />
41C7 41D8<br />
42C7<br />
24D8<br />
45B8<br />
58D2<br />
56B6<br />
59D8<br />
72D8<br />
63D5<br />
61C2<br />
60C3<br />
60C6 60C7<br />
44B8<br />
35B7<br />
45B8<br />
64C6<br />
42C8<br />
62C3 62D4 62D8<br />
36C3<br />
36C6<br />
41C3<br />
42D5<br />
36D5<br />
36B6<br />
35D8<br />
34B1<br />
34D2<br />
35C7<br />
34D8<br />
35D3<br />
D<br />
C<br />
B<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
7 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
D<br />
8 7 6 5 4 3 2 1<br />
PCI-E ALIASES<br />
DACS ALIASES<br />
SO-DIMM ALIASES<br />
UNUSED GPU LANES<br />
UNUSED CRT & TV-OUT INTERFACE<br />
UNUSED ADDRESS PINS<br />
HEATSINK STANDOFFS<br />
16D6 16C6 =PEG_D2R_N<br />
NC_PEG_D2R_N<br />
Z0902<br />
STDOFF-4.5OD.98H-1.1-3.48-TH<br />
1<br />
LEFT OF CPU<br />
Z0903<br />
STDOFF-4.5OD.98H-1.1-3.48-TH<br />
1<br />
BELOW MCP<br />
FAN STANDOFF<br />
Z0905<br />
STDOFF-4.5OD.98H-1.1-3.48-TH<br />
1<br />
MIN_LINE_WIDTH=0.6MM<br />
MIN_NECK_WIDTH=0.2MM<br />
VOLTAGE=0V<br />
Z0901<br />
STDOFF-4.5OD.98H-1.1-3.48-TH<br />
1<br />
ABOVE CPU<br />
Z0904<br />
STDOFF-4.5OD.98H-1.1-3.48-TH<br />
1<br />
BELOW CPU<br />
16D6 16C6<br />
16D3 16C3<br />
16D3 16C3<br />
16C6<br />
16C3<br />
16C3<br />
16B6<br />
16B6<br />
16B3<br />
16B3<br />
16C6<br />
16C6<br />
16C3<br />
16C3<br />
=PEG_D2R_P<br />
=PEG_R2D_C_N<br />
=PEG_R2D_C_P<br />
PEG_PRSNT_L<br />
PEG_CLK100M_P<br />
PEG_CLK100M_N<br />
PCIE_EXCARD_D2R_P<br />
PCIE_EXCARD_D2R_N<br />
PCIE_EXCARD_R2D_C_P<br />
PCIE_EXCARD_R2D_C_N<br />
PCIE_EXCARD_PRSNT_L<br />
EXCARD_CLKREQ_L<br />
PCIE_CLK100M_EXCARD_P<br />
PCIE_CLK100M_EXCARD_N<br />
UNUSED EXPRESS CARD LANE<br />
NO_TEST=TRUE MAKE_BASE=TRUE<br />
NC_PEG_D2R_P<br />
NO_TEST=TRUE MAKE_BASE=TRUE<br />
NC_PEG_R2D_C_N<br />
NO_TEST=TRUE MAKE_BASE=TRUE<br />
NC_PEG_R2D_C_P<br />
NO_TEST=TRUE MAKE_BASE=TRUE<br />
TP_PEG_PRSNT_L<br />
MAKE_BASE=TRUE<br />
TP_PEG_CLK100M_P<br />
MAKE_BASE=TRUE<br />
TP_PEG_CLK100M_N<br />
MAKE_BASE=TRUE<br />
TP_PCIE_EXCARD_D2R_P<br />
MAKE_BASE=TRUE<br />
TP_PCIE_EXCARD_D2R_N<br />
MAKE_BASE=TRUE<br />
TP_PCIE_EXCARD_R2D_C_P<br />
MAKE_BASE=TRUE<br />
TP_PCIE_EXCARD_R2D_C_N<br />
MAKE_BASE=TRUE<br />
TP_PCIE_EXCARD_PRSNT_L<br />
MAKE_BASE=TRUE<br />
TP_EXCARD_CLKREQ_L<br />
MAKE_BASE=TRUE<br />
TP_PCIE_CLK100M_EXCARD_P<br />
MAKE_BASE=TRUE<br />
TP_PCIE_CLK100M_EXCARD_N<br />
MAKE_BASE=TRUE<br />
17B3<br />
17B3<br />
17B3<br />
17B3<br />
17B3<br />
17B3<br />
17C6<br />
17C6<br />
17C6<br />
17C6<br />
17C3<br />
17C3<br />
17C3<br />
17C3<br />
17C3<br />
MCP_TV_DAC_RSET<br />
MCP_TV_DAC_VREF<br />
MCP_CLK27M_XTALIN<br />
MCP_CLK27M_XTALOUT<br />
CRT_IG_R_C_PR<br />
CRT_IG_G_Y_Y<br />
CRT_IG_B_COMP_PB<br />
CRT_IG_HSYNC<br />
CRT_IG_VSYNC<br />
NC_MCP_TV_DAC_RSET<br />
LVDS ALIASES<br />
NO_TEST=TRUE<br />
NC_MCP_TV_DAC_VREF<br />
NO_TEST=TRUE<br />
NC_MCP_CLK27M_XTALIN<br />
NO_TEST=TRUE<br />
NC_MCP_CLK27M_XTALOUT<br />
NO_TEST=TRUE<br />
NC_CRT_IG_R_C_PR<br />
NO_TEST=TRUE<br />
NC_CRT_IG_G_Y_Y<br />
NO_TEST=TRUE<br />
NC_CRT_IG_B_COMP_PB<br />
NO_TEST=TRUE<br />
NC_CRT_IG_HSYNC<br />
NO_TEST=TRUE<br />
NC_CRT_IG_VSYNC<br />
NO_TEST=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
UNUSED LVDS SIGNALS<br />
LVDS_IG_A_DATA_P NC_LVDS_IG_A_DATA_P3<br />
NO_TEST=TRUE<br />
LVDS_IG_A_DATA_N NC_LVDS_IG_A_DATA_N3<br />
NO_TEST=TRUE<br />
LVDS_IG_B_CLK_P<br />
NC_LVDS_IG_B_CLK_P<br />
NO_TEST=TRUE<br />
LVDS_IG_B_CLK_N<br />
NC_LVDS_IG_B_CLK_N<br />
NO_TEST=TRUE<br />
LVDS_IG_B_DATA_P NC_LVDS_IG_B_DATA_P<br />
NO_TEST=TRUE<br />
LVDS_IG_B_DATA_N NC_LVDS_IG_B_DATA_N<br />
NO_TEST=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
26D5<br />
27D5<br />
32C5<br />
32B5<br />
31C2<br />
31C2<br />
31C6<br />
31B6<br />
MEM_A_A<br />
MEM_B_A<br />
=P3V3ENET_EN<br />
=P1V05ENET_EN<br />
=PP3V3_ENET_PHY_VDDREG<br />
=RTL8211_REGOUT<br />
=RTL8211_ENSWREG<br />
TP_RTL8211_CLK125<br />
ETHERNET ALIASES<br />
PM_SLP_RMGT_L<br />
1<br />
TP_MEM_A_A15<br />
TP_MEM_B_A15<br />
MAKE_BASE=TRUE<br />
R0931<br />
22<br />
5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
FW ALIASES<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
20C3<br />
MAKE_BASE=TRUE<br />
TP_PP3V3_ENET_PHY_VDDREG<br />
MAKE_BASE=TRUE<br />
NC_RTL8211_REGOUT<br />
MAKE_BASE=TRUE<br />
D<br />
C<br />
<strong>MLB</strong> MOUNTING (TO C. BRACKET) SCREW HOLES<br />
OMIT<br />
OMIT<br />
Z0906<br />
Z0907<br />
3R2P5<br />
1<br />
3R2P5<br />
1<br />
35D3 16C6<br />
FIREWIRE PRESENT SIGNALS<br />
R0950<br />
0<br />
PCIE_FW_PRSNT_L<br />
1<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
NOSTUFF<br />
13B6<br />
CPU_PECI_MCP<br />
16B6 GMUX_JTAG_TCK_L<br />
16B6 GMUX_JTAG_TDO<br />
18D4 GMUX_JTAG_TDI<br />
18D4 GMUX_JTAG_TMS<br />
MISC MCP79 ALIASES<br />
TP_CPU_PECI_MCP<br />
MAKE_BASE=TRUE<br />
TP_GMUX_JTAG_TCK_L<br />
MAKE_BASE=TRUE<br />
TP_GMUX_JTAG_TDO<br />
MAKE_BASE=TRUE<br />
TP_GMUX_JTAG_TDI<br />
MAKE_BASE=TRUE<br />
TP_GMUX_JTAG_TMS<br />
MAKE_BASE=TRUE<br />
18B7<br />
35C8 34B2<br />
FW_PME_L<br />
=FW_PME_L<br />
FW_PLUG_DET_L<br />
FW643_WAKE_L<br />
35B1 35D7<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
C<br />
<strong>MLB</strong> MOUNTING (TO TOPCASE) SCREW HOLES<br />
OMIT<br />
3R2P5<br />
1<br />
Z0908<br />
OMIT<br />
3R2P5<br />
Z0911<br />
1<br />
OMIT<br />
3R2P5<br />
Z0909<br />
1<br />
OMIT<br />
3R2P5<br />
Z0912<br />
1<br />
OMIT<br />
3R2P5<br />
1<br />
Z0910<br />
USB ALIASES<br />
UNUSED USB PORTS<br />
19C3 USB_EXTC_P<br />
TP_USB_EXTC_P<br />
MAKE_BASE=TRUE<br />
19C3 USB_EXTC_N<br />
TP_USB_EXTC_N<br />
MAKE_BASE=TRUE<br />
19D3 USB_EXTD_P<br />
TP_USB_EXTD_P<br />
MAKE_BASE=TRUE<br />
19D3 USB_EXTD_N<br />
TP_USB_EXTD_N<br />
MAKE_BASE=TRUE<br />
19C3 USB_EXCARD_P<br />
TP_USB_EXCARD_P<br />
MAKE_BASE=TRUE<br />
19C3 USB_EXCARD_N<br />
TP_USB_EXCARD_N<br />
MAKE_BASE=TRUE<br />
19D3 USB_MINI_P<br />
TP_USB_MINI_P<br />
MAKE_BASE=TRUE<br />
19D3 USB_MINI_N<br />
TP_USB_MINI_N<br />
MAKE_BASE=TRUE<br />
17D6<br />
17D6<br />
17D6<br />
17B6<br />
=MCP_MII_RXER<br />
=MCP_MII_COL<br />
=MCP_MII_CRS<br />
LAN ALIASES<br />
MCP_MII_PD<br />
MAKE_BASE=TRUE<br />
DP HOTPLUG PULL-DOWN<br />
=DVI_HPD_GMUX_INT<br />
HPLUG_DET2<br />
MAKE_BASE=TRUE<br />
1<br />
R0930<br />
47K<br />
5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
1 R0940<br />
20K<br />
5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
73C3 9B4<br />
IN<br />
CPU FSB FREQUENCY STRAPS<br />
CPU_BSEL<br />
MAKE_BASE=TRUE<br />
=MCP_BSEL OUT 13A7<br />
BSEL<br />
0 0 0<br />
1<br />
0<br />
0 1 1<br />
0<br />
0 1<br />
1 1 0<br />
1<br />
FSB MHZ<br />
266<br />
133<br />
200<br />
(166)<br />
333<br />
100<br />
(400)<br />
(RSVD)<br />
B<br />
B<br />
EMI IO POGO PINS<br />
ZS0900<br />
ZS0901<br />
1.4DIA-SHORT-EMI-<strong>MLB</strong>-M97-M98 1.4DIA-SHORT-EMI-<strong>MLB</strong>-M97-M98<br />
SM OMIT<br />
SM OMIT<br />
1<br />
1<br />
ZS0902<br />
1.4DIA-SHORT-EMI-<strong>MLB</strong>-M97-M98<br />
SM OMIT<br />
1<br />
ZS0903<br />
1.4DIA-SHORT-EMI-<strong>MLB</strong>-M97-M98<br />
SM<br />
1<br />
OMIT<br />
ZS0908<br />
1.4DIA-SHORT-EMI-<strong>MLB</strong>-M97-M98<br />
SM<br />
1<br />
OMIT<br />
ZS0909<br />
1.4DIA-SHORT-EMI-<strong>MLB</strong>-M97-M98<br />
SM OMIT<br />
1<br />
A<br />
PART NUMBER<br />
QTY<br />
870-1801 6<br />
ZS0904<br />
2.0DIA-TALL-EMI-<strong>MLB</strong>-M97-M98<br />
SM<br />
1<br />
DESCRIPTION REFERENCE DES CRITICAL BOM OPTION<br />
POGO PIN,SHORT,EMI,<strong>MLB</strong>,K19/<strong>K24</strong><br />
EMI POGO PINS<br />
ZS0905<br />
2.0DIA-TALL-EMI-<strong>MLB</strong>-M97-M98<br />
SM<br />
1<br />
ZS0900,ZS0901,ZS0902,ZS0903,ZS0908,ZS0909<br />
CRITICAL<br />
ZS0906<br />
2.0DIA-TALL-EMI-<strong>MLB</strong>-M97-M98<br />
SM<br />
1<br />
ZS0907<br />
2.0DIA-TALL-EMI-<strong>MLB</strong>-M97-M98<br />
SM<br />
1<br />
SYNC_MASTER=M97_<strong>MLB</strong><br />
APPLE INC.<br />
SIGNAL ALIAS<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
8<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
A<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
OMIT<br />
D<br />
73D3 13D6<br />
73D3 13D6<br />
73D3 13D6<br />
73D3 13D6<br />
73D3 13D6<br />
73D3 13D6<br />
73D3 13C6<br />
73D3 13C6<br />
73D3 13C6<br />
73D3 13C6<br />
73D3 13C6<br />
73D3 13C6<br />
73D3 13C6<br />
73D3 13C6<br />
73D3 13B6<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_ADSTB_L<br />
J4 A3* U1000<br />
L5 A4* PENRYN<br />
L4<br />
FCBGA<br />
A5*<br />
1 OF 4<br />
K5 A6*<br />
M3 A7*<br />
N2 A8*<br />
J1 A9*<br />
N3 A10*<br />
P5 A11*<br />
P2 A12*<br />
L2 A13*<br />
P4 A14*<br />
P1 A15*<br />
R1 A16*<br />
M1 ADSTB0*<br />
ADDR GROUP0<br />
CONTROL<br />
ADS*<br />
BNR*<br />
BPRI*<br />
DEFER*<br />
DRDY*<br />
DBSY*<br />
BR0*<br />
IERR*<br />
INIT*<br />
LOCK*<br />
H1<br />
E2<br />
G5<br />
H5<br />
F21<br />
E1<br />
F1<br />
D20<br />
B3<br />
H4<br />
FSB_ADS_L<br />
FSB_BNR_L<br />
FSB_BPRI_L<br />
FSB_DEFER_L<br />
FSB_DRDY_L<br />
FSB_DBSY_L<br />
FSB_BREQ0_L<br />
73B3 CPU_IERR_L<br />
CPU_INIT_L<br />
FSB_LOCK_L<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
BI<br />
13B6 73C3<br />
13B6 73C3<br />
13B3 73C3<br />
13B3 73C3<br />
13B6 73C3<br />
13B6 73C3<br />
13B6 73C3<br />
13A3 73C3<br />
13B6 73C3<br />
R1000 1<br />
54.9<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
=PP1V05_S0_CPU<br />
7D7 10C6 11B6 12D6<br />
D<br />
73D3 13B6<br />
73D3 13B6<br />
73D3 13B6<br />
73D3 13B6<br />
73D3 13B6<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
FSB_REQ_L<br />
FSB_REQ_L<br />
FSB_REQ_L<br />
FSB_REQ_L<br />
FSB_REQ_L<br />
K3<br />
H2<br />
K2<br />
J3<br />
L1<br />
REQ0*<br />
REQ1*<br />
REQ2*<br />
REQ3*<br />
REQ4*<br />
RESET*<br />
RS0*<br />
RS1*<br />
RS2*<br />
TRDY*<br />
C1<br />
F3<br />
F4<br />
G3<br />
G2<br />
FSB_CPURST_L<br />
FSB_RS_L<br />
FSB_RS_L<br />
FSB_RS_L<br />
FSB_TRDY_L<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
12C2 13A3 73C3<br />
13A6 73C3<br />
13A6 73C3<br />
13A6 73C3<br />
13B6 73C3<br />
C<br />
B<br />
73C3 13C6<br />
73C3 13C6<br />
73C3 13C6<br />
73C3 13C6<br />
73C3 13C6<br />
73C3 13C6<br />
73C3 13C6<br />
73C3 13C6<br />
73C3 13C6<br />
73C3 13C6<br />
73C3 13C6<br />
73C3 13C6<br />
73C3 13C6<br />
73C3 13C6<br />
73C3 13C6<br />
73C3 13C6<br />
73C3 13C6<br />
73C3 13C6<br />
73C3 13C6<br />
73C3 13B6<br />
73C3 13A3<br />
73C3 13B7<br />
73C3 13A3<br />
73B3 13A3<br />
73C3 13A3<br />
73C3 13A3<br />
73B3 13A3<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_ADSTB_L<br />
CPU_A20M_L<br />
CPU_FERR_L<br />
CPU_IGNNE_L<br />
CPU_STPCLK_L<br />
CPU_INTR<br />
CPU_NMI<br />
CPU_SMI_L<br />
TP_CPU_RSVD_M4<br />
TP_CPU_RSVD_N5<br />
TP_CPU_RSVD_T2<br />
TP_CPU_RSVD_V3<br />
TP_CPU_RSVD_B2<br />
TP_CPU_RSVD_F6<br />
TP_CPU_RSVD_D2<br />
TP_CPU_RSVD_D22<br />
TP_CPU_RSVD_D3<br />
Y2<br />
U5<br />
R3<br />
W6<br />
U4<br />
Y5<br />
U1<br />
R4<br />
T5<br />
T3<br />
W2<br />
W5<br />
Y4<br />
U2<br />
V4<br />
W3<br />
AA4<br />
AB2<br />
AA3<br />
V1<br />
A6<br />
A5<br />
C4<br />
D5<br />
C6<br />
B4<br />
A3<br />
M4<br />
N5<br />
T2<br />
V3<br />
B2<br />
F6<br />
D2<br />
D22<br />
D3<br />
A17*<br />
A18*<br />
A19*<br />
A20*<br />
A21*<br />
A22*<br />
A23*<br />
A24*<br />
A25*<br />
A26*<br />
A27*<br />
A28*<br />
A29*<br />
A30*<br />
A31*<br />
A32*<br />
A33*<br />
A34*<br />
A35*<br />
ADSTB1*<br />
A20M*<br />
FERR*<br />
IGNNE*<br />
STPCLK*<br />
LINT0<br />
LINT1<br />
SMI*<br />
RSVD0<br />
RSVD1<br />
RSVD2<br />
RSVD3<br />
RSVD4<br />
RSVD5<br />
RSVD6<br />
RSVD7<br />
RSVD8<br />
ADDR GROUP1<br />
ICH<br />
RESERVED<br />
XDP/ITP SIGNALS<br />
THERMAL<br />
HIT*<br />
HITM*<br />
BPM0*<br />
BPM1*<br />
BPM2*<br />
BPM3*<br />
PRDY*<br />
PREQ*<br />
TCK<br />
TDI<br />
TDO<br />
TMS<br />
TRST*<br />
DBR*<br />
PROCHOT*<br />
THERMDA<br />
THERMDC<br />
THERMTRIP*<br />
H CLK<br />
BCLK0<br />
BCLK1<br />
G6<br />
E4<br />
AD4<br />
AD3<br />
AD1<br />
AC4<br />
AC2<br />
AC1<br />
AC5<br />
AA6<br />
AB3<br />
AB5<br />
AB6<br />
C20<br />
D21<br />
A24<br />
B25<br />
C7<br />
A22<br />
A21<br />
FSB_HIT_L<br />
FSB_HITM_L<br />
XDP_BPM_L<br />
XDP_BPM_L<br />
XDP_BPM_L<br />
XDP_BPM_L<br />
XDP_BPM_L<br />
XDP_BPM_L<br />
XDP_TCK<br />
XDP_TDI<br />
XDP_TDO<br />
XDP_TMS<br />
XDP_TRST_L<br />
XDP_DBRESET_L<br />
CPU_PROCHOT_L<br />
CPU_THERMD_P<br />
CPU_THERMD_N<br />
PM_THRMTRIP_L<br />
FSB_CLK_CPU_P<br />
FSB_CLK_CPU_N<br />
73A3 12B3 9C6<br />
73A3 12B3 9C6<br />
73A3 12B3 9C6<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
IN<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
13B6 73C3<br />
13B6 73C3<br />
12C6 73A3<br />
12C6 73A3<br />
12C6 73A3<br />
12C6 73A3<br />
12C6 73A3<br />
9A6 12B6 73A3<br />
9B6 12B3 73A3<br />
9B6 12B3 73A3<br />
9B6 12B3 73A3<br />
9A6 12B3 73A3<br />
12B3 24A3<br />
46D5 80D3<br />
46D5 80D3<br />
13B7 41C4 73B3<br />
13B3 73B3<br />
13B3 73B3<br />
CPU JTAG Support<br />
R1091<br />
54.9<br />
1 2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
PLACEMENT_NOTE=Place R1092 near ITP connector (if present)<br />
73A3 12B6 9C6<br />
73A3 12B3 9C6<br />
XDP_TMS<br />
XDP_TDI<br />
XDP_TDO<br />
XDP_TCK<br />
XDP_TRST_L<br />
R1094<br />
649<br />
1 2<br />
R1001 1<br />
54.9<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R1002 1<br />
68<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R1090<br />
54.9<br />
1 2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
R1092<br />
54.9<br />
1 2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
R1093<br />
54.9<br />
1 2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
BI<br />
OUT<br />
1<br />
R1005<br />
1K<br />
2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
12C6 73A3<br />
13B6 41D4 62C8 73C3<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13D6<br />
73D3 13D6<br />
73D3 13D6<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13D3<br />
73D3 13C3<br />
73D3 13C3<br />
73D3 13C3<br />
73D3 13C3<br />
73D3 13C3<br />
73D3 13C3<br />
73D3 13C3<br />
73D3 13C3<br />
73D3 13C3<br />
73D3 13C3<br />
73D3 13C3<br />
73D3 13D6<br />
73D3 13D6<br />
73D3 13D6<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_DSTB_L_N<br />
FSB_DSTB_L_P<br />
FSB_DINV_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_DSTB_L_N<br />
FSB_DSTB_L_P<br />
FSB_DINV_L<br />
E22<br />
D0* D32*<br />
F24 D1*<br />
E26 D2*<br />
G22 D3*<br />
F23 D4*<br />
G25 D5*<br />
E25 D6*<br />
E23 D7*<br />
<strong>K24</strong> D8*<br />
G24 D9*<br />
J24 D10*<br />
J23 D11*<br />
H22 D12*<br />
F26 D13*<br />
K22 D14*<br />
H23 D15*<br />
J26 DSTBN0*<br />
H26 DSTBP0*<br />
H25 DINV0*<br />
N22 D16*<br />
K25 D17*<br />
P26 D18*<br />
R23 D19*<br />
L23 D20*<br />
M24 D21*<br />
L22 D22*<br />
M23 D23*<br />
P25 D24*<br />
P23 D25*<br />
P22 D26*<br />
T24 D27*<br />
R24 D28*<br />
L25 D29*<br />
T25 D30*<br />
N25 D31*<br />
L26 DSTBN1*<br />
M26 DSTBP1*<br />
N24 DINV1*<br />
73B3 25B1 CPU_GTLREF<br />
AD26 GTLREF<br />
COMP0 R26 73A3 CPU_COMP<br />
MISC<br />
CPU_TEST1<br />
C23 TEST1<br />
COMP1 U26 73B3 CPU_COMP<br />
1<br />
R1006<br />
CPU_TEST2<br />
D25 TEST2<br />
COMP2 AA1 73B3 CPU_COMP<br />
2.0K<br />
TP_CPU_TEST3<br />
C24 TEST3<br />
COMP3 Y1 73B3 CPU_COMP<br />
1%<br />
1/16W<br />
CPU_TEST4<br />
AF26 TEST4<br />
MF-LF<br />
402 NO STUFF<br />
TP_CPU_TEST5<br />
AF1 TEST5<br />
DPRSTP* E5 CPU_DPRSTP_L<br />
2<br />
IN 13A3 62C7 73B3<br />
R1023 1<br />
C1014 1 TP_CPU_TEST6<br />
A26 TEST6<br />
DPSLP* B5 CPU_DPSLP_L<br />
IN 13A3 73B3<br />
54.9<br />
1%<br />
NO STUFF<br />
0.1uF<br />
TP_CPU_TEST7<br />
C3 TEST7<br />
DPWR* D24 FSB_DPWR_L<br />
IN 13A3 73B3<br />
1/16W<br />
10%<br />
16V<br />
MF-LF<br />
2<br />
73C3 8B2 OUT<br />
BSEL0<br />
PWRGOOD<br />
IN 12C7 13A3 73C3<br />
402<br />
R1010<br />
CPU_BSEL<br />
B22<br />
D6 CPU_PWRGD<br />
X5R<br />
2<br />
402<br />
0<br />
73C3 8B2 OUT CPU_BSEL<br />
B23 BSEL1<br />
SLP* D7 FSB_CPUSLP_L<br />
IN 13A3 73B3<br />
1 2<br />
73C3 8B2 OUT CPU_BSEL<br />
C21 BSEL2<br />
PSI* AE6 CPU_PSI_L<br />
OUT 62C7<br />
NO STUFF<br />
5% NO STUFF<br />
1/16W<br />
MF-LF<br />
R1011 1 1<br />
402<br />
R1012<br />
1K<br />
1K<br />
PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU.<br />
5%<br />
5%<br />
1/16W<br />
1/16W<br />
PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU.<br />
MF-LF<br />
MF-LF<br />
402<br />
2<br />
2 402<br />
PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.<br />
U1000<br />
PENRYN<br />
DATA GRP 0<br />
DATA GRP 1<br />
OMIT<br />
FCBGA<br />
2 OF 4<br />
DATA GRP 3 DATA GRP 2<br />
D33*<br />
D34*<br />
D35*<br />
D36*<br />
D37*<br />
D38*<br />
D39*<br />
D40*<br />
D41*<br />
D42*<br />
D43*<br />
D44*<br />
D45*<br />
D46*<br />
D47*<br />
DSTBN2*<br />
DSTBP2*<br />
DINV2*<br />
D48*<br />
D49*<br />
D50*<br />
D51*<br />
D52*<br />
D53*<br />
D54*<br />
D55*<br />
D56*<br />
D57*<br />
D58*<br />
D59*<br />
D60*<br />
D61*<br />
D62*<br />
D63*<br />
DSTBN3*<br />
DSTBP3*<br />
DINV3*<br />
Y22<br />
AB24<br />
V24<br />
V26<br />
V23<br />
T22<br />
U25<br />
U23<br />
Y25<br />
W22<br />
Y23<br />
W24<br />
W25<br />
AA23<br />
AA24<br />
AB25<br />
Y26<br />
AA26<br />
U22<br />
AE24<br />
AD24<br />
AA21<br />
AB22<br />
AB21<br />
AC26<br />
AD20<br />
AE22<br />
AF23<br />
AC25<br />
AE21<br />
AD21<br />
AC22<br />
AD23<br />
AF22<br />
AC23<br />
AE25<br />
AF24<br />
AC20<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_DSTB_L_N<br />
FSB_DSTB_L_P<br />
FSB_DINV_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_DSTB_L_N<br />
FSB_DSTB_L_P<br />
FSB_DINV_L<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
13C3 73D3<br />
13C3 73D3<br />
13C3 73D3<br />
13C3 73D3<br />
13C3 73D3<br />
13C3 73D3<br />
13C3 73D3<br />
13C3 73D3<br />
13C3 73D3<br />
13C3 73D3<br />
13C3 73D3<br />
13C3 73D3<br />
13C3 73D3<br />
13C3 73D3<br />
13C3 73D3<br />
13B3 73D3<br />
13D6 73D3<br />
13D6 73D3<br />
13D6 73D3<br />
13B3 73D3<br />
13B3 73D3<br />
13B3 73D3<br />
13B3 73D3<br />
13B3 73D3<br />
13B3 73D3<br />
13B3 73D3<br />
13B3 73D3<br />
13B3 73D3<br />
13B3 73D3<br />
13B3 73D3<br />
13B3 73D3<br />
13B3 73D3<br />
13B3 73D3<br />
13B3 73D3<br />
13B3 73D3<br />
13D6 73D3<br />
13D6 73D3<br />
13D6 73D3<br />
PLACEMENT_NOTE (all 4 resistors):<br />
1<br />
R1022<br />
27.4<br />
1%<br />
2<br />
1/16W<br />
MF-LF<br />
402<br />
R1021 1<br />
54.9<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
R1020<br />
27.4<br />
1%<br />
2<br />
1/16W<br />
MF-LF<br />
402<br />
C<br />
B<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
Place within 12.7mm of CPU<br />
A<br />
CPU FSB<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
SYNC_DATE=12/12/2007<br />
NOTICE OF PROPRIETARY PROPERTY<br />
A<br />
SYNC FROM T18<br />
CHANGE CPU FROM SOCKET TO BGA SYMBOL<br />
APPLE INC.<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
9<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
A4<br />
P6<br />
D<br />
A7<br />
A9<br />
A10<br />
A12<br />
A13<br />
OMIT<br />
U1000<br />
PENRYN<br />
FCBGA<br />
AB20<br />
AB7<br />
AC7<br />
AC9<br />
AC12<br />
(CPU CORE POWER)<br />
=PPVCORE_S0_CPU<br />
7D7 10B5 11D6<br />
44 A (SV Design Target)<br />
41 A (SV HFM)<br />
30.4 A (SV LFM)<br />
23 A (LV Design Target)<br />
A8<br />
A11<br />
A14<br />
A16<br />
A19<br />
A23<br />
AF2<br />
B6<br />
B8<br />
B11<br />
OMIT<br />
U1000<br />
PENRYN<br />
FCBGA<br />
4 OF 4<br />
P21<br />
P24<br />
R2<br />
R5<br />
R22<br />
R25<br />
T1<br />
T4<br />
T23<br />
T26<br />
D<br />
A15<br />
A17<br />
3 OF 4<br />
AC13<br />
AC15<br />
B13<br />
B16<br />
U3<br />
U6<br />
A18<br />
AC17<br />
B19<br />
U21<br />
A20<br />
AC18<br />
B21<br />
U24<br />
B7<br />
AD7<br />
B24<br />
V2<br />
B9<br />
AD9<br />
C5<br />
V5<br />
B10<br />
AD10<br />
C8<br />
V22<br />
B12<br />
AD12<br />
C11<br />
V25<br />
B14<br />
AD14<br />
C14<br />
W1<br />
B15<br />
AD15<br />
C16<br />
W4<br />
B17<br />
AD17<br />
C19<br />
W23<br />
B18<br />
AD18<br />
C2<br />
W26<br />
B20<br />
C9<br />
VCC<br />
AE9<br />
AE10<br />
C22<br />
C25<br />
Y3<br />
Y6<br />
C10<br />
AE12<br />
D1<br />
Y21<br />
C12<br />
AE13<br />
D4<br />
Y24<br />
C13<br />
AE15<br />
D8<br />
AA2<br />
C15<br />
AE17<br />
D11<br />
AA5<br />
C17<br />
AE18<br />
D13<br />
AA8<br />
C18<br />
AE20<br />
D16<br />
AA11<br />
C<br />
D9<br />
D10<br />
D12<br />
AF9<br />
AF10<br />
AF12<br />
D19<br />
D23<br />
D26<br />
AA14<br />
AA16<br />
AA19<br />
C<br />
D14<br />
AF14<br />
E3<br />
AA22<br />
D15<br />
D17<br />
VCC<br />
AF15<br />
AF17<br />
E6<br />
E8<br />
AA25<br />
AB1<br />
D18<br />
E7<br />
E9<br />
AF18<br />
AF20<br />
(CPU IO POWER 1.05V)<br />
=PP1V05_S0_CPU<br />
7D7 9D5 11B6 12D6<br />
E11<br />
E14<br />
E16<br />
VSS<br />
VSS<br />
AB4<br />
AB8<br />
AB11<br />
E10<br />
E12<br />
E13<br />
G21<br />
V6<br />
J6<br />
4500 mA (before VCC stable)<br />
2500 mA (after VCC stable)<br />
E19<br />
E21<br />
E24<br />
AB13<br />
AB16<br />
AB19<br />
E15<br />
K6<br />
F5<br />
AB23<br />
E17<br />
M6<br />
F8<br />
AB26<br />
E18<br />
J21<br />
F11<br />
AC3<br />
E20<br />
K21<br />
F13<br />
AC6<br />
F7<br />
F9<br />
VCCP<br />
M21<br />
N21<br />
F16<br />
F19<br />
AC8<br />
AC11<br />
F10<br />
N6<br />
F2<br />
AC14<br />
F12<br />
R21<br />
F22<br />
AC16<br />
F14<br />
R6<br />
F25<br />
AC19<br />
F15<br />
T21<br />
G4<br />
AC21<br />
F17<br />
T6<br />
G1<br />
AC24<br />
F18<br />
F20<br />
V21<br />
W21<br />
(CPU INTERNAL PLL POWER 1.5V)<br />
G23<br />
G26<br />
AD2<br />
AD5<br />
AA7<br />
(BR1#)<br />
=PP1V5_S0_CPU<br />
7B6 11B6<br />
H3<br />
AD8<br />
B<br />
AA9<br />
AA10<br />
AA12<br />
AA13<br />
AA15<br />
AA17<br />
AA18<br />
AA20<br />
AB9<br />
AC10<br />
AB10<br />
AB12<br />
AB14<br />
AB15<br />
AB17<br />
AB18<br />
VCCA<br />
VID0 AD6<br />
VID1 AF5<br />
VID2 AE5<br />
VID3 AF4<br />
VID4 AE3<br />
VID5 AF3<br />
VID6 AE2<br />
VCCSENSE<br />
VSSSENSE<br />
B26<br />
C26<br />
AF7<br />
AE7<br />
CPU_VID<br />
CPU_VID<br />
CPU_VID<br />
CPU_VID<br />
CPU_VID<br />
CPU_VID<br />
CPU_VID<br />
CPU_VCCSENSE_P<br />
CPU_VCCSENSE_N<br />
130 mA<br />
OUT 62C7 73A3<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
62C7 73A3<br />
62C7 73A3<br />
62C7 73A3<br />
62C7 73A3<br />
62C7 73A3<br />
62C7 73A3<br />
1<br />
=PPVCORE_S0_CPU<br />
R1100<br />
100<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
OUT<br />
PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.<br />
PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.<br />
OUT<br />
62A5 73A3<br />
62A5 73A3<br />
7D7 10D6 11D6<br />
H6<br />
H21<br />
H24<br />
J2<br />
J5<br />
J22<br />
J25<br />
K1<br />
K4<br />
K23<br />
K26<br />
L3<br />
L6<br />
L21<br />
L24<br />
M2<br />
M5<br />
AD11<br />
AD13<br />
AD16<br />
AD19<br />
AD22<br />
AD25<br />
AE1<br />
AE4<br />
AE8<br />
AE11<br />
AE14<br />
AE16<br />
AE19<br />
AE23<br />
AE26<br />
A2<br />
AF6<br />
B<br />
1<br />
R1101<br />
100<br />
1%<br />
1/16W<br />
2<br />
MF-LF<br />
402<br />
M22<br />
M25<br />
N1<br />
N4<br />
N23<br />
AF8<br />
AF11<br />
AF13<br />
AF16<br />
AF19<br />
N26<br />
AF21<br />
P3<br />
A25<br />
A<br />
B1<br />
(Socket-P KEY)<br />
AF25<br />
CPU Power & Ground<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
SYNC_DATE=12/12/2007<br />
NOTICE OF PROPRIETARY PROPERTY<br />
A<br />
SYNC FROM T18<br />
CHANGE CPU FROM SOCKET TO BGA SYMBOL<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
Current numbers from Merom for Santa Rosa EMTS, doc #20905.<br />
8 7 6 5 4 3 2 1<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
10<br />
OF<br />
REV.<br />
81<br />
4.7.0
8 7 6 5 4 3 2 1<br />
CPU VCore HF and Bulk Decoupling<br />
4X 330UF. 20X 22UF 0805<br />
D<br />
10D6 10B5 7D7 =PPVCORE_S0_CPU<br />
PLACEMENT_NOTE (C1200-C1219):<br />
Place inside socket cavity on secondary side.<br />
CRITICAL<br />
1<br />
C1200<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
CRITICAL<br />
1<br />
C1201<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
CRITICAL<br />
1<br />
C1202<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
CRITICAL<br />
1<br />
C1203<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
CRITICAL<br />
1<br />
C1204<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
CRITICAL<br />
1<br />
C1205<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
CRITICAL<br />
1<br />
C1206<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
CRITICAL<br />
1<br />
C1207<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
CRITICAL<br />
1<br />
C1208<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
CRITICAL<br />
1<br />
C1209<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
D<br />
CRITICAL<br />
1<br />
C1210<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
CRITICAL<br />
1<br />
C1211<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
CRITICAL<br />
1<br />
C1212<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
CRITICAL<br />
1<br />
C1213<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
CRITICAL<br />
1<br />
C1214<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
CRITICAL<br />
1<br />
C1215<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
CRITICAL<br />
1<br />
C1216<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
CRITICAL<br />
1<br />
C1217<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
CRITICAL<br />
1<br />
C1218<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
CRITICAL<br />
1<br />
C1219<br />
22UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
805<br />
C<br />
C<br />
PLACEMENT_NOTE (C1240-C1243):<br />
Place on secondary side.<br />
Place on secondary side.<br />
NOSTUFF<br />
CRITICAL CRITICAL<br />
1<br />
C1240<br />
1<br />
C1241<br />
1<br />
470UF-4MOHM 470UF-4MOHM<br />
20%<br />
20%<br />
2.0V<br />
2.0V<br />
3 2<br />
3 2<br />
3 2<br />
POLY-TANT<br />
POLY-TANT<br />
D2T-SM<br />
D2T-SM<br />
CRITICAL<br />
C1242<br />
470UF-4MOHM<br />
20%<br />
2.0V<br />
POLY-TANT<br />
D2T-SM<br />
CRITICAL<br />
1<br />
C1243<br />
470UF-4MOHM<br />
20%<br />
3 2 2.0V<br />
POLY-TANT<br />
D2T-SM<br />
Place on secondary side.<br />
Place on secondary side.<br />
10B6 7B6 =PP1V5_S0_CPU<br />
VCCA (CPU AVdd) DECOUPLING<br />
1x 10uF, 1x 0.01uF<br />
PLACEMENT_NOTE=Place C1281 near CPU pin B26.<br />
C1250 1 2<br />
10uF<br />
20%<br />
6.3V<br />
X5R<br />
603<br />
1<br />
2<br />
C1251<br />
0.01UF<br />
10%<br />
16V<br />
CERM<br />
402<br />
B<br />
B<br />
12D6 10C6 9D5 7D7 =PP1V05_S0_CPU<br />
VCCP (CPU I/O) DECOUPLING<br />
1x 330uF, 6x 0.1uF 0402<br />
PLACEMENT_NOTE=Place C1260 between CPU & NB.<br />
CRITICAL<br />
C1260 1<br />
330UF<br />
20%<br />
2.0V 2 3<br />
POLY-TANT<br />
D2T-SM2<br />
1<br />
2<br />
C1261<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
1<br />
2<br />
C1262<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
1<br />
C1263<br />
0.1UF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
1<br />
2<br />
C1264<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
1<br />
C1265<br />
0.1UF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
1<br />
2<br />
C1266<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
A<br />
CPU Decoupling<br />
SYNC_MASTER=RAYMOND<br />
SYNC_DATE=03/31/2008<br />
NOTICE OF PROPRIETARY PROPERTY<br />
A<br />
SYNC FROM T18<br />
REMOVE NO STUFF CAPS C1220 TO C1231<br />
REMOVE C1244 & C1245<br />
CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM)<br />
APPLE INC.<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
11<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
Mini-XDP Connector<br />
NOTE: This is not the standard XDP pinout.<br />
Use with 920-0620 adapter board to support CPU, MCP debugging.<br />
MCP79-specific pinout<br />
D<br />
7C5 =PP3V3_S0_XDP<br />
11B6 10C6 9D5 7D7 =PP1V05_S0_CPU<br />
C<br />
73A3 9C5 BI<br />
73A3 9C6 BI<br />
73A3 9C6 BI<br />
73A3 9C6 IN<br />
73A3 9C6 IN<br />
73A3 9C6 IN<br />
XDP_BPM_L<br />
XDP_BPM_L<br />
XDP_BPM_L<br />
XDP_BPM_L<br />
XDP_BPM_L<br />
XDP_BPM_L<br />
TP_XDP_OBSFN_B0<br />
TP_XDP_OBSFN_B1<br />
XDP<br />
R1315 1<br />
54.9<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
OBSFN_A0<br />
OBSFN_A1<br />
OBSDATA_A0<br />
OBSDATA_A1<br />
OBSDATA_A2<br />
OBSDATA_A3<br />
OBSFN_B0<br />
OBSFN_B1<br />
LTH-030-01-G-D-NOPEGS<br />
F-ST-SM<br />
2<br />
4<br />
6<br />
8<br />
10<br />
12<br />
14<br />
16<br />
18<br />
20<br />
22<br />
24<br />
26<br />
XDP_CONN<br />
CRITICAL<br />
J1300<br />
1<br />
3<br />
5<br />
7<br />
9<br />
11<br />
13<br />
15<br />
17<br />
19<br />
21<br />
23<br />
25<br />
OBSFN_C0<br />
OBSFN_C1<br />
OBSDATA_C0<br />
OBSDATA_C1<br />
OBSDATA_C2<br />
OBSDATA_C3<br />
OBSFN_D0<br />
OBSFN_D1<br />
JTAG_MCP_TDO<br />
JTAG_MCP_TRST_L<br />
MCP_DEBUG<br />
MCP_DEBUG<br />
MCP_DEBUG<br />
MCP_DEBUG<br />
JTAG_MCP_TDI<br />
JTAG_MCP_TMS<br />
IN 20B7<br />
OUT 20B7<br />
BI 18D7 76D3<br />
BI 18D7 76D3<br />
BI 18D7 76D3<br />
BI 18D7 76D3<br />
OUT 20B7<br />
OUT 20B7<br />
C<br />
B<br />
73C3 13A3 9B2<br />
IN<br />
CPU_PWRGD<br />
XDP<br />
R1399<br />
1K<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
18C4<br />
20B7<br />
76B3 43D8 20C3<br />
76B3 43D8 20C3<br />
73A3 9C6 9A6<br />
IN<br />
OUT<br />
BI<br />
BI<br />
OUT<br />
TP_XDP_OBSDATA_B0<br />
TP_XDP_OBSDATA_B1<br />
TP_XDP_OBSDATA_B2<br />
TP_XDP_OBSDATA_B3<br />
XDP_PWRGD<br />
PM_LATRIGGER_L<br />
JTAG_MCP_TCK<br />
SMBUS_MCP_0_DATA<br />
SMBUS_MCP_0_CLK<br />
XDP_TCK<br />
XDP_OBS20<br />
OBSDATA_B0<br />
OBSDATA_B1<br />
OBSDATA_B2<br />
OBSDATA_B3<br />
PWRGD/HOOK0<br />
HOOK1<br />
VCC_OBS_AB<br />
HOOK2<br />
HOOK3<br />
SDA<br />
SCL<br />
TCK1<br />
TCK0<br />
XDP<br />
C1300 1<br />
0.1uF<br />
10%<br />
16V<br />
2<br />
X5R<br />
402<br />
28<br />
30<br />
32<br />
34<br />
36<br />
38<br />
40<br />
42<br />
44<br />
46<br />
48<br />
50<br />
52<br />
54<br />
56<br />
NC<br />
58<br />
60<br />
27<br />
29<br />
31<br />
33<br />
35<br />
37<br />
39<br />
41<br />
43<br />
45<br />
47<br />
49<br />
51<br />
53<br />
55<br />
57<br />
59<br />
998-1571<br />
OBSDATA_D0<br />
OBSDATA_D1<br />
OBSDATA_D2<br />
OBSDATA_D3<br />
MCP_DEBUG<br />
MCP_DEBUG<br />
MCP_DEBUG<br />
MCP_DEBUG<br />
ITPCLK/HOOK4<br />
FSB_CLK_ITP_P<br />
ITPCLK#/HOOK5<br />
FSB_CLK_ITP_N<br />
VCC_OBS_CD<br />
RESET#/HOOK6<br />
73A3 XDP_CPURST_L<br />
DBR#/HOOK7<br />
XDP_DBRESET_L<br />
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.<br />
TDO<br />
XDP_TDO<br />
TRSTn<br />
XDP_TRST_L<br />
TDI<br />
XDP_TDI<br />
TMS<br />
XDP_TMS<br />
XDP_PRESENT#<br />
XDP<br />
1<br />
C1301<br />
0.1uF<br />
10%<br />
16V<br />
2<br />
X5R<br />
402<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
18D7 76D3<br />
18D7 76D3<br />
18D7 76D3<br />
18D7 76D3<br />
13B3 73B3<br />
13B3 73B3<br />
9C6 24A3<br />
9B6 9C6 73A3<br />
9A6 9C6 73A3<br />
9B6 9C6 73A3<br />
9B6 9C6 73A3<br />
XDP<br />
R1303<br />
1K<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
FSB_CPURST_L<br />
IN 9D6 13A3 73C3<br />
PLACEMENT_NOTE=Place close to CPU to minimize stub.<br />
B<br />
Direction of XDP module<br />
Please avoid any obstructions<br />
on even-numbered side of J1300<br />
A<br />
SYNC_MASTER=K19_<strong>MLB</strong><br />
eXtended Debug Port(MiniXDP)<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=11/07/2008<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
12<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
8 7 6 5 4 3 2 1
D<br />
C<br />
B<br />
A<br />
8 7 6 5 4 3 2 1<br />
22C8 21D3 13A2 7D7<br />
73B3 41C4 9C6<br />
73C3 9C8<br />
8B1<br />
8B1<br />
8B1<br />
=PP1V05_S0_MCP_FSB<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
PM_THRMTRIP_L<br />
CPU_FERR_L<br />
=MCP_BSEL<br />
=MCP_BSEL<br />
=MCP_BSEL<br />
R1410<br />
54.9<br />
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
NO STUFF<br />
1<br />
R1420<br />
1K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
2<br />
2<br />
R1415<br />
62<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
NO STUFF<br />
1<br />
R1421<br />
1K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
2<br />
2<br />
1<br />
R1416<br />
62<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
NO STUFF<br />
1<br />
R1422<br />
1K<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
R1430<br />
49.9<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
R1431<br />
49.9<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
2<br />
2<br />
R1435<br />
49.9<br />
1<br />
2<br />
2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
R1436<br />
49.9<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
73D3 9C4<br />
73D3 9C4<br />
73D3 9C4<br />
73D3 9B4<br />
73D3 9B4<br />
73D3 9B4<br />
73D3 9C2<br />
73D3 9C2<br />
73D3 9C2<br />
73D3 9B2<br />
73D3 9B2<br />
73D3 9B2<br />
73D3 9D8<br />
73D3 9D8<br />
73D3 9D8<br />
73D3 9D8<br />
73D3 9D8<br />
73D3 9D8<br />
73D3 9D8<br />
73D3 9D8<br />
73D3 9D8<br />
73D3 9D8<br />
73D3 9D8<br />
73D3 9D8<br />
73D3 9D8<br />
73D3 9D8<br />
73C3 9D8<br />
73C3 9C8<br />
73C3 9C8<br />
73C3 9C8<br />
73C3 9C8<br />
73C3 9C8<br />
73C3 9C8<br />
73C3 9C8<br />
73C3 9C8<br />
73C3 9C8<br />
73C3 9C8<br />
73C3 9C8<br />
73C3 9C8<br />
73C3 9C8<br />
73C3 9C8<br />
73C3 9C8<br />
73C3 9C8<br />
73C3 9C8<br />
73C3 9C8<br />
73D3 9D8<br />
73C3 9C8<br />
73D3 9D8<br />
73D3 9D8<br />
73D3 9D8<br />
73D3 9D8<br />
73D3 9D8<br />
73C3 9D6<br />
73C3 9D6<br />
73C3 9D6<br />
73C3 9D6<br />
73C3 9D6<br />
73C3 9D6<br />
73C3 9D6<br />
73C3 9D6<br />
73C3 9D6<br />
8C4<br />
73C3 62C8 41D4 9C5<br />
73C3 9D6<br />
73C3 9D6<br />
73C3 9D6<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI FSB_ADS_L<br />
BI FSB_BNR_L<br />
BI FSB_BREQ0_L<br />
73C3 FSB_BREQ1_L<br />
BI FSB_DBSY_L<br />
BI<br />
FSB_DRDY_L<br />
BI FSB_HIT_L<br />
BI FSB_HITM_L<br />
IN FSB_LOCK_L<br />
OUT FSB_TRDY_L<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
22C2<br />
FSB_DSTB_L_P<br />
FSB_DSTB_L_N<br />
FSB_DINV_L<br />
FSB_DSTB_L_P<br />
FSB_DSTB_L_N<br />
FSB_DINV_L<br />
FSB_DSTB_L_P<br />
FSB_DSTB_L_N<br />
FSB_DINV_L<br />
FSB_DSTB_L_P<br />
FSB_DSTB_L_N<br />
FSB_DINV_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_A_L<br />
FSB_ADSTB_L<br />
FSB_ADSTB_L<br />
FSB_REQ_L<br />
FSB_REQ_L<br />
FSB_REQ_L<br />
FSB_REQ_L<br />
FSB_REQ_L<br />
CPU_PECI_MCP<br />
CPU_PROCHOT_L<br />
(MCP_BSEL)<br />
(MCP_BSEL)<br />
(MCP_BSEL)<br />
FSB_RS_L<br />
FSB_RS_L<br />
FSB_RS_L<br />
PP1V05_S0_MCP_PLL_FSB<br />
270 mA (A01) 206 mA<br />
20 mA<br />
29 mA<br />
15 mA<br />
73B3 MCP_BCLK_VML_COMP_VDD<br />
73B3 MCP_BCLK_VML_COMP_GND<br />
73B3 MCP_CPU_COMP_VCC<br />
73B3 MCP_CPU_COMP_GND<br />
T40 CPU_DSTBP0#<br />
U40 CPU_DSTBN0#<br />
V41 CPU_DBI0#<br />
W39 CPU_DSTBP1#<br />
W37 CPU_DSTBN1#<br />
V35 CPU_DBI1#<br />
N37 CPU_DSTBP2#<br />
L36 CPU_DSTBN2#<br />
N35 CPU_DBI2#<br />
M39 CPU_DSTBP3#<br />
M41 CPU_DSTBN3#<br />
J41 CPU_DBI3#<br />
AC34 CPU_A3#<br />
AE38 CPU_A4#<br />
AE34 CPU_A5#<br />
AC37 CPU_A6#<br />
AE37 CPU_A7#<br />
AE35 CPU_A8#<br />
AB35 CPU_A9#<br />
AF35 CPU_A10#<br />
AG35 CPU_A11#<br />
AG39 CPU_A12#<br />
AE33 CPU_A13#<br />
AG37 CPU_A14#<br />
AG38 CPU_A15#<br />
AG34 CPU_A16#<br />
AN38 CPU_A17#<br />
AL39 CPU_A18#<br />
AG33 CPU_A19#<br />
AL33 CPU_A20#<br />
AJ33 CPU_A21#<br />
AN36 CPU_A22#<br />
AJ35 CPU_A23#<br />
AJ37 CPU_A24#<br />
AJ36 CPU_A25#<br />
AJ38 CPU_A26#<br />
AL37 CPU_A27#<br />
AL34 CPU_A28#<br />
AN37 CPU_A29#<br />
AJ34 CPU_A30#<br />
AL38 CPU_A31#<br />
AL35 CPU_A32#<br />
AN34 CPU_A33#<br />
AR39 CPU_A34#<br />
AN35 CPU_A35#<br />
AE36 CPU_ADSTB0#<br />
AK35 CPU_ADSTB1#<br />
AC38 CPU_REQ0#<br />
AA33 CPU_REQ1#<br />
AC39 CPU_REQ2#<br />
AC33 CPU_REQ3#<br />
AC35 CPU_REQ4#<br />
AD42 CPU_ADS#<br />
AD43 CPU_BNR#<br />
AE40 CPU_BR0#<br />
AL32 CPU_BR1#<br />
AD39 CPU_DBSY#<br />
AD41 CPU_DRDY#<br />
AB42 CPU_HIT#<br />
AD40 CPU_HITM#<br />
AC43 CPU_LOCK#<br />
AE41 CPU_TRDY#<br />
E41 CPU_PECI<br />
AJ41 CPU_PROCHOT#<br />
AG43 CPU_THERMTRIP#<br />
AH40 CPU_FERR#<br />
F42 CPU_BSEL2<br />
D42 CPU_BSEL1<br />
F41 CPU_BSEL0<br />
AC41 CPU_RS0#<br />
AB41 CPU_RS1#<br />
AC42 CPU_RS2#<br />
FSB<br />
AG27 +V_DLL_DLCELL_AVDD<br />
AH27 +V_PLL_MCLK<br />
AG28 +V_PLL_FSB<br />
AH28 +V_PLL_CPU<br />
AM43 CPU_COMP_VCC<br />
AM42 CPU_COMP_GND<br />
CPU_D0# Y43<br />
CPU_D1# W42<br />
CPU_D2# Y40<br />
CPU_D3# W41<br />
CPU_D4# Y39<br />
CPU_D5# V42<br />
CPU_D6# Y41<br />
CPU_D7# Y42<br />
CPU_D8# P42<br />
CPU_D9# U41<br />
CPU_D10# R42<br />
CPU_D11# T39<br />
CPU_D12# T42<br />
CPU_D13# T41<br />
CPU_D14# R41<br />
CPU_D15# T43<br />
CPU_D16# W35<br />
CPU_D17# AA37<br />
CPU_D18# W33<br />
CPU_D19# W34<br />
CPU_D20# AA36<br />
CPU_D21# AA34<br />
CPU_D22# AA38<br />
CPU_D23# AA35<br />
CPU_D24# U38<br />
CPU_D25# U36<br />
CPU_D26# U35<br />
CPU_D27# U33<br />
CPU_D28# U34<br />
CPU_D29# W38<br />
CPU_D30# R33<br />
CPU_D31# U37<br />
CPU_D32# N34<br />
CPU_D33# N33<br />
CPU_D34# R34<br />
CPU_D35# R35<br />
CPU_D36# P35<br />
CPU_D37# R39<br />
CPU_D38# R37<br />
CPU_D39# R38<br />
CPU_D40# L37<br />
CPU_D41# L39<br />
CPU_D42# L38<br />
CPU_D43# N36<br />
CPU_D44# N38<br />
CPU_D45# J39<br />
CPU_D46# J38<br />
CPU_D47# J37<br />
CPU_D48# L42<br />
CPU_D49# M42<br />
CPU_D50# P41<br />
CPU_D51# N41<br />
CPU_D52# N40<br />
CPU_D53# M40<br />
CPU_D54# H40<br />
CPU_D55# K42<br />
CPU_D56# H41<br />
CPU_D57# L41<br />
CPU_D58# H43<br />
CPU_D59# H42<br />
CPU_D60# K41<br />
CPU_D61# J40<br />
CPU_D62# H39<br />
CPU_D63# M43<br />
CPU_BPRI# AA41<br />
CPU_DEFER# AA40<br />
BCLK_OUT_ITP_P AL43<br />
BCLK_OUT_ITP_N AL42<br />
CPU_A20M# AF41<br />
CPU_IGNNE# AH39<br />
CPU_INIT# AH42<br />
CPU_INTR AF42<br />
CPU_NMI AG41<br />
CPU_SMI# AH41<br />
CPU_SLP# AM33<br />
CPU_DPSLP# AN33<br />
CPU_DPWR# AM32<br />
CPU_STPCLK# AG42<br />
CPU_DPRSTP# AN32<br />
8 7 6 5 4 3 2 1<br />
OMIT<br />
U1400<br />
MCP79-TOPO-B<br />
BGA<br />
(1 OF 11)<br />
AM39 BCLK_VML_COMP_VDD<br />
AM40 BCLK_VML_COMP_GND<br />
BCLK_OUT_CPU_P G42<br />
BCLK_OUT_CPU_N G41<br />
BCLK_OUT_NB_P AL41<br />
BCLK_OUT_NB_N AK42<br />
BCLK_IN_N AK41<br />
BCLK_IN_P AJ40<br />
CPU_PWRGD AH43<br />
CPU_RESET# H38<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_D_L<br />
FSB_BPRI_L<br />
FSB_DEFER_L<br />
FSB_CLK_CPU_P<br />
FSB_CLK_CPU_N<br />
FSB_CLK_ITP_P<br />
FSB_CLK_ITP_N<br />
73B3 FSB_CLK_MCP_P<br />
73B3 FSB_CLK_MCP_N<br />
CPU_A20M_L<br />
CPU_IGNNE_L<br />
CPU_INIT_L<br />
CPU_INTR<br />
CPU_NMI<br />
CPU_SMI_L<br />
CPU_PWRGD<br />
FSB_CPURST_L<br />
FSB_CPUSLP_L<br />
CPU_DPSLP_L<br />
FSB_DPWR_L<br />
CPU_STPCLK_L<br />
CPU_DPRSTP_L<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9C4 73D3<br />
9B4 73D3<br />
9B4 73D3<br />
9B4 73D3<br />
9B4 73D3<br />
9B4 73D3<br />
9B4 73D3<br />
9B4 73D3<br />
9B4 73D3<br />
9B4 73D3<br />
9B4 73D3<br />
9B4 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9C2 73D3<br />
9B2 73D3<br />
9B2 73D3<br />
9B2 73D3<br />
9B2 73D3<br />
9B2 73D3<br />
9B2 73D3<br />
9B2 73D3<br />
9B2 73D3<br />
9B2 73D3<br />
9B2 73D3<br />
9B2 73D3<br />
9D6 73C3<br />
9D6 73C3<br />
9B6 73B3<br />
9B6 73B3<br />
12C3 73B3<br />
12C3 73B3<br />
Loop-back clock for delay matching.<br />
9C8 73C3<br />
9C8 73C3<br />
9D6 73C3<br />
9C8 73C3<br />
9B8 73C3<br />
9B8 73B3<br />
9D6 12C2 73C3<br />
9B2 73B3<br />
9B2 73B3<br />
9B2 73B3<br />
9C8 73B3<br />
9B2 62C7 73B3<br />
NO STUFF<br />
1<br />
R1440<br />
150<br />
2<br />
=PP1V05_S0_MCP_FSB<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
OUT<br />
9B2 12C7 73C3<br />
7D7 13B7 21D3 22C8<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
APPLE INC.<br />
MCP CPU Interface<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
SYNC_DATE=04/04/2008<br />
OF<br />
13 81<br />
REV.<br />
4.7.0<br />
D<br />
C<br />
B<br />
A
8 7 6 5 4 3 2 1<br />
OMIT<br />
OMIT<br />
U1400<br />
MCP79-TOPO-B<br />
BGA<br />
U1400<br />
MCP79-TOPO-B<br />
BGA<br />
(2 OF 11)<br />
(3 OF 11)<br />
D<br />
C<br />
B<br />
74D3 26A5<br />
74D3 26A5<br />
74D3 26B7<br />
74D3 26A7<br />
74D3 26A7<br />
74D3 26A7<br />
74D3 26B5<br />
74D3 26B5<br />
74D3 26B5<br />
74D3 26B7<br />
74D3 26B5<br />
74D3 26B7<br />
74D3 26B7<br />
74D3 26B5<br />
74D3 26B7<br />
74D3 26B5<br />
74D3 26B7<br />
74D3 26B7<br />
74D3 26B7<br />
74D3 26B7<br />
74D3 26B5<br />
74D3 26B5<br />
74D3 26B5<br />
74D3 26B5<br />
74D3 26B5<br />
74D3 26B7<br />
74D3 26C5<br />
74D3 26B5<br />
74D3 26B5<br />
74D3 26B7<br />
74D3 26B7<br />
74D3 26C7<br />
74D3 26C2<br />
74D3 26C4<br />
74D3 26C2<br />
74D3 26C2<br />
74D3 26C2<br />
74D3 26C4<br />
74D3 26C4<br />
74D3 26C4<br />
74D3 26B4<br />
74D3 26B2<br />
74D3 26C4<br />
74D3 26C4<br />
74D3 26B2<br />
74D3 26C2<br />
74D3 26C2<br />
74D3 26B4<br />
74D3 26C4<br />
74D3 26C2<br />
74D3 26C2<br />
74D3 26C4<br />
74D3 26C2<br />
74D3 26C4<br />
74D3 26C2<br />
74D3 26C4<br />
74D3 26C4<br />
74D3 26C4<br />
74D3 26D2<br />
74D3 26D2<br />
74D3 26C2<br />
74D3 26C2<br />
74D3 26D4<br />
74D3 26D4<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
AL8 MDQ0_63<br />
AL9 MDQ0_62<br />
AP9 MDQ0_61<br />
AN9 MDQ0_60<br />
AL6 MDQ0_59<br />
AL7 MDQ0_58<br />
AN6 MDQ0_57<br />
AN7 MDQ0_56<br />
AR6 MDQ0_55<br />
AR7 MDQ0_54<br />
AV6 MDQ0_53<br />
AW5 MDQ0_52<br />
AN10 MDQ0_51<br />
AR5 MDQ0_50<br />
AU6 MDQ0_49<br />
AV5 MDQ0_48<br />
AU7 MDQ0_47<br />
AU8 MDQ0_46<br />
AW9 MDQ0_45<br />
AP11 MDQ0_44<br />
AW6 MDQ0_43<br />
AY5 MDQ0_42<br />
AU9 MDQ0_41<br />
AV9 MDQ0_40<br />
AU11 MDQ0_39<br />
AV11 MDQ0_38<br />
AV13 MDQ0_37<br />
AW13 MDQ0_36<br />
AR11 MDQ0_35<br />
AT11 MDQ0_34<br />
AR14 MDQ0_33<br />
AU13 MDQ0_32<br />
AR26 MDQ0_31<br />
AU25 MDQ0_30<br />
AT27 MDQ0_29<br />
AU27 MDQ0_28<br />
AP25 MDQ0_27<br />
AR25 MDQ0_26<br />
AP27 MDQ0_25<br />
AR27 MDQ0_24<br />
AP29 MDQ0_23<br />
AR29 MDQ0_22<br />
AP31 MDQ0_21<br />
AR31 MDQ0_20<br />
AV27 MDQ0_19<br />
AN29 MDQ0_18<br />
AV29 MDQ0_17<br />
AN31 MDQ0_16<br />
AU31 MDQ0_15<br />
AR33 MDQ0_14<br />
AV37 MDQ0_13<br />
AW37 MDQ0_12<br />
AT31 MDQ0_11<br />
AV31 MDQ0_10<br />
AT37 MDQ0_9<br />
AU37 MDQ0_8<br />
AW39 MDQ0_7<br />
AV39 MDQ0_6<br />
AR37 MDQ0_5<br />
AR38 MDQ0_4<br />
AV38 MDQ0_3<br />
AW38 MDQ0_2<br />
AR35 MDQ0_1<br />
AP35 MDQ0_0<br />
MEMORY PARTITION 0<br />
MDQS0_7_P AL10<br />
MDQS0_7_N AL11<br />
MDQS0_6_P AR8<br />
MDQS0_6_N AR9<br />
MDQS0_5_P AW7<br />
MDQS0_5_N AW8<br />
MDQS0_4_P AP13<br />
MDQS0_4_N AR13<br />
MDQS0_3_P AV25<br />
MDQS0_3_N AW25<br />
MDQS0_2_P AU30<br />
MDQS0_2_N AU29<br />
MDQS0_1_P AT35<br />
MDQS0_1_N AU35<br />
MDQS0_0_P AU39<br />
MDQS0_0_N AT39<br />
MRAS0# AV17<br />
MCAS0# AP17<br />
MWE0# AR17<br />
MBA0_2 AP23<br />
MBA0_1 AP19<br />
MBA0_0 AW17<br />
MA0_14 AR23<br />
MA0_13 AU15<br />
MA0_12 AN23<br />
MA0_11 AW21<br />
MA0_10 AN19<br />
MA0_9 AV21<br />
MA0_8 AR22<br />
MA0_7 AU21<br />
MA0_6 AP21<br />
MA0_5 AR21<br />
MA0_4 AN21<br />
MA0_3 AV19<br />
MA0_2 AU19<br />
MA0_1 AT19<br />
MA0_0 AR19<br />
MEMORY<br />
CONTROL<br />
0A<br />
MCLK0A_2_P<br />
MCLK0A_2_N<br />
AW33<br />
AV33<br />
MCLK0A_1_P BA24<br />
MCLK0A_1_N AY24<br />
MCLK0A_0_P BB20<br />
MCLK0A_0_N BC20<br />
MEM_A_DQS_P<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQS_N<br />
MEM_A_RAS_L<br />
MEM_A_CAS_L<br />
MEM_A_WE_L<br />
MEM_A_BA<br />
MEM_A_BA<br />
MEM_A_BA<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
TP_MEM_A_CLK2P<br />
TP_MEM_A_CLK2N<br />
MEM_A_CLK_P<br />
MEM_A_CLK_N<br />
MEM_A_CLK_P<br />
MEM_A_CLK_N<br />
BI 26A5 74C3<br />
BI 26A5 74C3<br />
BI 26B7 74C3<br />
BI 26B7 74C3<br />
BI 26B5 74C3<br />
BI 26B5 74C3<br />
BI 26B7 74C3<br />
BI 26B7 74C3<br />
BI 26C4 74C3<br />
BI 26C4 74C3<br />
BI 26B2 74C3<br />
BI 26C2 74C3<br />
BI 26C4 74C3<br />
BI 26C4 74C3<br />
BI 26C2 74C3<br />
BI 26D2 74C3<br />
OUT 26C5 74D3<br />
OUT 26C7 74D3<br />
OUT 26C7 74D3<br />
OUT 26C7 74D3<br />
OUT 26C5 74D3<br />
OUT 26C7 74D3<br />
OUT 26C5 74D3<br />
OUT 26C7 74D3<br />
OUT 26C7 74D3<br />
OUT 26C5 74D3<br />
OUT 26C7 74D3<br />
OUT 26C7 74D3<br />
OUT 26C7 74D3<br />
OUT 26C5 74D3<br />
OUT 26C5 74D3<br />
OUT 26C7 74D3<br />
OUT 26C5 74D3<br />
OUT 26C7 74D3<br />
OUT 26C5 74D3<br />
OUT 26C7 74D3<br />
OUT 26C5 74D3<br />
OUT 26C5 74D3<br />
OUT 26C5 74D3<br />
OUT 26C7 74D3<br />
OUT 26C7 74D3<br />
74B3 27B5<br />
74B3 27A5<br />
74B3 27A7<br />
74B3 27A7<br />
74B3 27B5<br />
74B3 27A7<br />
74B3 27A5<br />
74B3 27B7<br />
74B3 27B7<br />
74B3 27B7<br />
74B3 27B7<br />
74B3 27B5<br />
74B3 27B5<br />
74B3 27B5<br />
74B3 27B7<br />
74B3 27B5<br />
74B3 27B7<br />
74B3 27B7<br />
74B3 27B7<br />
74B3 27B5<br />
74B3 27B5<br />
74B3 27B5<br />
74B3 27B7<br />
74B3 27B5<br />
74B3 27B7<br />
74B3 27B5<br />
74B3 27C7<br />
74B3 27C5<br />
74B3 27B7<br />
74B3 27B5<br />
74B3 27B5<br />
74B3 27B7<br />
74B3 27B4<br />
74B3 27B2<br />
74B3 27C2<br />
74B3 27C4<br />
74B3 27B2<br />
74B3 27B4<br />
74B3 27C2<br />
74B3 27C4<br />
74B3 27C2<br />
74B3 27C4<br />
74B3 27C2<br />
74B3 27C4<br />
74B3 27C4<br />
74B3 27C2<br />
74B3 27C4<br />
74B3 27C2<br />
74B3 27C4<br />
74B3 27C4<br />
74B3 27C4<br />
74B3 27C2<br />
74B3 27C2<br />
74B3 27C4<br />
74B3 27C2<br />
74B3 27C2<br />
74B3 27C2<br />
74B3 27C4<br />
74B3 27D2<br />
74B3 27D2<br />
74B3 27C4<br />
74B3 27C2<br />
74B3 27D4<br />
74B3 27D4<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
AT4 MDQ1_63<br />
AT3 MDQ1_62<br />
AV2 MDQ1_61<br />
AV3 MDQ1_60<br />
AR4 MDQ1_59<br />
AR3 MDQ1_58<br />
AU2 MDQ1_57<br />
AU3 MDQ1_56<br />
AY4 MDQ1_55<br />
AY3 MDQ1_54<br />
BB3 MDQ1_53<br />
BC3 MDQ1_52<br />
AW4 MDQ1_51<br />
AW3 MDQ1_50<br />
BA3 MDQ1_49<br />
BB2 MDQ1_48<br />
BB5 MDQ1_47<br />
BA5 MDQ1_46<br />
BA8 MDQ1_45<br />
BC8 MDQ1_44<br />
BB4 MDQ1_43<br />
BC4 MDQ1_42<br />
BA7 MDQ1_41<br />
AY8 MDQ1_40<br />
BA9 MDQ1_39<br />
BB10 MDQ1_38<br />
BB12 MDQ1_37<br />
AW12 MDQ1_36<br />
BB8 MDQ1_35<br />
BB9 MDQ1_34<br />
AY12 MDQ1_33<br />
BA12 MDQ1_32<br />
BC32 MDQ1_31<br />
AW32 MDQ1_30<br />
BA35 MDQ1_29<br />
AY36 MDQ1_28<br />
BA32 MDQ1_27<br />
BB32 MDQ1_26<br />
BA34 MDQ1_25<br />
AY35 MDQ1_24<br />
BC36 MDQ1_23<br />
AW36 MDQ1_22<br />
BA39 MDQ1_21<br />
AY40 MDQ1_20<br />
BA36 MDQ1_19<br />
BB36 MDQ1_18<br />
BA38 MDQ1_17<br />
AY39 MDQ1_16<br />
BB40 MDQ1_15<br />
AW40 MDQ1_14<br />
AV42 MDQ1_13<br />
AV41 MDQ1_12<br />
BA40 MDQ1_11<br />
BC40 MDQ1_10<br />
AW42 MDQ1_9<br />
AW41 MDQ1_8<br />
AT40 MDQ1_7<br />
AT41 MDQ1_6<br />
AP41 MDQ1_5<br />
AN40 MDQ1_4<br />
AU40 MDQ1_3<br />
AU41 MDQ1_2<br />
AR41 MDQ1_1<br />
AP42 MDQ1_0<br />
MEMORY PARTITION 1<br />
MDQS1_7_P AT2<br />
MDQS1_7_N AT1<br />
MDQS1_6_P AY2<br />
MDQS1_6_N AY1<br />
MDQS1_5_P BB6<br />
MDQS1_5_N BA6<br />
MDQS1_4_P BA10<br />
MDQS1_4_N AY11<br />
MDQS1_3_P BB33<br />
MDQS1_3_N BA33<br />
MDQS1_2_P BB37<br />
MDQS1_2_N BA37<br />
MDQS1_1_P BA43<br />
MDQS1_1_N AY42<br />
MDQS1_0_P AT42<br />
MDQS1_0_N AT43<br />
MRAS1# AW16<br />
MCAS1# BA15<br />
MWE1# BA16<br />
MBA1_2 BB29<br />
MBA1_1 BB18<br />
MBA1_0 BB17<br />
MA1_14 BA29<br />
MA1_13 BA14<br />
MA1_12 AW28<br />
MA1_11 BC28<br />
MA1_10 BA17<br />
MA1_9 BB28<br />
MA1_8 AY28<br />
MA1_7 BA28<br />
MA1_6 AY27<br />
MA1_5 BA27<br />
MA1_4 BA26<br />
MA1_3 BB26<br />
MA1_2 BA25<br />
MA1_1 BB25<br />
MA1_0 BA18<br />
MEMORY<br />
CONTROL<br />
1A<br />
MCLK1A_2_P<br />
MCLK1A_2_N<br />
BA42<br />
BB42<br />
MCLK1A_1_P BB22<br />
MCLK1A_1_N BA22<br />
MCLK1A_0_P BA19<br />
MCLK1A_0_N AY19<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_RAS_L<br />
MEM_B_CAS_L<br />
MEM_B_WE_L<br />
MEM_B_BA<br />
MEM_B_BA<br />
MEM_B_BA<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
TP_MEM_B_CLK2P<br />
TP_MEM_B_CLK2N<br />
MEM_B_CLK_P<br />
MEM_B_CLK_N<br />
MEM_B_CLK_P<br />
MEM_B_CLK_N<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
27A5 74A3<br />
27A5 74A3<br />
27B7 74A3<br />
27B7 74A3<br />
27B5 74A3<br />
27B5 74A3<br />
27B7 74A3<br />
27B7 74A3<br />
27B2 74A3<br />
27C2 74A3<br />
27C4 74A3<br />
27C4 74A3<br />
27C4 74A3<br />
27C4 74A3<br />
27C2 74A3<br />
27D2 74A3<br />
27C5 74B3<br />
27C7 74B3<br />
27C7 74B3<br />
27C7 74B3<br />
27C5 74B3<br />
27C7 74B3<br />
27C5 74B3<br />
27C7 74B3<br />
27C7 74B3<br />
27C5 74B3<br />
27C7 74B3<br />
27C7 74B3<br />
27C7 74B3<br />
27C5 74B3<br />
27C5 74B3<br />
27C7 74B3<br />
27C5 74B3<br />
27C7 74B3<br />
27C5 74B3<br />
27C7 74B3<br />
27C5 74B3<br />
27C5 74C3<br />
27C5 74C3<br />
27C7 74C3<br />
27C7 74C3<br />
D<br />
C<br />
B<br />
74C3 26A7 OUT<br />
74C3 26B5 OUT<br />
74C3 26B7 OUT<br />
74C3 26B5 OUT<br />
74C3 26C2 OUT<br />
74C3 26B4 OUT<br />
74C3 26C2 OUT<br />
74D3 26C4 OUT<br />
MEM_A_DM<br />
MEM_A_DM<br />
MEM_A_DM<br />
MEM_A_DM<br />
MEM_A_DM<br />
MEM_A_DM<br />
MEM_A_DM<br />
MEM_A_DM<br />
AN5 MDQM0_7<br />
AU5 MDQM0_6<br />
AR10 MDQM0_5<br />
AN13 MDQM0_4<br />
AN27 MDQM0_3<br />
AW29 MDQM0_2<br />
AV35 MDQM0_1<br />
AR34 MDQM0_0<br />
MCS0A_1# AT15<br />
MCS0A_0# AR18<br />
MODT0A_1 AP15<br />
MODT0A_0 AV15<br />
MCKE0A_1 AU23<br />
MCKE0A_0 AT23<br />
MEM_A_CS_L<br />
MEM_A_CS_L<br />
MEM_A_ODT<br />
MEM_A_ODT<br />
MEM_A_CKE<br />
MEM_A_CKE<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
26C7 74D3<br />
26C5 74D3<br />
26C5 74D3<br />
26C5 74D3<br />
26D5 74D3<br />
26D7 74D3<br />
74B3 27A7 OUT<br />
74B3 27B5 OUT<br />
74B3 27B7 OUT<br />
74B3 27B5 OUT<br />
74B3 27B4 OUT<br />
74B3 27C2 OUT<br />
74B3 27C2 OUT<br />
74B3 27C4 OUT<br />
MEM_B_DM<br />
MEM_B_DM<br />
MEM_B_DM<br />
MEM_B_DM<br />
MEM_B_DM<br />
MEM_B_DM<br />
MEM_B_DM<br />
MEM_B_DM<br />
AT5 MDQM1_7<br />
BA2 MDQM1_6<br />
AY7 MDQM1_5<br />
BA11 MDQM1_4<br />
BB34 MDQM1_3<br />
BB38 MDQM1_2<br />
AY43 MDQM1_1<br />
AR42 MDQM1_0<br />
MCS1A_1# BB14<br />
MCS1A_0# BB16<br />
MODT1A_1 BB13<br />
MODT1A_0 AY15<br />
MCKE1A_1 AY31<br />
MCKE1A_0 BB30<br />
MEM_B_CS_L<br />
MEM_B_CS_L<br />
MEM_B_ODT<br />
MEM_B_ODT<br />
MEM_B_CKE<br />
MEM_B_CKE<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
27C7 74B3<br />
27C5 74B3<br />
27C5 74B3<br />
27C5 74B3<br />
27D5 74B3<br />
27D7 74B3<br />
A<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
MCP Memory Interface<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=04/04/2008<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
14<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
OMIT<br />
U1400<br />
MCP79-TOPO-B<br />
BGA<br />
(4 OF 11)<br />
D<br />
TP_MEM_A_CLK5P<br />
TP_MEM_A_CLK5N<br />
TP_MEM_A_CLK4P<br />
TP_MEM_A_CLK4N<br />
TP_MEM_A_CLK3P<br />
TP_MEM_A_CLK3N<br />
TP_MEM_A_CS_L<br />
TP_MEM_A_CS_L<br />
TP_MEM_A_ODT<br />
TP_MEM_A_ODT<br />
TP_MEM_A_CKE<br />
TP_MEM_A_CKE<br />
AU33 MCLK0B_2_P<br />
AU34 MCLK0B_2_N<br />
BB24 MCLK0B_1_P<br />
BC24 MCLK0B_1_N<br />
BA21 MCLK0B_0_P<br />
BB21 MCLK0B_0_N<br />
AU17 MCS0B_0#<br />
AR15 MCS0B_1#<br />
AN17 MODT0B_0<br />
AN15 MODT0B_1<br />
AV23 MCKE0B_0<br />
AN25 MCKE0B_1<br />
MEMORY CONTROL 0B<br />
MEMORY CONTROL 1B<br />
MCLK1B_2_P BA41<br />
MCLK1B_2_N BB41<br />
MCLK1B_1_P AY23<br />
MCLK1B_1_N BA23<br />
MCLK1B_0_P BA20<br />
MCLK1B_0_N AY20<br />
MCS1B_0# BC16<br />
MCS1B_1# BA13<br />
MODT1B_0 AY16<br />
MODT1B_1 BC13<br />
MCKE1B_0 BA30<br />
MCKE1B_1 BA31<br />
TP_MEM_B_CLK5P<br />
TP_MEM_B_CLK5N<br />
TP_MEM_B_CLK4P<br />
TP_MEM_B_CLK4N<br />
TP_MEM_B_CLK3P<br />
TP_MEM_B_CLK3N<br />
TP_MEM_B_CS_L<br />
TP_MEM_B_CS_L<br />
TP_MEM_B_ODT<br />
TP_MEM_B_ODT<br />
TP_MEM_B_CKE<br />
TP_MEM_B_CKE<br />
D<br />
22C8 15C3 7B6<br />
=PP1V8R1V5_S0_MCP_MEM<br />
R1610<br />
40.2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
2<br />
22B2 PP1V05_S0_MCP_PLL_CORE<br />
87 mA (A01)<br />
17 mA<br />
12 mA<br />
19 mA<br />
39 mA<br />
T27 +V_PLL_XREF_XS<br />
U28 +V_PLL_DP<br />
U27 +V_PLL_CORE<br />
T28 +V_VPLL<br />
MRESET0#<br />
AY32<br />
MCP_MEM_RESET_L<br />
TP or NC for DDR2.<br />
OUT<br />
28C6<br />
C<br />
B<br />
A<br />
1<br />
R1611<br />
40.2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
74A3 MCP_MEM_COMP_VDD<br />
74A3 MCP_MEM_COMP_GND<br />
AN41 MEM_COMP_VDD<br />
AM41 MEM_COMP_GND<br />
AA22 GND1<br />
AP12 GND2<br />
G30 GND3<br />
P10 GND4<br />
T10 GND5<br />
T6 GND6<br />
V10 GND7<br />
V34 GND8<br />
W5 GND9<br />
AA39 GND10<br />
AB22 GND11<br />
AB7 GND12<br />
AD22 GND13<br />
AE20 GND14<br />
AF24 GND15<br />
AG24 GND16<br />
AH35 GND17<br />
AK7 GND18<br />
AM28 GND19<br />
AT25 GND20<br />
AP30 GND21<br />
AR36 GND22<br />
AU10 GND23<br />
F28 GND24<br />
BC21 GND25<br />
AY9 GND26<br />
BC9 GND27<br />
D34 GND28<br />
F24 GND29<br />
G32 GND30<br />
H31 GND31<br />
K7 GND32<br />
M38 GND33<br />
M5 GND34<br />
M6 GND35<br />
M7 GND36<br />
M9 GND37<br />
N39 GND38<br />
N8 GND39<br />
P33 GND40<br />
P34 GND41<br />
P37 GND42<br />
P4 GND43<br />
P40 GND44<br />
P7 GND45<br />
R36 GND46<br />
R40 GND47<br />
R43 GND48<br />
R5 GND49<br />
T18 GND50<br />
T20 GND51<br />
AK11 GND52<br />
T24 GND53<br />
T26 GND54<br />
+VDD_MEM1 AM17<br />
+VDD_MEM2 AM19<br />
+VDD_MEM3 AM21<br />
+VDD_MEM4 AM23<br />
+VDD_MEM5 AM25<br />
+VDD_MEM6 AM27<br />
+VDD_MEM7 AM29<br />
+VDD_MEM8 AN16<br />
+VDD_MEM9 BC29<br />
+VDD_MEM10 AN20<br />
+VDD_MEM11 AN24<br />
+VDD_MEM12 AT17<br />
+VDD_MEM13 AP16<br />
+VDD_MEM14 AN22<br />
+VDD_MEM15 AP20<br />
+VDD_MEM16 AP24<br />
+VDD_MEM17 AV16<br />
+VDD_MEM18 AR16<br />
+VDD_MEM19 AR20<br />
+VDD_MEM20 AR24<br />
+VDD_MEM21 AW15<br />
+VDD_MEM22 AP22<br />
+VDD_MEM23 AP18<br />
+VDD_MEM24 AU16<br />
+VDD_MEM25 AN18<br />
+VDD_MEM26 AU24<br />
+VDD_MEM27 AT21<br />
+VDD_MEM28 AY29<br />
+VDD_MEM29 AV24<br />
+VDD_MEM30 AU20<br />
+VDD_MEM31 AU22<br />
+VDD_MEM32 AW27<br />
+VDD_MEM33 BC17<br />
+VDD_MEM34 AV20<br />
+VDD_MEM35 AY17<br />
+VDD_MEM36 AY18<br />
+VDD_MEM37 AM15<br />
+VDD_MEM38 AU18<br />
+VDD_MEM39 AY25<br />
+VDD_MEM40 AY26<br />
+VDD_MEM41 AW19<br />
+VDD_MEM42 AW24<br />
+VDD_MEM43 BC25<br />
+VDD_MEM44 AL30<br />
+VDD_MEM45 AM31<br />
GND55 T33<br />
GND56 T34<br />
GND57 T35<br />
GND58 T37<br />
GND59 T38<br />
GND60 T7<br />
GND61 T9<br />
GND62 U18<br />
GND63 U20<br />
GND64 U22<br />
=PP1V8R1V5_S0_MCP_MEM<br />
7B6 15C7 22C8<br />
4771 mA (A01, DDR3)<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
MCP Memory Misc<br />
NOTICE OF PROPRIETARY PROPERTY<br />
SYNC_DATE=04/04/2008<br />
C<br />
B<br />
A<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).<br />
8 7 6 5 4 3 2 1<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
15<br />
81
8 7 6 5 4 3 2 1<br />
OMIT<br />
U1400<br />
MCP79-TOPO-B<br />
BGA<br />
(5 OF 11)<br />
D<br />
C<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
=PEG_D2R_P<br />
=PEG_D2R_N<br />
=PEG_D2R_P<br />
=PEG_D2R_N<br />
=PEG_D2R_P<br />
=PEG_D2R_N<br />
=PEG_D2R_P<br />
=PEG_D2R_N<br />
=PEG_D2R_P<br />
=PEG_D2R_N<br />
=PEG_D2R_P<br />
=PEG_D2R_N<br />
=PEG_D2R_P<br />
=PEG_D2R_N<br />
=PEG_D2R_P<br />
=PEG_D2R_N<br />
=PEG_D2R_P<br />
=PEG_D2R_N<br />
=PEG_D2R_P<br />
=PEG_D2R_N<br />
=PEG_D2R_P<br />
=PEG_D2R_N<br />
=PEG_D2R_P<br />
=PEG_D2R_N<br />
=PEG_D2R_P<br />
=PEG_D2R_N<br />
=PEG_D2R_P<br />
=PEG_D2R_N<br />
=PEG_D2R_P<br />
=PEG_D2R_N<br />
=PEG_D2R_P<br />
=PEG_D2R_N<br />
PEG_PRSNT_L<br />
F7 PE0_RX0_P<br />
E7 PE0_RX0_N<br />
D7 PE0_RX1_P<br />
C7 PE0_RX1_N<br />
E6 PE0_RX2_P<br />
F6 PE0_RX2_N<br />
E5 PE0_RX3_P<br />
F5 PE0_RX3_N<br />
E4 PE0_RX4_P<br />
E3 PE0_RX4_N<br />
C3 PE0_RX5_P<br />
D3 PE0_RX5_N<br />
G5 PE0_RX6_P<br />
H5 PE0_RX6_N<br />
J7 PE0_RX7_P<br />
J6 PE0_RX7_N<br />
J5 PE0_RX8_P<br />
J4 PE0_RX8_N<br />
L11 PE0_RX9_P<br />
L10 PE0_RX9_N<br />
L9 PE0_RX10_P<br />
L8 PE0_RX10_N<br />
L7 PE0_RX11_P<br />
L6 PE0_RX11_N<br />
N11 PE0_RX12_P<br />
N10 PE0_RX12_N<br />
N9 PE0_RX13_P<br />
P9 PE0_RX13_N<br />
N7 PE0_RX14_P<br />
N6 PE0_RX14_N<br />
N5 PE0_RX15_P<br />
N4 PE0_RX15_N<br />
Int PU<br />
C9 PE0_PRSNT_16#<br />
PCI EXPRESS<br />
PE0_TX0_P C5<br />
PE0_TX0_N D4<br />
PE0_TX1_P C4<br />
PE0_TX1_N B4<br />
PE0_TX2_P A4<br />
PE0_TX2_N A3<br />
PE0_TX3_P B3<br />
PE0_TX3_N B2<br />
PE0_TX4_P C1<br />
PE0_TX4_N D1<br />
PE0_TX5_P D2<br />
PE0_TX5_N E1<br />
PE0_TX6_P E2<br />
PE0_TX6_N F2<br />
PE0_TX7_P F3<br />
PE0_TX7_N F4<br />
PE0_TX8_P G3<br />
PE0_TX8_N H4<br />
PE0_TX9_P H3<br />
PE0_TX9_N H2<br />
PE0_TX10_P H1<br />
PE0_TX10_N J1<br />
PE0_TX11_P J2<br />
PE0_TX11_N J3<br />
PE0_TX12_P K2<br />
PE0_TX12_N K3<br />
PE0_TX13_P L4<br />
PE0_TX13_N L3<br />
PE0_TX14_P M4<br />
PE0_TX14_N M3<br />
PE0_TX15_P M2<br />
PE0_TX15_N M1<br />
PE0_REFCLK_P E11<br />
PE0_REFCLK_N D11<br />
=PEG_R2D_C_P<br />
=PEG_R2D_C_N<br />
=PEG_R2D_C_P<br />
=PEG_R2D_C_N<br />
=PEG_R2D_C_P<br />
=PEG_R2D_C_N<br />
=PEG_R2D_C_P<br />
=PEG_R2D_C_N<br />
=PEG_R2D_C_P<br />
=PEG_R2D_C_N<br />
=PEG_R2D_C_P<br />
=PEG_R2D_C_N<br />
=PEG_R2D_C_P<br />
=PEG_R2D_C_N<br />
=PEG_R2D_C_P<br />
=PEG_R2D_C_N<br />
=PEG_R2D_C_P<br />
=PEG_R2D_C_N<br />
=PEG_R2D_C_P<br />
=PEG_R2D_C_N<br />
=PEG_R2D_C_P<br />
=PEG_R2D_C_N<br />
=PEG_R2D_C_P<br />
=PEG_R2D_C_N<br />
=PEG_R2D_C_P<br />
=PEG_R2D_C_N<br />
=PEG_R2D_C_P<br />
=PEG_R2D_C_N<br />
=PEG_R2D_C_P<br />
=PEG_R2D_C_N<br />
=PEG_R2D_C_P<br />
=PEG_R2D_C_N<br />
PEG_CLK100M_P<br />
PEG_CLK100M_N<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
8D6<br />
D<br />
C<br />
29D7<br />
29D7<br />
IN<br />
IN<br />
MINI_CLKREQ_L<br />
PCIE_MINI_PRSNT_L<br />
D5<br />
D9<br />
Int PU<br />
PEB_CLKREQ#/GPIO_49<br />
PEB_PRSNT# Int PU<br />
PE1_REFCLK_P<br />
PE1_REFCLK_N<br />
G11<br />
F11<br />
PCIE_CLK100M_MINI_P<br />
PCIE_CLK100M_MINI_N<br />
OUT<br />
OUT<br />
29C5 75D3<br />
29C5 75D3<br />
35D3<br />
35D3 8C6<br />
IN<br />
IN<br />
FW_CLKREQ_L<br />
PCIE_FW_PRSNT_L<br />
E8<br />
C10<br />
Int PU<br />
PEC_CLKREQ#/GPIO_50<br />
PEC_PRSNT# Int PU<br />
PE2_REFCLK_P<br />
PE2_REFCLK_N<br />
J11<br />
J10<br />
PCIE_CLK100M_FW_P<br />
PCIE_CLK100M_FW_N<br />
OUT<br />
OUT<br />
34C2<br />
34C2<br />
8D6<br />
8D6<br />
IN<br />
IN<br />
EXCARD_CLKREQ_L<br />
PCIE_EXCARD_PRSNT_L<br />
M15<br />
B10<br />
Int PU<br />
PED_CLKREQ#/GPIO_51<br />
PED_PRSNT# Int PU<br />
PE3_REFCLK_P<br />
PE3_REFCLK_N<br />
G13<br />
F13<br />
PCIE_CLK100M_EXCARD_P<br />
PCIE_CLK100M_EXCARD_N<br />
OUT<br />
OUT<br />
8D6<br />
8C6<br />
8C4<br />
30B7<br />
8C4<br />
29C7 6D5<br />
OUT<br />
IN<br />
IN<br />
TP_PE4_CLKREQ_L<br />
TP_PE4_PRSNT_L<br />
57A4 AUD_IP_PERIPHERAL_DET<br />
OUT GMUX_JTAG_TCK_L<br />
CARDREADER_RESET<br />
GMUX_JTAG_TDO<br />
PCIE_WAKE_L<br />
Int PU<br />
L16 PEE_CLKREQ#/GPIO_16<br />
L18 PEE_PRSNT#/GPIO_46<br />
Int PU<br />
Int PU<br />
M16 PEF_CLKREQ#/GPIO_17<br />
M18 PEF_PRSNT#/GPIO_47<br />
Int PU<br />
Int PU<br />
M17 PEG_CLKREQ#/GPIO_18<br />
M19 PEG_PRSNT#/GPIO_48<br />
Int PU<br />
F17 PE_WAKE# Int PU (S5)<br />
PE4_REFCLK_P J13<br />
PE4_REFCLK_N H13<br />
PE5_REFCLK_P L14<br />
PE5_REFCLK_N K14<br />
PE6_REFCLK_P N14<br />
PE6_REFCLK_N M14<br />
PEX_RST0#<br />
K11<br />
TP_PCIE_CLK100M_PE4P<br />
TP_PCIE_CLK100M_PE4N<br />
TP_PCIE_CLK100M_PE5P<br />
TP_PCIE_CLK100M_PE5N<br />
TP_PCIE_CLK100M_PE6P<br />
TP_PCIE_CLK100M_PE6N<br />
PCIE_RESET_L<br />
OUT<br />
24C4<br />
75D3 29C7 6D5<br />
75D3 29C7 6D5<br />
IN<br />
IN<br />
PCIE_MINI_D2R_P<br />
PCIE_MINI_D2R_N<br />
K9<br />
J9<br />
PE1_RX0_P<br />
PE1_RX0_N<br />
PE1_TX0_P<br />
PE1_TX0_N<br />
D8<br />
C8<br />
PCIE_MINI_R2D_C_P<br />
PCIE_MINI_R2D_C_N<br />
OUT<br />
OUT<br />
29C5 75D3<br />
29C5 75D3<br />
B<br />
75D3 34C1<br />
75D3 34C1<br />
8D6<br />
8D6<br />
IN<br />
IN<br />
IN<br />
IN<br />
PCIE_FW_D2R_P<br />
PCIE_FW_D2R_N<br />
PCIE_EXCARD_D2R_P<br />
PCIE_EXCARD_D2R_N<br />
H9<br />
G9<br />
F9<br />
E9<br />
PE1_RX1_P<br />
PE1_RX1_N<br />
PE1_RX2_P<br />
PE1_RX2_N<br />
PE1_TX1_P<br />
PE1_TX1_N<br />
PE1_TX2_P<br />
PE1_TX2_N<br />
B8<br />
A8<br />
A7<br />
B7<br />
PCIE_FW_R2D_C_P<br />
PCIE_FW_R2D_C_N<br />
PCIE_EXCARD_R2D_C_P<br />
PCIE_EXCARD_R2D_C_N<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
34C1 75D3<br />
34C1 75D3<br />
8D6<br />
8D6<br />
B<br />
TP_PCIE_PE4_D2RP<br />
TP_PCIE_PE4_D2RN<br />
H7 PE1_RX3_P<br />
G7 PE1_RX3_N<br />
PE1_TX3_P B6<br />
PE1_TX3_N C6<br />
TP_PCIE_PE4_R2D_CP<br />
TP_PCIE_PE4_R2D_CN<br />
A<br />
7A6 =PP1V05_S0_MCP_PEX_DVDD0<br />
57 mA (A01, DVDD0 & 1)<br />
7A6 =PP1V05_S0_MCP_PEX_DVDD1<br />
22C2 PP1V05_S0_MCP_PLL_PEX<br />
84 mA (A01)<br />
75C3 MCP_PEX_CLK_COMP<br />
NO STUFF<br />
1<br />
R1710<br />
2.37K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
PLACEMENT_NOTE=Place within 12.7mm of U1400<br />
T17 +DVDD0_PEX1<br />
W19 +DVDD0_PEX2<br />
U17 +DVDD0_PEX3<br />
V19 +DVDD0_PEX4<br />
W16 +DVDD0_PEX5<br />
W17 +DVDD0_PEX6<br />
W18 +DVDD0_PEX7<br />
U16 +DVDD0_PEX8<br />
T19 +DVDD1_PEX1<br />
U19 +DVDD1_PEX2<br />
T16<br />
A11<br />
+V_PLL_PEX<br />
PEX_CLK_COMP<br />
+AVDD0_PEX1 Y12<br />
+AVDD0_PEX2 AA12<br />
+AVDD0_PEX3 AB12<br />
+AVDD0_PEX4 M12<br />
+AVDD0_PEX5 P12<br />
+AVDD0_PEX6 R12<br />
+AVDD0_PEX7 N12<br />
+AVDD0_PEX8 T12<br />
+AVDD0_PEX9 U12<br />
+AVDD0_PEX10 AC12<br />
+AVDD0_PEX11 AD12<br />
+AVDD0_PEX12 V12<br />
+AVDD0_PEX13 W12<br />
+AVDD1_PEX1 M13<br />
+AVDD1_PEX2 N13<br />
+AVDD1_PEX3 P13<br />
=PP1V05_S0_MCP_PEX_AVDD0<br />
If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.<br />
If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.<br />
206 mA (A01, AVDD0 & 1)<br />
=PP1V05_S0_MCP_PEX_AVDD1<br />
7A6<br />
7A6<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
MCP PCIe Interfaces<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
SYNC_DATE=04/04/2008<br />
A<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).<br />
8 7 6 5 4 3 2 1<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
16<br />
81
8 7 6 5 4 3 2 1<br />
OMIT<br />
D<br />
C<br />
22B6 22A5 17D3 7B5<br />
19C1 7A3<br />
=PP3V3_ENET_MCP_RMGT<br />
=PP3V3_S5_MCP_GPIO<br />
1<br />
R1810<br />
49.9<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R1811<br />
49.9<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
2<br />
R1820<br />
47K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
2<br />
77D3 31C1<br />
77D3 31C1<br />
77D3 31C1<br />
77D3 31C1<br />
77D3 31C1<br />
77D3 31B1<br />
8C4<br />
8C4<br />
8C4<br />
8D4<br />
8D4<br />
8D4<br />
8D4<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
22A6<br />
OUT<br />
ENET_RXD<br />
ENET_RXD<br />
ENET_RXD<br />
ENET_RXD<br />
ENET_CLK125M_RXCLK<br />
ENET_RX_CTRL<br />
=MCP_MII_RXER<br />
=MCP_MII_COL<br />
=MCP_MII_CRS<br />
TP_ENET_INTR_L<br />
PP1V05_ENET_MCP_PLL_MAC<br />
5 mA (A01)<br />
77D3 MCP_MII_COMP_VDD<br />
77D3 MCP_MII_COMP_GND<br />
TP_MCP_RGB_DAC_RSET<br />
TP_MCP_RGB_DAC_VREF<br />
MCP_TV_DAC_RSET<br />
MCP_TV_DAC_VREF<br />
MCP_CLK27M_XTALIN<br />
MCP_CLK27M_XTALOUT<br />
C23 RGMII_RXD0<br />
B23 RGMII_RXD1<br />
E24 RGMII_RXD2<br />
A24 RGMII_RXD3<br />
A23<br />
C22<br />
RGMII_RXC/MII_RXCLK<br />
RGMII_RXCTL/MII_RXDV<br />
F23 MII_RXER/GPIO_36<br />
B26 MII_COL/GPIO_20/MSMB_DATA<br />
B22 MII_CRS/GPIO_21/MSMB_CLK<br />
J22<br />
T23<br />
RGMII_INTR/GPIO_35<br />
+V_DUAL_MACPLL<br />
C27 MII_COMP_VDD<br />
B27 MII_COMP_GND<br />
C39 RGB_DAC_RSET<br />
B38 RGB_DAC_VREF<br />
E36 TV_DAC_RSET<br />
A35 TV_DAC_VREF<br />
C38 XTALIN_TV<br />
D38 XTALOUT_TV<br />
U1400<br />
MCP79-TOPO-B<br />
BGA<br />
(6 OF 11)<br />
LAN<br />
DACS<br />
+3.3V_DUAL_RMGT1<br />
+3.3V_DUAL_RMGT2<br />
MII_VREF<br />
RGMII_TXD0 B24<br />
RGMII_TXD1 C24<br />
RGMII_TXD2 C25<br />
RGMII_TXD3 D25<br />
RGMII_TXC/MII_TXCLK<br />
RGMII_TXCTL/MII_TXEN<br />
RGMII_PWRDWN/GPIO_37<br />
RGB ONLY<br />
BUF_25MHZ<br />
MII_RESET#<br />
J24<br />
<strong>K24</strong><br />
+V_DUAL_RMGT1 U23<br />
+V_DUAL_RMGT2 V23<br />
E28<br />
D24<br />
C26<br />
RGMII_MDC D21<br />
RGMII_MDIO C21<br />
G23<br />
E23<br />
J23<br />
+V_RGB_DAC J32<br />
+V_TV_DAC K32<br />
DDC_CLK0 B31<br />
DDC_DATA0 A31<br />
RGB_DAC_RED B39<br />
RGB_DAC_GREEN A39<br />
RGB_DAC_BLUE B40<br />
RGB_DAC_HSYNC A40<br />
RGB_DAC_VSYNC A41<br />
TV / Component<br />
C / Pr TV_DAC_RED A36<br />
Y / Y TV_DAC_GREEN B36<br />
Comp / Pb TV_DAC_BLUE C36<br />
TV_DAC_HSYNC/GPIO_44 D36<br />
TV_DAC_VSYNC/GPIO_45 C37<br />
=PP3V3_ENET_MCP_RMGT<br />
=PP1V05_ENET_MCP_RMGT<br />
MCP_MII_VREF<br />
ENET_TXD<br />
ENET_TXD<br />
ENET_TXD<br />
ENET_TXD<br />
ENET_CLK125M_TXCLK<br />
ENET_TX_CTRL<br />
ENET_MDC<br />
ENET_MDIO<br />
TP_ENET_PWRDWN_L<br />
MCP_CLK25M_BUF0_R<br />
ENET_RESET_L<br />
PP3V3_S0_MCP_DAC<br />
103 mA<br />
103 mA<br />
MCP_DDC_CLK0<br />
MCP_DDC_DATA0<br />
TP_MCP_RGB_RED<br />
TP_MCP_RGB_GREEN<br />
TP_MCP_RGB_BLUE<br />
TP_MCP_RGB_HSYNC<br />
TP_MCP_RGB_VSYNC<br />
CRT_IG_R_C_PR<br />
CRT_IG_G_Y_Y<br />
CRT_IG_B_COMP_PB<br />
CRT_IG_HSYNC<br />
CRT_IG_VSYNC<br />
7B5 17D7 22A5 22B6<br />
83 mA (A01)<br />
7A5 22D6<br />
131 mA (A01)<br />
IN 22A4<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
OUT<br />
OUT<br />
23D2<br />
206 mA (A01)<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
31C6 77D3<br />
31C6 77D3<br />
31C6 77D3<br />
31C6 77D3<br />
31C8 77D3<br />
31B6 77C3<br />
31B6 77D3<br />
31B6 77D3<br />
32A5 77D3<br />
31B7 77C3<br />
8D4<br />
8D4<br />
8D4<br />
8D4<br />
8D4<br />
1<br />
R1860<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
2<br />
NOTE: All Apple products set strap to<br />
MII, RGMII products will enable<br />
feature via software. This<br />
avoids a leakage issue since<br />
MCP79 requires a S5 pull-up.<br />
=PP3V3_S0_MCP_GPIO<br />
R1861<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
RGB DAC Disable:<br />
Okay to float all RGB_DAC signals.<br />
DDC_CLK0/DDC_DATA0 pull-ups still required.<br />
TV DAC Disable:<br />
Network Interface Select<br />
Interface<br />
RGMII<br />
MII<br />
7C5 18D1 20A4<br />
ENET_TXD<br />
Okay to float all TV_DAC signals.<br />
Okay to float XTALIN_TV and XTALOUT_TV.<br />
DDC_CLK0/DDC_DATA0 pull-ups still required.<br />
1<br />
0<br />
D<br />
C<br />
42C3<br />
BI<br />
69A5<br />
IN<br />
LPCPLUS_GPIO<br />
DP_IG_CA_DET<br />
E16<br />
B15<br />
GPIO_6/FERR*/IGPU_GPIO_6<br />
GPIO_7/NFERR*/IGPU_GPIO_7<br />
IFPA_TXC_P<br />
IFPA_TXC_N<br />
B35<br />
C35<br />
LVDS_IG_A_CLK_P<br />
LVDS_IG_A_CLK_N<br />
OUT<br />
OUT<br />
68B3 75B3<br />
68B3 75B3<br />
B<br />
MCP Signal<br />
=MCP_HDMI_TXC_P/N<br />
=MCP_HDMI_TXD_P/N<br />
=MCP_HDMI_TXD_P/N<br />
=MCP_HDMI_TXD_P/N<br />
=MCP_HDMI_DDC_CLK<br />
=MCP_HDMI_DDC_DATA<br />
=MCP_HDMI_HPD<br />
DP_IG_AUX_CH_P/N<br />
TMDS/HDMI<br />
TMDS_IG_TXC_P/N<br />
TMDS_IG_TXD_P/N<br />
TMDS_IG_TXD_P/N<br />
TMDS_IG_TXD_P/N<br />
TMDS_IG_DDC_CLK<br />
TMDS_IG_DDC_DATA<br />
TMDS_IG_HPD<br />
TP_DP_IG_AUX_CHP/N<br />
Interface Mode<br />
DisplayPort<br />
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.<br />
NOTE: 20K pull-down required on DP_HPD_DET.<br />
NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.<br />
DP_IG_ML_P/N<br />
DP_IG_ML_P/N<br />
DP_IG_ML_P/N<br />
DP_IG_ML_P/N<br />
DP_IG_DDC_CLK<br />
DP_IG_DDC_DATA<br />
DP_IG_HPD<br />
DP_IG_AUX_CH_P/N<br />
NOTE: HDMI port requires level-shifting. IFP interface can<br />
be used to provide HDMI or dual-channel TMDS without<br />
level-shifters.<br />
LVDS: Power +VDD_IFPx at 1.8V<br />
Dual-channel TMDS: Power +VDD_IFPx at 3.3V<br />
72B7 71A7<br />
72C8 72B7<br />
68C8<br />
69D3<br />
69D3<br />
69D3<br />
69D3<br />
69D3<br />
69D3<br />
69D3<br />
69D3<br />
75B3 69C7<br />
75B3 69C7<br />
8B4<br />
69D3<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT =MCP_HDMI_TXD_P<br />
OUT =MCP_HDMI_TXD_N<br />
OUT =MCP_HDMI_TXD_P<br />
OUT =MCP_HDMI_TXD_N<br />
OUT =MCP_HDMI_TXD_P<br />
OUT =MCP_HDMI_TXD_N<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
23D7 7B6<br />
23C5<br />
23D7 7D7<br />
LVDS_IG_BKL_PWM<br />
LVDS_IG_BKL_ON<br />
LVDS_IG_PANEL_PWR<br />
=MCP_HDMI_TXC_P<br />
=MCP_HDMI_TXC_N<br />
DP_IG_AUX_CH_P<br />
DP_IG_AUX_CH_N<br />
=DVI_HPD_GMUX_INT<br />
=MCP_HDMI_HPD<br />
=PP3V3R1V8_S0_MCP_IFP_VDD<br />
190 mA (A01, 1.8V)<br />
PP3V3_S0_MCP_VPLL<br />
16 mA (A01)<br />
=PP1V05_S0_MCP_HDMI_VDD<br />
95 mA (A01)<br />
75B3 23C7 OUT MCP_HDMI_RSET<br />
75B3 23C7 OUT MCP_HDMI_VPROBE<br />
(See below)<br />
(See below)<br />
8 mA<br />
8 mA<br />
G39 LCD_BKL_CTL/GPIO_57<br />
E37 LCD_BKL_ON/GPIO_59<br />
F40 LCD_PANEL_PWR/GPIO_58<br />
D35 HDMI_TXC_P/ML0_LANE3_P<br />
E35 HDMI_TXC_N/ML0_LANE3_N<br />
G35 HDMI_TXD0_P/ML0_LANE2_P<br />
F35 HDMI_TXD0_N/ML0_LANE2_N<br />
F33 HDMI_TXD1_P/ML0_LANE1_P<br />
G33 HDMI_TXD1_N/ML0_LANE1_N<br />
J33 HDMI_TXD2_P/ML0_LANE0_P<br />
H33 HDMI_TXD2_N/ML0_LANE0_N<br />
D43 DP_AUX_CH0_P<br />
C43 DP_AUX_CH0_N<br />
C31 HPLUG_DET2/GPIO_22<br />
F31 HPLUG_DET3<br />
M27 +VDD_IFPA<br />
M26 +VDD_IFPB<br />
M28 +V_PLL_IFPAB<br />
M29 +V_PLL_HDMI<br />
T25<br />
+VDD_HDMI<br />
J31 HDMI_RSET<br />
J30 HDMI_VPROBE<br />
FLAT PANEL<br />
IFPA_TXD0_P B32<br />
IFPA_TXD0_N A32<br />
IFPA_TXD1_P D32<br />
IFPA_TXD1_N C32<br />
IFPA_TXD2_P D33<br />
IFPA_TXD2_N C33<br />
IFPA_TXD3_P B34<br />
IFPA_TXD3_N C34<br />
IFPB_TXC_P L31<br />
IFPB_TXC_N K31<br />
IFPB_TXD4_P J29<br />
IFPB_TXD4_N H29<br />
IFPB_TXD5_P L29<br />
IFPB_TXD5_N K29<br />
IFPB_TXD6_P L30<br />
IFPB_TXD6_N K30<br />
IFPB_TXD7_P N30<br />
IFPB_TXD7_N M30<br />
DDC_CLK2/GPIO_23 C30<br />
DDC_DATA2/GPIO_24 B30<br />
DDC_CLK3 D31<br />
DDC_DATA3 E31<br />
IFPAB_RSET E32<br />
IFPAB_VPROBE G31<br />
LVDS_IG_A_DATA_P<br />
LVDS_IG_A_DATA_N<br />
LVDS_IG_A_DATA_P<br />
LVDS_IG_A_DATA_N<br />
LVDS_IG_A_DATA_P<br />
LVDS_IG_A_DATA_N<br />
LVDS_IG_A_DATA_P<br />
LVDS_IG_A_DATA_N<br />
LVDS_IG_B_CLK_P<br />
LVDS_IG_B_CLK_N<br />
LVDS_IG_B_DATA_P<br />
LVDS_IG_B_DATA_N<br />
LVDS_IG_B_DATA_P<br />
LVDS_IG_B_DATA_N<br />
LVDS_IG_B_DATA_P<br />
LVDS_IG_B_DATA_N<br />
LVDS_IG_B_DATA_P<br />
LVDS_IG_B_DATA_N<br />
LVDS_IG_DDC_CLK<br />
LVDS_IG_DDC_DATA<br />
=MCP_HDMI_DDC_CLK<br />
=MCP_HDMI_DDC_DATA<br />
MCP_IFPAB_RSET<br />
MCP_IFPAB_VPROBE<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
OUT<br />
BI<br />
OUT<br />
OUT<br />
6C7 68C2 75B3<br />
6C7 68C2 75B3<br />
6C7 68C2 75B3<br />
6C7 68C2 75B3<br />
6C7 68C2 75B3<br />
6C7 68C2 75B3<br />
8D4<br />
8D4<br />
8D4<br />
8D4<br />
8C4<br />
8C4<br />
8C4<br />
8C4<br />
8C4<br />
8C4<br />
8C4<br />
8C4<br />
6C7 68C5<br />
6C7 68C5<br />
69D3<br />
69D3<br />
23C6 75B3<br />
23C6 75B3<br />
WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases<br />
B<br />
A<br />
GPIOs 57-59 (if LCD panel is used):<br />
In MCP79 these pins have undocumented internal<br />
pull-ups (~10K to 3.3V S0). To ensure pins are low<br />
by default, pull-downs (1K or stronger) must be used.<br />
1<br />
R1850<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
MCP Ethernet & Graphics<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
SYNC_DATE=04/04/2008<br />
NOTICE OF PROPRIETARY PROPERTY<br />
A<br />
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).<br />
=DVI_HPD_GMUX_INT:<br />
Alias to DVI_HPD for systems using IFP for DVI.<br />
Alias to GMUX_INT for systems with GMUX.<br />
Alias to HPLUG_DET2 for other systems.<br />
Pull-down (20k) required in all cases.<br />
8 7 6 5 4 3 2 1<br />
APPLE INC.<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
17<br />
81
8 7 6 5 4 3 2 1<br />
OMIT<br />
D<br />
C<br />
76D3 18D2 PCI_REQ0_L<br />
76D3 18D2 PCI_REQ1_L<br />
35D6 35C7 35C4 35A4 18D2 OUT FW_PWR_EN<br />
57D3 OUT AUD_IPHS_SWITCH_EN<br />
18D2 IN MCP_RS232_SIN_L<br />
76D3 12C3<br />
76D3 12C3<br />
76D3 12C3<br />
76D3 12C3<br />
76D3 12C3<br />
76D3 12C3<br />
76D3 12C3<br />
76D3 12C3<br />
42D5 40C5<br />
42D3<br />
8C2<br />
40C8<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
IN<br />
BI<br />
MCP_DEBUG<br />
MCP_DEBUG<br />
MCP_DEBUG<br />
MCP_DEBUG<br />
MCP_DEBUG<br />
MCP_DEBUG<br />
MCP_DEBUG<br />
MCP_DEBUG<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_AD<br />
TP_PCI_INTW_L<br />
TP_PCI_INTX_L<br />
TP_PCI_INTY_L<br />
TP_PCI_INTZ_L<br />
TP_PCI_TRDY_L<br />
PM_CLKRUN_L<br />
FW_PME_L<br />
TP_LPC_DRQ0_L<br />
LPC_SERIRQ<br />
T2 PCI_REQ0#<br />
V9 PCI_REQ1#/FANRPM2<br />
T3 PCI_REQ2#/GPIO_40/RS232_DSR#<br />
U9 PCI_REQ3#/GPIO_38/RS232_CTS#<br />
T4 PCI_REQ4#/GPIO_52/RS232_SIN#<br />
AC3 PCI_AD0<br />
AE10 PCI_AD1<br />
AC4 PCI_AD2<br />
AE11 PCI_AD3<br />
AB3 PCI_AD4<br />
AC6 PCI_AD5<br />
AB2 PCI_AD6<br />
AC7 PCI_AD7<br />
AC8 PCI_AD8<br />
AA2 PCI_AD9<br />
AC9 PCI_AD10<br />
AC10 PCI_AD11<br />
AC11 PCI_AD12<br />
AA1 PCI_AD13<br />
AA5 PCI_AD14<br />
Y5 PCI_AD15<br />
W3 PCI_AD16<br />
W6 PCI_AD17<br />
W4 PCI_AD18<br />
W7 PCI_AD19<br />
V3 PCI_AD20<br />
W8 PCI_AD21<br />
V2 PCI_AD22<br />
W9 PCI_AD23<br />
U3 PCI_AD24<br />
W11 PCI_AD25<br />
U2 PCI_AD26<br />
U5 PCI_AD27<br />
U1 PCI_AD28<br />
U6 PCI_AD29<br />
T5 PCI_AD30<br />
U7 PCI_AD31<br />
P2 PCI_INTW#<br />
N3 PCI_INTX#<br />
N2 PCI_INTY#<br />
N1 PCI_INTZ#<br />
Y3<br />
AD11<br />
PCI_TRDY#<br />
PCI_CLKRUN#/GPIO_42<br />
AE2 LPC_DRQ1#/GPIO_19 Int PU<br />
AE1 LPC_DRQ0# Int PU<br />
AE6 LPC_SERIRQ Int PU<br />
U1400<br />
MCP79-TOPO-B<br />
BGA<br />
(7 OF 11)<br />
LPC PCI<br />
PCI_GNT0# R3<br />
PCI_GNT1#/FANCTL2 U10<br />
PCI_GNT2#/GPIO_41/RS232_DTR# R4<br />
PCI_GNT3#/GPIO_39/RS232_RTS# U11<br />
PCI_GNT4#/GPIO_53/RS232_SOUT# P3<br />
PCI_CBE0# AA3<br />
PCI_CBE1# AA6<br />
PCI_CBE2# AA11<br />
PCI_CBE3# W10<br />
PCI_DEVSEL# AA9<br />
PCI_FRAME# Y4<br />
PCI_IRDY# AA10<br />
PCI_PAR Y1<br />
PCI_PERR#/GPIO_43/RS232_DCD# AB9<br />
PCI_SERR# AA7<br />
PCI_STOP# Y2<br />
PCI_PME#/GPIO_30 T1<br />
Int PU (S5)<br />
PCI_RESET0# R10<br />
PCI_RESET1# R11<br />
PCI_CLK0 R6<br />
PCI_CLK1 R7<br />
PCI_CLK2 R8<br />
PCI_CLKIN<br />
LPC_FRAME# AD4<br />
LPC_PWRDWN#/GPIO_54/EXT_NMI# AE12<br />
LPC_RESET0#<br />
LPC_AD0 AD3<br />
LPC_AD1 AD2<br />
LPC_AD2 AD1<br />
LPC_AD3 AD5<br />
LPC_CLK0<br />
R9<br />
AE5<br />
AE9<br />
TP_PCI_GNT0_L<br />
TP_PCI_GNT1_L<br />
GMUX_JTAG_TMS<br />
GMUX_JTAG_TDI<br />
MCP_RS232_SOUT_L<br />
TP_PCI_C_BE_L<br />
TP_PCI_C_BE_L<br />
TP_PCI_C_BE_L<br />
TP_PCI_C_BE_L<br />
TP_PCI_DEVSEL_L<br />
TP_PCI_FRAME_L<br />
TP_PCI_IRDY_L<br />
TP_PCI_PAR<br />
TP_PCI_PERR_L<br />
TP_PCI_SERR_L<br />
TP_PCI_STOP_L<br />
PM_LATRIGGER_L<br />
MEM_VTT_EN_R<br />
TP_PCI_RESET1_L<br />
TP_PCI_CLK0<br />
TP_PCI_CLK1<br />
76C3 PCI_CLK33M_MCP_R<br />
76C3 PCI_CLK33M_MCP<br />
LPC_FRAME_R_L<br />
LPC_PWRDWN_L<br />
LPC_RESET_L<br />
LPC_AD_R<br />
LPC_AD_R<br />
LPC_AD_R<br />
LPC_AD_R<br />
LPC_CLK33M_SMC_R<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
1<br />
R1910<br />
2<br />
22<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
18D2<br />
PLACEMENT_NOTE=Place close to pin R8<br />
R1960<br />
8C4<br />
8C4<br />
12C6<br />
24C4<br />
22<br />
R1950 22<br />
R1951 22<br />
R1952 22<br />
R1953 22<br />
1<br />
1<br />
1<br />
1<br />
1<br />
2<br />
2<br />
2<br />
2<br />
2<br />
5%<br />
5%<br />
5%<br />
5%<br />
1/16W<br />
1/16W<br />
1/16W<br />
1/16W<br />
MF-LF<br />
MF-LF<br />
MF-LF<br />
MF-LF<br />
402<br />
402<br />
402<br />
402<br />
5% 1/16W MF-LF 402<br />
LPC_FRAME_L<br />
LPC_AD<br />
LPC_AD<br />
LPC_AD<br />
LPC_AD<br />
OUT 40C8 42D5 76C3<br />
OUT 40C5 42D3<br />
OUT 24D4 76C3<br />
BI 40C8 42D5 76C3<br />
BI 40C8 42D5 76C3<br />
BI 40C8 42D3 76C3<br />
BI 40C8 42D3 76C3<br />
OUT 24B4 76C3<br />
18D4<br />
MCP_RS232_SOUT_L<br />
76D3 18D7 PCI_REQ0_L<br />
76D3 18D7 PCI_REQ1_L<br />
35D6 35C7 35C4 35A4 18D7 FW_PWR_EN<br />
18D7 MCP_RS232_SIN_L<br />
R1989 8.2K<br />
R1990 8.2K<br />
R1991 8.2K<br />
R1992 8.2K<br />
R1994 8.2K<br />
20A4 17C1 7C5 =PP3V3_S0_MCP_GPIO<br />
1<br />
2<br />
5% 1/16W MF-LF 402<br />
1<br />
2<br />
5% 1/16W MF-LF 402<br />
1<br />
2<br />
5% 1/16W MF-LF 402<br />
1<br />
2<br />
5% 1/16W MF-LF 402<br />
1<br />
2<br />
5% 1/16W MF-LF 402<br />
D<br />
C<br />
B<br />
A<br />
U24 GND65<br />
U26 GND66<br />
U39 GND67<br />
U4 GND68<br />
U8 GND69<br />
V16 GND70<br />
V17 GND71<br />
V18 GND72<br />
V20 GND73<br />
V22 GND74<br />
V24 GND75<br />
V26 GND76<br />
V27 GND77<br />
V28 GND78<br />
V33 GND79<br />
V37 GND80<br />
V4 GND81<br />
V40 GND82<br />
V7 GND83<br />
W20 GND84<br />
W22 GND85<br />
W24 GND86<br />
W36 GND87<br />
W40 GND88<br />
W43 GND89<br />
Y16 GND90<br />
Y17 GND91<br />
Y18 GND92<br />
Y19 GND93<br />
Y20 GND94<br />
Y22 GND95<br />
Y24 GND96<br />
Y25 GND97<br />
GND<br />
GND98 Y26<br />
GND99 Y27<br />
GND100 AB18<br />
GND101 H34<br />
GND102 AB20<br />
GND103 AB21<br />
GND104 AB23<br />
GND105 AB24<br />
GND106 AB25<br />
GND107 AB26<br />
GND108 AB27<br />
GND109 AB28<br />
GND110 AB34<br />
GND111 AB37<br />
GND112 AB4<br />
GND113 AB40<br />
GND114 AC22<br />
GND115 AC36<br />
GND116 AC40<br />
GND117 AB33<br />
GND118 AC5<br />
GND119 AD16<br />
GND120 AD17<br />
GND121 AD18<br />
GND122 AD19<br />
GND123 AD20<br />
GND124 AD24<br />
GND125 AD25<br />
GND126 AD26<br />
GND127 AD27<br />
GND128 AD28<br />
GND129 AD33<br />
GND130 AD34<br />
1<br />
R1961<br />
10K<br />
5%<br />
2<br />
1/16W<br />
MF-LF<br />
402<br />
Strap for Boot ROM Selection (See HDA_SDOUT)<br />
MCP PCI & LPC<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
SYNC_DATE=04/04/2008<br />
NOTICE OF PROPRIETARY PROPERTY<br />
B<br />
A<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
18 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
OMIT<br />
D<br />
C<br />
75A3 37A2 OUT<br />
75A3 37A2 OUT<br />
75A3 37B2 IN<br />
75A3 37B2 IN<br />
75A3 37C3 OUT<br />
75A3 37C3 OUT<br />
75A3 37C3 IN<br />
75A3 37C3 IN<br />
SATA_HDD_R2D_C_P<br />
SATA_HDD_R2D_C_N<br />
SATA_HDD_D2R_N<br />
SATA_HDD_D2R_P<br />
SATA_ODD_R2D_C_P<br />
SATA_ODD_R2D_C_N<br />
SATA_ODD_D2R_N<br />
SATA_ODD_D2R_P<br />
TP_SATA_C_R2D_CP<br />
TP_SATA_C_R2D_CN<br />
TP_SATA_C_D2RN<br />
TP_SATA_C_D2RP<br />
TP_SATA_D_R2D_CP<br />
TP_SATA_D_R2D_CN<br />
TP_SATA_D_D2RN<br />
TP_SATA_D_D2RP<br />
TP_SATA_E_R2D_CP<br />
TP_SATA_E_R2D_CN<br />
TP_SATA_E_D2RN<br />
TP_SATA_E_D2RP<br />
TP_SATA_F_R2D_CP<br />
TP_SATA_F_R2D_CN<br />
AJ7 SATA_A0_TX_P<br />
AJ6 SATA_A0_TX_N<br />
AJ5 SATA_A0_RX_N<br />
AJ4 SATA_A0_RX_P<br />
AJ11 SATA_A1_TX_P<br />
AJ10 SATA_A1_TX_N<br />
AJ9 SATA_A1_RX_N<br />
AK9 SATA_A1_RX_P<br />
AK2 SATA_B0_TX_P<br />
AJ3 SATA_B0_TX_N<br />
AJ2 SATA_B0_RX_N<br />
AJ1 SATA_B0_RX_P<br />
AM4 SATA_B1_TX_P<br />
AL3 SATA_B1_TX_N<br />
AL4 SATA_B1_RX_N<br />
AK3 SATA_B1_RX_P<br />
AN1 SATA_C0_TX_P<br />
AM1 SATA_C0_TX_N<br />
AM2 SATA_C0_RX_N<br />
AM3 SATA_C0_RX_P<br />
AP3 SATA_C1_TX_P<br />
AP2 SATA_C1_TX_N<br />
U1400<br />
MCP79-TOPO-B<br />
BGA<br />
(8 OF 11)<br />
SATA<br />
USB<br />
USB0_P C29<br />
USB0_N D29<br />
USB1_P C28<br />
USB1_N D28<br />
USB2_P A28<br />
USB2_N B28<br />
USB3_P F29<br />
USB3_N G29<br />
USB4_P K27<br />
USB4_N L27<br />
USB5_P J26<br />
USB5_N J27<br />
USB6_P F27<br />
USB6_N G27<br />
USB7_P D27<br />
USB7_N E27<br />
USB8_P K25<br />
USB8_N L25<br />
USB9_P H25<br />
USB9_N J25<br />
USB10_P F25<br />
USB10_N G25<br />
USB11_P K23<br />
USB11_N L23<br />
USB_OC0#/GPIO_25 L21<br />
USB_OC1#/GPIO_26 K21<br />
USB_OC2#/GPIO_27/MGPIO J21<br />
USB_OC3#/GPIO_28/MGPIO H21<br />
External A<br />
USB_EXTA_P<br />
USB_EXTA_N<br />
AirPort (PCIe Mini-Card)<br />
USB_MINI_P<br />
USB_MINI_N<br />
External D<br />
USB_EXTD_P<br />
USB_EXTD_N<br />
Camera<br />
IR<br />
USB_CAMERA_P<br />
USB_CAMERA_N<br />
USB_IR_P<br />
USB_IR_N<br />
Geyser Trackpad/Keyboard<br />
USB_TPAD_P<br />
USB_TPAD_N<br />
Bluetooth<br />
USB_BT_P<br />
USB_BT_N<br />
External B<br />
USB_EXTB_P<br />
USB_EXTB_N<br />
ExpressCard<br />
USB_EXCARD_P<br />
USB_EXCARD_N<br />
External C<br />
USB_EXTC_P<br />
USB_EXTC_N<br />
TP_USB_10P<br />
TP_USB_10N<br />
USB_CARDREADER_P<br />
USB_CARDREADER_N<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
38A8 76C3<br />
38A8 76C3<br />
8C6<br />
8C6<br />
8C6<br />
8C6<br />
29B5 76C3<br />
29B5 76C3<br />
39D7 76B3<br />
39D7 76B3<br />
48B8 76B3<br />
48B8 76B3<br />
29B5 76C3<br />
29B5 76C3<br />
38A4 76B3<br />
38B4 76B3<br />
8C6<br />
8C6<br />
8C6<br />
8C6<br />
30C7 76B3<br />
30C7 76B3<br />
1<br />
R2050<br />
8.2K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R2051<br />
8.2K<br />
5%<br />
1<br />
2<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
R2052<br />
8.2K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R2053<br />
8.2K<br />
5%<br />
1<br />
2<br />
=PP3V3_S5_MCP_GPIO<br />
1/16W<br />
MF-LF<br />
402<br />
USB_EXTA_OC_L<br />
USB_EXTB_OC_L<br />
USB_EXTC_OC_L<br />
EXCARD_OC_L<br />
IN<br />
IN<br />
IN<br />
IN<br />
7A3 17C7<br />
38C7<br />
38C7<br />
41C4<br />
D<br />
C<br />
TP_SATA_F_D2RN<br />
TP_SATA_F_D2RP<br />
AN3 SATA_C1_RX_N<br />
AN2 SATA_C1_RX_P<br />
+V_PLL_USB<br />
USB_RBIAS_GND<br />
L28<br />
A27<br />
PP3V3_S0_MCP_PLL_USB<br />
76B3 MCP_USB_RBIAS_GND<br />
19 mA (A01)<br />
22B4<br />
B<br />
TP_MCP_SATALED_L<br />
22B2 PP1V05_S0_MCP_PLL_SATA<br />
84 mA (A01)<br />
7A6 =PP1V05_S0_MCP_SATA_DVDD0<br />
43 mA (A01, DVDD0 & 1)<br />
7A6 =PP1V05_S0_MCP_SATA_DVDD1<br />
7A6 =PP1V05_S0_MCP_SATA_AVDD0<br />
127 mA (A01, AVDD0 & 1)<br />
7A6 =PP1V05_S0_MCP_SATA_AVDD1<br />
75A3 MCP_SATA_TERMP<br />
E12<br />
AE16<br />
SATA_LED#<br />
+V_PLL_SATA<br />
AF19 +DVDD0_SATA1<br />
AG16 +DVDD0_SATA2<br />
AG17 +DVDD0_SATA3<br />
AG19 +DVDD0_SATA4<br />
AH17 +DVDD1_SATA1<br />
AH19 +DVDD1_SATA2<br />
AJ12 +AVDD0_SATA1<br />
AN11 +AVDD0_SATA2<br />
AK12 +AVDD0_SATA3<br />
AK13 +AVDD0_SATA4<br />
AL12 +AVDD0_SATA5<br />
AM11 +AVDD0_SATA6<br />
AM12 +AVDD0_SATA7<br />
AN12 +AVDD0_SATA8<br />
AL13 +AVDD0_SATA9<br />
AN14 +AVDD1_SATA1<br />
AL14 +AVDD1_SATA2<br />
AM13 +AVDD1_SATA3<br />
AM14 +AVDD1_SATA4<br />
AE3<br />
SATA_TERMP<br />
GND131 AD35<br />
GND132 AD37<br />
GND133 AD38<br />
GND134 AE22<br />
GND135 AE24<br />
GND136 AE39<br />
GND137 AE4<br />
GND138 AD6<br />
GND139 AF16<br />
GND140 AF17<br />
GND141 AF18<br />
GND142 AF20<br />
GND143 AF22<br />
GND144 AF26<br />
GND145 AF27<br />
GND146 AF28<br />
GND147 AF33<br />
GND148 AF34<br />
GND149 AF37<br />
GND150 AF40<br />
GND151 AG18<br />
GND152 AG20<br />
GND153 AG22<br />
GND154 AG26<br />
GND155 AG36<br />
GND156 AG40<br />
GND157 AH18<br />
GND158 AH20<br />
GND159 AH22<br />
GND160 AH24<br />
R2060<br />
1<br />
806<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
B<br />
A<br />
1<br />
R2010<br />
2.49K<br />
2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.<br />
If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
MCP SATA & USB<br />
NOTICE OF PROPRIETARY PROPERTY<br />
SYNC_DATE=04/04/2008<br />
A<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).<br />
8 7 6 5 4 3 2 1<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
19 81<br />
REV.<br />
4.7.0
8 7 6 5 4 3 2 1<br />
OMIT<br />
U1400<br />
MCP79-TOPO-B<br />
BGA<br />
(9 OF 11)<br />
=PP3V3R1V5_S0_MCP_HDA<br />
7C5 20D8 22A8<br />
7 mA (A01)<br />
D<br />
C<br />
22A8 20D3 7C5 =PP3V3R1V5_S0_MCP_HDA<br />
24D4 21A5 6C3 PP3V3_G3_RTC<br />
R2120<br />
1<br />
49.9K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
R2110<br />
49.9<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
R2121<br />
49.9K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
76A3 52C7<br />
42B8<br />
41B2 40D5 35B5 32B7<br />
40C5<br />
40B8<br />
40B8<br />
73B3 62D8<br />
40C8<br />
24A1<br />
40D8<br />
24A5<br />
IN<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
HDA_SDIN0<br />
(MXM_OK for MXM systems)<br />
76A3 MCP_HDA_PULLDN_COMP<br />
22A2<br />
TP_<strong>MLB</strong>_RAM_SIZE<br />
TP_<strong>MLB</strong>_RAM_VENDOR<br />
PP1V05_S0_MCP_PLL_NV<br />
37 mA (A01) 20 mA<br />
17 mA<br />
=SPI_CS1_R_L_USE_<strong>MLB</strong><br />
SMC_ADAPTER_EN<br />
TP_SB_A20GATE<br />
TP_MCP_KBDRSTIN_L<br />
SMC_WAKE_SCI_L<br />
SMC_RUNTIME_SCI_L<br />
SM_INTRUDER_L<br />
TP_MCP_LID_L<br />
PM_BATLOW_L<br />
PM_DPRSLPVR<br />
PM_PWRBTN_L<br />
PM_SYSRST_DEBOUNCE_L<br />
RTC_RST_L<br />
PM_RSMRST_L<br />
MCP_PS_PWRGD<br />
G15 HDA_SDATA_IN0<br />
Int PD<br />
J14 HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK<br />
Int PD<br />
J15 HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA<br />
Int PD<br />
A15<br />
HDA_PULLDN_COMP<br />
AE18 +V_PLL_NV_H<br />
AE17 +V_PLL_SP_SPREF<br />
L24<br />
L26<br />
GPIO_1/PWRDN_OK/SPI_CS1<br />
GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L<br />
K13 A20GATE Int PU<br />
L13 KBRDRSTIN* Int PU<br />
C19 SIO_PME* Int PU (S5)<br />
C18 EXT_SMI/GPIO_32* Int PU (S5)<br />
B20<br />
INTRUDER*<br />
M25 LID* Int PU (S5)<br />
M24 LLB* Int PU (S5)<br />
M22<br />
CPU_DPRSLPVR<br />
C16 PWRBTN*<br />
D16 RSTBTN*<br />
C20<br />
RTC_RST*<br />
D20 PWRGD_SB<br />
E20 PS_PWRGD<br />
Int PU (S5)<br />
Int PU<br />
MISC HDA<br />
(MGPIO2)<br />
(MGPIO3)<br />
+V_DUAL_HDA1 J16<br />
+V_DUAL_HDA2 K16<br />
HDA_SDATA_OUT<br />
HDA_BITCLK<br />
HDA_RESET*<br />
HDA_SYNC<br />
THERM_DIODE_P B11<br />
THERM_DIODE_N C11<br />
MCP_VID0/GPIO_13 L20<br />
MCP_VID1/GPIO_14 M20<br />
MCP_VID2/GPIO_15 M21<br />
SPKR<br />
F15<br />
E15<br />
K15<br />
L15<br />
HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK K17<br />
HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA L17<br />
SLP_S3* G17<br />
SLP_RMGT* J17<br />
SLP_S5* H17<br />
C13<br />
SMB_CLK0 L19<br />
SMB_DATA0 K19<br />
SMB_CLK1/MSMB_CLK G21<br />
SMB_DATA1/MSMB_DATA F21<br />
SMB_ALERT*/GPIO_64 M23<br />
FANRPM0/GPIO_60 B12<br />
FANCTL0/GPIO_61 A12<br />
FANRPM1/GPIO_63 D12<br />
FANCTL1/GPIO_62 C12<br />
1<br />
R2160<br />
8.2K<br />
5%<br />
2<br />
1/16W<br />
MF-LF<br />
402<br />
76A3 20A7 HDA_SDOUT_R<br />
76B3 20A7 HDA_BIT_CLK_R<br />
76A3 20A7 HDA_RST_R_L<br />
76B3 20A7 HDA_SYNC_R<br />
MCP_GPIO_4<br />
AUD_I2C_INT_L<br />
PM_SLP_S3_L<br />
PM_SLP_RMGT_L<br />
PM_SLP_S4_L<br />
MCP_THMDIODE_P<br />
MCP_THMDIODE_N<br />
MCP_VID<br />
MCP_VID<br />
MCP_VID<br />
MCP_SPKR<br />
SMBUS_MCP_0_CLK<br />
SMBUS_MCP_0_DATA<br />
SMBUS_MCP_1_CLK<br />
SMBUS_MCP_1_DATA<br />
AP_PWR_EN<br />
MEM_EVENT_L<br />
ODD_PWR_EN_L<br />
SMC_IG_THROTTLE_L<br />
ARB_DETECT<br />
R2171<br />
22<br />
1<br />
1<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R2173<br />
22<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
20A4<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
OUT<br />
BI<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
20A4<br />
R2170<br />
22<br />
1<br />
1<br />
6C3 32B7 35A5 40C5 66D5 70D8<br />
8D1<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
6C3 40C5 41A2 66C8<br />
46B5 80D3<br />
46B5 80D3<br />
20A3 63D8<br />
20A3 63C8<br />
20A3 63C8<br />
12B6 43D8 76B3<br />
12B6 43D8 76B3<br />
43B8 76B3<br />
2<br />
R2172<br />
22<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
20A4 57D3<br />
2<br />
43B8 76B3<br />
20A3 29D5 32C7<br />
20A4 26A5 27A5 40B8<br />
37D6<br />
20A4 41D4<br />
HDA_SDOUT<br />
HDA_BIT_CLK<br />
HDA_RST_L<br />
HDA_SYNC<br />
2<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
=PP3V3_S0_MCP<br />
52C7 76A3<br />
52C7 76B3<br />
52C7 76A3<br />
52C7 76B3<br />
BOOT_MODE_SAFE<br />
1<br />
R2180<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
7C5 21B3 22B8<br />
OUT 41C5<br />
BOOT_MODE_USER<br />
1<br />
R2181<br />
10K<br />
5% USER mode: Normal<br />
1/16W<br />
MF-LF SAFE mode: For ROMSIP<br />
402<br />
2<br />
recovery<br />
Connects to SMC for<br />
automatic recovery.<br />
I/F<br />
LPC<br />
PCI<br />
SPI0<br />
SPI1<br />
BIOS Boot Select<br />
HDA_SDOUT<br />
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L<br />
R1961 and R2160 selects SPI0 ROM by<br />
default, LPC+ debug card pulls<br />
LPC_FRAME# high for SPI1 ROM override.<br />
NOTE: MCP79 does not support FWH, only<br />
LPC ROMs. So Apple designs will<br />
not use LPC for BootROM override.<br />
NOTE: MCP79 rev A01 does not support<br />
SPI1 option. Rev B01 will.<br />
0<br />
0<br />
1<br />
1<br />
Frequency<br />
LPC_FRAME#<br />
BUF_SIO_CLK Frequency<br />
14.31818 MHz<br />
SPI Frequency Select<br />
Frequency<br />
31 MHz<br />
42 MHz<br />
24 MHz<br />
SPI_DO<br />
0<br />
0<br />
0<br />
1<br />
0<br />
1<br />
HDA_SYNC<br />
1<br />
0<br />
SPI_CLK<br />
0<br />
1<br />
D<br />
C<br />
24A5<br />
IN<br />
MCP_CPU_VLD<br />
C17<br />
CPU_VLD<br />
CPUVDD_EN<br />
D17<br />
MCP_CPUVDD_EN<br />
OUT<br />
24A8<br />
25 MHz<br />
1<br />
0<br />
B<br />
12C3<br />
12C3<br />
12C3<br />
12C3<br />
12B6<br />
24B8<br />
24C8<br />
IN<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
OUT<br />
JTAG_MCP_TDI<br />
JTAG_MCP_TDO<br />
JTAG_MCP_TMS<br />
JTAG_MCP_TRST_L<br />
JTAG_MCP_TCK<br />
MCP_CLK25M_XTALIN<br />
MCP_CLK25M_XTALOUT<br />
E19<br />
F19<br />
J19<br />
J18<br />
G19<br />
A16<br />
B16<br />
JTAG_TDI Int PU<br />
JTAG_TDO<br />
JTAG_TMS Int PU<br />
JTAG_TRST*<br />
JTAG_TCK<br />
XTALIN<br />
XTALOUT<br />
SPI_CS0/GPIO_10 C14<br />
SPI_CLK/GPIO_11 D13<br />
SPI_DI/GPIO_8 C15<br />
SPI_DO/GPIO_9 B14<br />
SUS_CLK/GPIO_34 B18<br />
BUF_SIO_CLK AE7<br />
SPI_CS0_R_L<br />
SPI_CLK_R<br />
SPI_MISO<br />
SPI_MOSI_R<br />
PM_CLK32K_SUSCLK_R<br />
TP_MCP_BUF_SIO_CLK<br />
OUT<br />
OUT 42A5 42C8 76A3<br />
IN<br />
OUT<br />
OUT<br />
42B7 76A3<br />
42A5 42B7 76A3<br />
42A5 42C7 76A3<br />
24B4 76A3<br />
1 MHz<br />
NOTE: Straps not provided on this page.<br />
1<br />
1<br />
B<br />
24C8 IN<br />
24C8 OUT<br />
RTC_CLK32K_XTALIN<br />
RTC_CLK32K_XTALOUT<br />
R2150<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
2<br />
1<br />
R2151<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
A19<br />
B19<br />
XTALIN_RTC<br />
XTALOUT_RTC<br />
TEST_MODE_EN K22<br />
PKG_TEST L22<br />
R2163<br />
10K<br />
1<br />
2<br />
MCP_TEST_MODE_EN<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
R2190<br />
1K<br />
2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
A<br />
C2170<br />
10PF<br />
5%<br />
50V<br />
CERM<br />
402<br />
1<br />
2<br />
HDA Output Caps<br />
For EMI Reduction on HDA interface<br />
1<br />
C2171<br />
10PF<br />
2<br />
C2172<br />
10PF<br />
5%<br />
50V<br />
CERM<br />
402<br />
5%<br />
50V<br />
CERM<br />
402<br />
1<br />
2<br />
1<br />
C2173<br />
10PF<br />
2<br />
HDA_SDOUT_R<br />
HDA_BIT_CLK_R<br />
HDA_RST_R_L<br />
HDA_SYNC_R<br />
5%<br />
50V<br />
CERM<br />
402<br />
20D4 76A3<br />
20D4 76B3<br />
20D4 76A3<br />
20D4 76B3<br />
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).<br />
1<br />
R2140<br />
10K<br />
5%<br />
2<br />
1/16W<br />
MF-LF<br />
402<br />
R2141<br />
10K<br />
1<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
R2142<br />
10K<br />
5%<br />
2<br />
1/16W<br />
MF-LF<br />
402<br />
R2143<br />
10K<br />
1<br />
2<br />
1 R2147<br />
100K<br />
5%<br />
2<br />
=PP3V3_S0_MCP_GPIO<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
MCP_GPIO_4<br />
AUD_I2C_INT_L<br />
MEM_EVENT_L<br />
SMC_IG_THROTTLE_L<br />
ARB_DETECT<br />
1/16W<br />
MF-LF<br />
402<br />
8 7 6 5 4 3 2 1<br />
7C5 17C1 18D1<br />
20C3<br />
20C3 57D3<br />
20B3 26A5 27A5 40B8<br />
20B3 41D4<br />
20B3<br />
1 R2155<br />
22K<br />
5%<br />
2<br />
1/16W<br />
MF-LF<br />
402<br />
1 R2156<br />
22K<br />
5%<br />
2<br />
1/16W<br />
MF-LF<br />
402<br />
R2154<br />
100K<br />
2<br />
1<br />
1 R2157<br />
22K<br />
5%<br />
2<br />
=PP3V3_S3_MCP_GPIO<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
AP_PWR_EN<br />
MCP_VID<br />
MCP_VID<br />
MCP_VID<br />
1/16W<br />
MF-LF<br />
402<br />
20C3 29D5 32C7<br />
20C3 63D8<br />
20C3 63C8<br />
20C3 63C8<br />
7D3<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
APPLE INC.<br />
MCP HDA & MISC<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
SYNC_DATE=06/26/2008<br />
OF<br />
20 81<br />
REV.<br />
4.7.0<br />
A
8 7 6 5 4 3 2 1<br />
OMIT<br />
OMIT<br />
D<br />
C<br />
B<br />
A<br />
AH26 GND161<br />
AH33 GND162<br />
AH34 GND163<br />
AH37 GND164<br />
AH38 GND165<br />
AJ39 GND166<br />
AJ8 GND167<br />
AK10 GND168<br />
AK33 GND169<br />
AK34 GND170<br />
AK37 GND171<br />
AK4 GND172<br />
AK40 GND173<br />
AL36 GND174<br />
AL40 GND175<br />
AL5 GND176<br />
AM10 GND177<br />
AM16 GND178<br />
AM18 GND179<br />
AM20 GND180<br />
AM22 GND181<br />
AM24 GND182<br />
AM26 GND183<br />
AM30 GND184<br />
AM34 GND185<br />
AM35 GND186<br />
AM37 GND187<br />
AM38 GND188<br />
AM5 GND189<br />
AM6 GND190<br />
AM7 GND191<br />
AM9 GND192<br />
AP26 GND193<br />
AN28 GND194<br />
AN30 GND195<br />
AN39 GND196<br />
AN4 GND197<br />
Y7 GND198<br />
AP10 GND199<br />
AU26 GND200<br />
AP14 GND201<br />
AU14 GND202<br />
AP28 GND203<br />
AP32 GND204<br />
AP34 GND205<br />
AP36 GND206<br />
AP37 GND207<br />
AP4 GND208<br />
AP40 GND209<br />
AP7 GND210<br />
AW23 GND211<br />
AR28 GND212<br />
AR32 GND213<br />
AR40 GND214<br />
AT10 GND215<br />
AR12 GND216<br />
AT13 GND217<br />
AT29 GND218<br />
AT33 GND219<br />
AT6 GND220<br />
AT7 GND221<br />
AT9 GND222<br />
AY21 GND223<br />
AY22 GND224<br />
L12 GND225<br />
AU12 GND226<br />
AU28 GND227<br />
AP33 GND228<br />
AU32 GND229<br />
AR30 GND230<br />
AU36 GND231<br />
AU38 GND232<br />
AU4 GND233<br />
G28 GND234<br />
F20 GND235<br />
AV28 GND236<br />
AV32 GND237<br />
AV36 GND238<br />
AV4 GND239<br />
AV7 GND240<br />
AW11 GND241<br />
G20 GND242<br />
AR43 GND243<br />
AW43 GND244<br />
AY10 GND245<br />
AV12 GND246<br />
AY30 GND247<br />
AY33 GND248<br />
AY34 GND249<br />
AY37 GND250<br />
AY38 GND251<br />
AY41 GND252<br />
U1400<br />
MCP79-TOPO-B<br />
BGA<br />
(11 OF 11)<br />
GND<br />
GND253 AV40<br />
GND254 BA1<br />
GND255 BA4<br />
GND256 AW31<br />
GND257 AY6<br />
GND258 L35<br />
GND259 BC33<br />
GND260 BC37<br />
GND261 BC41<br />
GND262 AY14<br />
GND263 BC5<br />
GND264 C2<br />
GND265 D10<br />
GND266 D14<br />
GND267 D15<br />
GND268 D18<br />
GND269 D19<br />
GND270 D22<br />
GND271 D23<br />
GND272 D26<br />
GND273 D30<br />
GND274 D37<br />
GND275 D6<br />
GND276 E13<br />
GND277 E17<br />
GND278 E21<br />
GND279 E25<br />
GND280 E29<br />
GND281 E33<br />
GND282 F12<br />
GND283 F16<br />
GND284 F32<br />
GND285 F8<br />
GND286 G10<br />
GND287 G12<br />
GND288 G14<br />
GND289 G16<br />
GND290 BC12<br />
GND291 G22<br />
GND292 G24<br />
GND293 AW20<br />
GND294 G34<br />
GND295 G4<br />
GND296 G43<br />
GND297 G6<br />
GND298 G8<br />
GND299 H11<br />
GND300 H15<br />
GND301 AW35<br />
GND302 H23<br />
GND303 AN8<br />
GND304 G40<br />
GND305 J12<br />
GND306 J8<br />
GND307 K10<br />
GND308 K12<br />
GND309 K18<br />
GND310 K26<br />
GND311 K37<br />
GND312 K4<br />
GND313 K40<br />
GND314 K8<br />
GND315 AU1<br />
GND316 L40<br />
GND317 L43<br />
GND318 L5<br />
GND319 M10<br />
GND320 M34<br />
GND321 M35<br />
GND322 M37<br />
GND323 Y28<br />
GND324 Y33<br />
GND325 Y34<br />
GND326 Y35<br />
GND327 Y37<br />
GND328 Y38<br />
GND329 AB17<br />
GND330 AB16<br />
GND331 AN26<br />
GND332 AD7<br />
GND333 M11<br />
GND334 AA4<br />
GND335 AB19<br />
GND336 AY13<br />
GND337 P11<br />
GND338 Y6<br />
GND339 T11<br />
GND340 V11<br />
GND341 Y11<br />
GND342 AH16<br />
GND343 T22<br />
22D8<br />
7C6<br />
23065 mA (A01, 1.2V)<br />
16996 mA (A01, 1.0V)<br />
24D4 20C8 6C3<br />
=PPVCORE_S0_MCP<br />
PP3V3_G3_RTC<br />
10 uA (G3)<br />
80 uA (S0)<br />
AA25 +VDD_CORE1<br />
AC23 +VDD_CORE2<br />
U25 +VDD_CORE3<br />
AH12 +VDD_CORE4<br />
AG10 +VDD_CORE5<br />
AG5 +VDD_CORE6<br />
Y21 +VDD_CORE7<br />
Y23 +VDD_CORE8<br />
AA16 +VDD_CORE9<br />
AA26 +VDD_CORE10<br />
AA27 +VDD_CORE11<br />
AA28 +VDD_CORE12<br />
AC16 +VDD_CORE13<br />
AC17 +VDD_CORE14<br />
AC18 +VDD_CORE15<br />
AC19 +VDD_CORE16<br />
AC20 +VDD_CORE17<br />
AC21 +VDD_CORE18<br />
AA17 +VDD_CORE19<br />
AC24 +VDD_CORE20<br />
AC25 +VDD_CORE21<br />
AC26 +VDD_CORE22<br />
AC27 +VDD_CORE23<br />
AC28 +VDD_CORE24<br />
AD21 +VDD_CORE25<br />
AD23 +VDD_CORE26<br />
W27 +VDD_CORE27<br />
V25 +VDD_CORE28<br />
AA18 +VDD_CORE29<br />
AE19 +VDD_CORE30<br />
AE21 +VDD_CORE31<br />
AE23 +VDD_CORE32<br />
AE25 +VDD_CORE33<br />
AE26 +VDD_CORE34<br />
AE27 +VDD_CORE35<br />
AE28 +VDD_CORE36<br />
AF10 +VDD_CORE37<br />
AF11 +VDD_CORE38<br />
AA19 +VDD_CORE39<br />
AF2 +VDD_CORE40<br />
AF21 +VDD_CORE41<br />
AF23 +VDD_CORE42<br />
AF25 +VDD_CORE43<br />
AF3 +VDD_CORE44<br />
AF4 +VDD_CORE45<br />
AF7 +VDD_CORE46<br />
AH23 +VDD_CORE47<br />
AF9 +VDD_CORE48<br />
AA20 +VDD_CORE49<br />
AG11 +VDD_CORE50<br />
AG12 +VDD_CORE51<br />
AG21 +VDD_CORE52<br />
AG23 +VDD_CORE53<br />
AG25 +VDD_CORE54<br />
AG3 +VDD_CORE55<br />
AG4 +VDD_CORE56<br />
AA21 +VDD_CORE57<br />
AG6 +VDD_CORE58<br />
AG7 +VDD_CORE59<br />
AG8 +VDD_CORE60<br />
AG9 +VDD_CORE61<br />
AH1 +VDD_CORE62<br />
AH10 +VDD_CORE63<br />
AH11 +VDD_CORE64<br />
W26 +VDD_CORE65<br />
AH2 +VDD_CORE66<br />
AA23 +VDD_CORE67<br />
W28 +VDD_CORE68<br />
AH25 +VDD_CORE69<br />
AH21 +VDD_CORE70<br />
AH3 +VDD_CORE71<br />
AH4 +VDD_CORE72<br />
AH5 +VDD_CORE73<br />
AH6 +VDD_CORE74<br />
AH7 +VDD_CORE75<br />
AH9 +VDD_CORE76<br />
AA24 +VDD_CORE77<br />
W21 +VDD_CORE78<br />
W23 +VDD_CORE79<br />
W25 +VDD_CORE80<br />
AF12 +VDD_CORE81<br />
A20<br />
+VBAT<br />
U1400<br />
MCP79-TOPO-B<br />
BGA<br />
(10 OF 11)<br />
POWER<br />
+VTT_CPU1 R32<br />
+VTT_CPU2 AC32<br />
+VTT_CPU3 E40<br />
+VTT_CPU4 J36<br />
+VTT_CPU5 N32<br />
+VTT_CPU6 T32<br />
+VTT_CPU7 U32<br />
+VTT_CPU8 V32<br />
+VTT_CPU9 W32<br />
+VTT_CPU10 P31<br />
+VTT_CPU11 AF32<br />
+VTT_CPU12 AE32<br />
+VTT_CPU13 AH32<br />
+VTT_CPU14 AJ32<br />
+VTT_CPU15 AK31<br />
+VTT_CPU16 AK32<br />
+VTT_CPU17 AD32<br />
+VTT_CPU18 AL31<br />
+VTT_CPU19 AB32<br />
+VTT_CPU20 B41<br />
+VTT_CPU21 B42<br />
+VTT_CPU22 C40<br />
+VTT_CPU23 C41<br />
+VTT_CPU24 C42<br />
+VTT_CPU25 D39<br />
+VTT_CPU26 D40<br />
+VTT_CPU27 D41<br />
+VTT_CPU28 E38<br />
+VTT_CPU29 E39<br />
+VTT_CPU30 F37<br />
+VTT_CPU31 F38<br />
+VTT_CPU32 F39<br />
+VTT_CPU33 G36<br />
+VTT_CPU34 G37<br />
+VTT_CPU35 G38<br />
+VTT_CPU36 H35<br />
+VTT_CPU37 H37<br />
+VTT_CPU38 J34<br />
+VTT_CPU39 J35<br />
+VTT_CPU40 K33<br />
+VTT_CPU41 K34<br />
+VTT_CPU42 K35<br />
+VTT_CPU43 L32<br />
+VTT_CPU44 L33<br />
+VTT_CPU45 L34<br />
+VTT_CPU46 M31<br />
+VTT_CPU47 M32<br />
+VTT_CPU48 M33<br />
+VTT_CPU49 N31<br />
+VTT_CPU50 P32<br />
+VTT_CPU51 Y32<br />
+VTT_CPU52 AA32<br />
+VTT_CPUCLK<br />
AG32<br />
+3.3V_1 AD10<br />
+3.3V_2 AE8<br />
+3.3V_3 AB10<br />
+3.3V_4 AD9<br />
+3.3V_5 Y10<br />
+3.3V_6 AB11<br />
+3.3V_7 AA8<br />
+3.3V_8 Y9<br />
+3.3V_DUAL1 G18<br />
+3.3V_DUAL2 H19<br />
+3.3V_DUAL3 J20<br />
+3.3V_DUAL4 K20<br />
+3.3V_DUAL_USB1 G26<br />
+3.3V_DUAL_USB2 H27<br />
+3.3V_DUAL_USB3 J28<br />
+3.3V_DUAL_USB4 K28<br />
+VDD_AUXC1 T21<br />
+VDD_AUXC2 U21<br />
+VDD_AUXC3 V21<br />
=PP1V05_S0_MCP_FSB<br />
7D7 13A2 13B7 22C8<br />
1139 mA<br />
1182 mA (A01)<br />
43 mA<br />
=PP3V3_S0_MCP<br />
7C5 20C2 22B8<br />
450 mA (A01)<br />
=PP3V3_S5_MCP<br />
7A3 22B8<br />
16 mA 266 mA (A01)<br />
250 mA<br />
=PP1V05_S5_MCP_VDD_AUXC<br />
7B3 22D8<br />
105 mA (A01)<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
MCP Power & Ground<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=04/04/2008<br />
D<br />
C<br />
B<br />
A<br />
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).<br />
8 7 6 5 4 3 2 1<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
21 81<br />
REV.<br />
4.7.0
8 7 6 5 4 3 2 1<br />
MCP Core Power<br />
21D5 7C6 =PPVCORE_S0_MCP<br />
23065 mA (A01, 1.2V)<br />
16996 mA (A01, 1.0V)<br />
(No IG vs. EG data)<br />
C2500 1 2<br />
4.7UF<br />
20%<br />
4V<br />
X5R-1<br />
402<br />
NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)<br />
Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)<br />
C2501 1 2<br />
4.7UF<br />
20%<br />
4V<br />
X5R-1<br />
402<br />
C2502 1 C2503 1 1<br />
C2504<br />
1<br />
C2505<br />
1<br />
C2506<br />
1<br />
C2507<br />
4.7UF<br />
1UF<br />
1UF<br />
1UF<br />
1UF<br />
20%<br />
10%<br />
10%<br />
10%<br />
10%<br />
4V<br />
10V<br />
10V<br />
10V<br />
10V<br />
2 2 2<br />
2<br />
2<br />
2<br />
4.7UF<br />
20%<br />
4V<br />
X5R-1<br />
402<br />
X5R-1<br />
402<br />
X5R<br />
402-1<br />
X5R<br />
402-1<br />
X5R<br />
402-1<br />
X5R<br />
402-1<br />
1<br />
C2508<br />
0.1UF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
1<br />
C2509<br />
0.1UF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
1<br />
C2510<br />
0.1UF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
1<br />
C2511<br />
0.1UF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
1<br />
C2512<br />
0.1UF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
1<br />
C2513<br />
0.1UF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
D<br />
MCP PCIE (DVDD) Power<br />
7D7 7A8 =PP1V05_S0_MCP_PEX_DVDD<br />
57 mA (A01)<br />
C2515 1 2<br />
4.7UF<br />
20%<br />
4V<br />
X5R-1<br />
402<br />
1<br />
2<br />
C2516<br />
1UF<br />
10%<br />
10V<br />
X5R<br />
402-1<br />
1<br />
2<br />
C2517<br />
1UF<br />
10%<br />
10V<br />
X5R<br />
402-1<br />
1<br />
2<br />
C2518<br />
0.1uF<br />
20%<br />
10V<br />
CERM<br />
402<br />
MCP SATA (DVDD) Power<br />
7D7 7A8 =PP1V05_S0_MCP_SATA_DVDD<br />
43 mA (A01)<br />
1<br />
C2519<br />
0.1uF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
4.7UF<br />
20%<br />
4V<br />
X5R-1<br />
402<br />
333 mA (A01)<br />
C2520 1 1<br />
C2521<br />
1<br />
C2570<br />
0.1uF<br />
2.2UF<br />
20%<br />
20%<br />
10V<br />
6.3V<br />
2 2<br />
2<br />
CERM<br />
402<br />
7D7<br />
=PP1V05_S0_MCP_AVDD_UF<br />
1<br />
L2570<br />
30-OHM-5A<br />
0603<br />
2<br />
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)<br />
Apple: 5x 2.2uF 0402 (11 uF)<br />
PP1V05_S0_MCP_PEX_AVDD<br />
MIN_LINE_WIDTH=0.4 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
CERM<br />
402-LF<br />
1<br />
C2571<br />
2<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
1<br />
C2572<br />
2<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
1<br />
C2573<br />
2<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
1<br />
C2574<br />
2<br />
VOLTAGE=1.05V<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
7A8<br />
206 mA (A01)<br />
D<br />
MCP 1.05V AUX Power<br />
21A3 7B3 =PP1V05_S5_MCP_VDD_AUXC<br />
105 mA (A01)<br />
1<br />
C2525<br />
0.1uF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
1<br />
C2526<br />
0.1uF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
MCP 1.05V RMGT Power<br />
17D3 7A5 =PP1V05_ENET_MCP_RMGT<br />
131 mA (A01)<br />
C2528 1<br />
4.7UF<br />
20%<br />
4V<br />
X5R-1<br />
2<br />
402<br />
1<br />
C2529<br />
0.1uF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
L2575<br />
30-OHM-5A<br />
1<br />
0603<br />
2<br />
2<br />
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)<br />
Apple: 2x 2.2uF 0402 (4.4 uF)<br />
PP1V05_S0_MCP_SATA_AVDD<br />
7A8<br />
MIN_LINE_WIDTH=0.4 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
127 mA (A01)<br />
VOLTAGE=1.05V<br />
1<br />
C2575<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
1<br />
C2576<br />
2.2UF<br />
2<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
C<br />
MCP FSB (VTT) Power<br />
21D3 13B7 13A2 7D7 =PP1V05_S0_MCP_FSB<br />
1182 mA (A01)<br />
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)<br />
Apple: 7x 2.2uF 0402 (15.4 uF)<br />
1<br />
C2530<br />
2<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
1<br />
C2531<br />
2.2UF<br />
2<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
1<br />
C2532<br />
2.2UF<br />
20%<br />
6.3V<br />
2<br />
CERM<br />
402-LF<br />
1<br />
2<br />
C2533<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
1<br />
C2534<br />
2<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
1<br />
C2535<br />
2<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
1<br />
C2536<br />
2<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
65B1 7B8 =PP1V05_S0_MCP_PLL_UF<br />
562 mA (A01)<br />
L2580<br />
30-OHM-1.7A<br />
1<br />
0402<br />
2<br />
C2592<br />
10UF<br />
20%<br />
6.3V<br />
X5R<br />
603<br />
1<br />
2<br />
C2580 1 2<br />
4.7UF<br />
20%<br />
4V<br />
X5R-1<br />
402<br />
1<br />
2<br />
PP1V05_S0_MCP_PLL_FSB 13A6<br />
MIN_LINE_WIDTH=0.4 MM<br />
MIN_NECK_WIDTH=0.2 MM 270 mA (A01)<br />
VOLTAGE=1.05V<br />
C2581<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
C<br />
MCP Memory Power<br />
15C7 15C3 7B6 =PP1V8R1V5_S0_MCP_MEM<br />
4771 mA (A01, DDR3)<br />
C2540 1 2<br />
4.7UF<br />
20%<br />
4V<br />
X5R-1<br />
402<br />
1<br />
C2541<br />
0.1UF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
1<br />
C2542<br />
0.1UF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
1<br />
C2543<br />
0.1UF<br />
2<br />
20%<br />
10V<br />
CERM<br />
402<br />
1<br />
C2544<br />
0.1UF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
1<br />
C2545<br />
0.1UF<br />
2<br />
20%<br />
10V<br />
CERM<br />
402<br />
1<br />
C2546<br />
0.1UF<br />
2<br />
20%<br />
10V<br />
CERM<br />
402<br />
1<br />
C2547<br />
0.1UF<br />
2<br />
20%<br />
10V<br />
CERM<br />
402<br />
1<br />
C2548<br />
0.1UF<br />
2<br />
20%<br />
10V<br />
CERM<br />
402<br />
1<br />
C2549<br />
0.1UF<br />
2<br />
20%<br />
10V<br />
CERM<br />
402<br />
L2582<br />
30-OHM-1.7A<br />
1<br />
2<br />
0402<br />
C2582 1 2<br />
4.7UF<br />
20%<br />
4V<br />
X5R-1<br />
402<br />
1<br />
2<br />
PP1V05_S0_MCP_PLL_PEX<br />
MIN_LINE_WIDTH=0.4 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=1.05V<br />
C2583<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
16A6<br />
84 mA (A01)<br />
B<br />
MCP 3.3V Power<br />
21B3 20C2 7C5 =PP3V3_S0_MCP<br />
450 mA (A01)<br />
NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)<br />
Apple: 4x 2.2uF 0402 (8.8 uF)<br />
1<br />
C2550<br />
2.2UF<br />
20%<br />
2<br />
6.3V<br />
CERM<br />
402-LF<br />
1<br />
C2551<br />
2.2UF<br />
2<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
1<br />
C2552<br />
2.2UF<br />
20%<br />
2<br />
6.3V<br />
CERM<br />
402-LF<br />
1<br />
C2553<br />
2.2UF<br />
2<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
7C5<br />
=PP3V3_S0_MCP_PLL_UF<br />
19 mA (A01)<br />
L2555<br />
30-OHM-1.7A<br />
1<br />
0402<br />
2<br />
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)<br />
Apple: 1x 2.2uF 0402 (2.2 uF)<br />
PP3V3_S0_MCP_PLL_USB<br />
19C3<br />
MIN_LINE_WIDTH=0.4 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
19 mA (A01)<br />
VOLTAGE=3.3V<br />
1<br />
C2555<br />
2.2UF<br />
2<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
L2584<br />
30-OHM-1.7A<br />
1<br />
2<br />
0402<br />
C2584 1 2<br />
4.7UF<br />
20%<br />
4V<br />
X5R-1<br />
402<br />
1<br />
2<br />
PP1V05_S0_MCP_PLL_SATA<br />
MIN_LINE_WIDTH=0.4 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=1.05V<br />
C2585<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
19B6<br />
84 mA (A01)<br />
B<br />
MCP 3.3V AUX/USB Power<br />
21B3 7A3 =PP3V3_S5_MCP<br />
266 mA (A01)<br />
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)<br />
Apple: 1x 2.2uF 0402 (2.2 uF)<br />
1<br />
2<br />
C2560<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
MCP 3.3V Ethernet Power<br />
22A5 17D7 17D3 7B5 =PP3V3_ENET_MCP_RMGT<br />
83 mA (A01)<br />
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)<br />
Apple: 1x 2.2uF 0402 (2.2 uF)<br />
1<br />
C2564<br />
2.2UF<br />
2<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
L2586<br />
30-OHM-1.7A<br />
1<br />
0402<br />
2<br />
C2586 1 2<br />
4.7UF<br />
20%<br />
4V<br />
X5R-1<br />
402<br />
1<br />
2<br />
PP1V05_S0_MCP_PLL_CORE<br />
MIN_LINE_WIDTH=0.4 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=1.05V<br />
C2587<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
15C6<br />
87 mA (A01)<br />
MCP 3.3V/1.5V HDA Power<br />
20D8 20D3 7C5 =PP3V3R1V5_S0_MCP_HDA<br />
7 mA (A01)<br />
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)<br />
Apple: 1x 2.2uF 0402 (2.2 uF)<br />
1<br />
C2562<br />
2<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
22B6 17D7 17D3 7B5<br />
=PP3V3_ENET_MCP_RMGT<br />
MCP79 Ethernet VRef<br />
L2588<br />
30-OHM-1.7A<br />
1<br />
2<br />
0402<br />
C2588 1 2<br />
4.7UF<br />
20%<br />
4V<br />
X5R-1<br />
402<br />
1<br />
2<br />
C2589<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
PP1V05_S0_MCP_PLL_NV<br />
MIN_LINE_WIDTH=0.4 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=1.05V<br />
1<br />
C2590<br />
0.1UF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
20C7<br />
37 mA (A01)<br />
A<br />
7B5<br />
=PP1V05_ENET_MCP_PLL_MAC<br />
5 mA (A01)<br />
L2595<br />
30-OHM-1.7A<br />
1<br />
C2595 1 2<br />
4.7UF<br />
20%<br />
4V<br />
X5R-1<br />
402<br />
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).<br />
0402<br />
2<br />
PP1V05_ENET_MCP_PLL_MAC<br />
MIN_LINE_WIDTH=0.4 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=1.05V<br />
1<br />
C2596<br />
0.1UF<br />
2<br />
20%<br />
10V<br />
CERM<br />
402<br />
17C6<br />
5 mA (A01)<br />
R2591<br />
1.47K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
R2590<br />
1.47K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
2<br />
1<br />
2<br />
1<br />
C2591<br />
0.1UF<br />
2<br />
MCP_MII_VREF<br />
20%<br />
10V<br />
CERM<br />
402<br />
8 7 6 5 4 3 2 1<br />
OUT 17D3<br />
APPLE INC.<br />
MCP Standard Decoupling<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
22<br />
SYNC_DATE=04/04/2008<br />
81<br />
A
8 7 6 5 4 3 2 1<br />
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.<br />
D<br />
17B6 7B6<br />
=PP3V3R1V8_S0_MCP_IFP_VDD<br />
190 mA (A01, 1.8V)<br />
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)<br />
Apple: 1x 2.2uF 0402 (2.2 uF)<br />
1<br />
C2610<br />
2.2UF<br />
20%<br />
6.3V<br />
2 CERM<br />
402-LF<br />
NO STUFF NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)<br />
L2650 Apple: 2x 2.2uF 0402 (4.4 uF)<br />
30-OHM-1.7A<br />
7C5 =PP3V3_S0_MCP_DAC_UF<br />
PP3V3_S0_MCP_DAC<br />
17C3<br />
MIN_LINE_WIDTH=0.4 MM<br />
1<br />
2<br />
206 mA (A01) MIN_NECK_WIDTH=0.2 MM<br />
206 mA (A01)<br />
VOLTAGE=3.3V<br />
0402<br />
NO STUFF<br />
1<br />
C2650<br />
1 R2651<br />
2.2UF<br />
0<br />
5%<br />
20%<br />
6.3V<br />
1/16W<br />
2<br />
CERM<br />
MF-LF<br />
402-LF<br />
402<br />
2<br />
D<br />
17A6 7D7<br />
=PP1V05_S0_MCP_HDMI_VDD<br />
95 mA (A01)<br />
1<br />
C2616<br />
C2615 1 2<br />
4.7UF<br />
20%<br />
4V<br />
X5R-1<br />
402<br />
0.1UF<br />
20%<br />
10V<br />
2 CERM<br />
402<br />
C<br />
75B3 17A6 MCP_HDMI_RSET<br />
75B3 17A6 MCP_HDMI_VPROBE<br />
NO STUFF<br />
1<br />
C2620<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
2<br />
402<br />
1<br />
R2620<br />
1K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
75B3 17A3 MCP_IFPAB_RSET<br />
75B3 17A3 MCP_IFPAB_VPROBE<br />
NO STUFF<br />
1<br />
C2630<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
2<br />
402<br />
NO STUFF<br />
1<br />
R2630<br />
1K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
C<br />
7C5<br />
=PP3V3_S0_MCP_VPLL_UF<br />
16 mA (A01)<br />
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.<br />
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)<br />
L2640 Apple: ???<br />
30-OHM-1.7A<br />
PP3V3_S0_MCP_VPLL<br />
17B6<br />
MIN_LINE_WIDTH=0.4 MM<br />
1<br />
2<br />
MIN_NECK_WIDTH=0.2 MM<br />
16 mA (A01)<br />
VOLTAGE=3.3V<br />
0402<br />
C2640<br />
4.7UF<br />
20%<br />
6.3V<br />
CERM<br />
603<br />
1<br />
2<br />
1<br />
C2641<br />
2<br />
0.1uF<br />
20%<br />
10V<br />
CERM<br />
402<br />
B<br />
B<br />
A<br />
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).<br />
SYNC FROM T18<br />
REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT<br />
REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672<br />
NOSTUFF PP3V3_S0_MCP_DAC RAIL COMPONENTS (L2650 AND C2650)<br />
CHANGE C2651 TO R2651 TO GND PP3V3_S0_MCP_DAC<br />
REMOVE HDCP ROMS<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
8 7 6 5 4 3 2 1<br />
APPLE INC.<br />
MCP Graphics Support<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
SYNC_DATE=12/12/2007<br />
OF<br />
23 81<br />
REV.<br />
4.7.0<br />
A
8 7 6 5 4 3 2 1<br />
D<br />
7D1 =PP3V42_G3H_RTC_D<br />
1<br />
2<br />
C2870<br />
1UF<br />
10%<br />
10V<br />
X5R<br />
402<br />
3<br />
1<br />
VIN<br />
U2801<br />
MIC5232-2.8YD5<br />
TSOT-23-5<br />
EN CRITICAL VOUT<br />
SUPERCAP_YES<br />
GND<br />
2<br />
NC<br />
5<br />
4<br />
RTC Power Sources<br />
SUPERCAP_YES<br />
1<br />
C2871<br />
0.47UF<br />
10%<br />
10V<br />
2<br />
X5R<br />
402<br />
SUPERCAP_YES<br />
R2819<br />
100<br />
402<br />
1 2<br />
MF-LF<br />
PP3V3_G3_SUPERCAP SUPERCAP_YES<br />
1<br />
C2800<br />
0.08F<br />
2%<br />
2 3.3V<br />
XHHG<br />
SM<br />
C2819<br />
10%<br />
1UF<br />
6.3V<br />
CERM<br />
402<br />
1<br />
2<br />
PP3V3_G3_RTC 6C3 20C8 21A5<br />
MIN_LINE_WIDTH=0.3 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=3.3V<br />
76C3 18C3<br />
PLACE C2819 CLOSE TO MCP79<br />
PLACE C2800 AT COOLEST SPOT ON <strong>MLB</strong><br />
IN<br />
PLACEMENT_NOTE=PLACE C2819 CLOSE TO MCP79<br />
LPC_RESET_L<br />
Platform Reset Connections<br />
LPC Reset (Unbuffered)<br />
PLACEMENT_NOTE=Place close to U1400<br />
R2881<br />
33<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
PLACEMENT_NOTE=Place close to U1400<br />
R2883<br />
33<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
PCIE Reset (Unbuffered)<br />
DEBUG_RESET_L<br />
SMC_LRESET_L<br />
OUT<br />
OUT<br />
42D5<br />
40C8<br />
D<br />
C<br />
20B7<br />
20B7<br />
IN<br />
OUT<br />
RTC_CLK32K_XTALOUT<br />
RTC_CLK32K_XTALIN<br />
NO STUFF<br />
1<br />
R2811<br />
10M<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
RTC Crystal<br />
R2810<br />
1<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
CRITICAL<br />
Y2810<br />
32.768K<br />
7X1.5X1.4-SM<br />
SUPERCAP_NO<br />
R2820<br />
0<br />
1<br />
2<br />
1 4<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
RTC_CLK32K_XTALOUT_R<br />
C2810<br />
12pF<br />
1 2<br />
5%<br />
50V<br />
CERM<br />
402<br />
C2811<br />
12pF<br />
1 2<br />
16B3<br />
IN<br />
PCIE_RESET_L<br />
MAKE_BASE=TRUE<br />
R2891<br />
0<br />
1<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R2895<br />
0<br />
1<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
R2892<br />
0<br />
1<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R2871<br />
0<br />
1<br />
2<br />
BKLT_PLT_RST_L<br />
MINI_RESET_L<br />
PCA9557D_RESET_L<br />
=FW_RESET_L<br />
CARDREADER_PLT_RST_L<br />
OUT 72C8<br />
OUT 29A6<br />
OUT 25A5<br />
OUT 35D1<br />
OUT 30A7<br />
C<br />
B<br />
A<br />
66A4 40D8<br />
62C7<br />
20B3<br />
20B7<br />
20B7<br />
IN<br />
IN<br />
IN<br />
IN<br />
OUT<br />
MCP_CLK25M_XTALOUT<br />
MCP_CLK25M_XTALIN<br />
7A3<br />
ALL_SYS_PWRGD<br />
VR_PWRGOOD_DELAY<br />
MCP_CPUVDD_EN<br />
MCP 25MHz Crystal<br />
NO STUFF<br />
1<br />
R2816<br />
1M<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R2815<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
3CRITICAL<br />
Y2815<br />
25.0000M<br />
SM-3.2X2.5MM<br />
NC<br />
NC<br />
MCP S0 PWRGD & CPU_VLD<br />
=PP3V3_S5_MCPPWRGD<br />
5 TC7SZ08AFEAPE<br />
2 SOT665<br />
A<br />
U2850Y<br />
4 S0_AND_IMVP_PGOOD<br />
1<br />
B<br />
MCPSEQ_SMC represents MCP79 ’<strong>MLB</strong>’ power sequencing connections,<br />
but results in MCP79 ROMSIP sequence happening after CPU powers up.<br />
MCPSEQ_MIX is cross between <strong>MLB</strong> and internal power sequencing, which<br />
results in earlier ROMSIP and MCP FSB I/O interface initialization.<br />
SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for<br />
VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before<br />
CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).<br />
NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.<br />
3<br />
MCPSEQ_SMC<br />
1<br />
C2850<br />
0.1UF<br />
2<br />
20%<br />
10V<br />
CERM<br />
402<br />
1<br />
1<br />
MCP_CLK25M_XTALOUT_R<br />
2 4<br />
MCPSEQ_MIX<br />
R2851<br />
0<br />
1<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
PLACEMENT_NOTE=Place close to U1400<br />
2<br />
MCPSEQ_SMC<br />
R2853<br />
0<br />
1<br />
MCPSEQ_MIX<br />
R2852<br />
0<br />
1<br />
MCPSEQ_SMC<br />
R2850<br />
0<br />
1<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
2<br />
2<br />
5%<br />
50V<br />
CERM<br />
402<br />
C2815<br />
12pF<br />
1 2<br />
5%<br />
50V<br />
CERM<br />
402<br />
C2816<br />
12pF<br />
1 2<br />
5%<br />
50V<br />
CERM<br />
402<br />
OUT<br />
SYNC FROM T18<br />
CHANGE RESET BUTTOM TO RESET PADS<br />
REMOVE UNUSED PCIE RESET SIGNALS<br />
REMOVE R2824 AND NET PCI_CLK33M_SLOT_A<br />
CHANGE RTC COIN CELL TO LDO & SUPERCAP<br />
ALIAS MEM_VTT_EN TO =DDRVTT_EN<br />
CHANGE Y2810 AND U2850 TO SMALLER PARTS<br />
8 7 6 5 4 3 2 1<br />
18C4<br />
76C3 18B3<br />
76A3 20B3<br />
IN<br />
IN<br />
IN<br />
R2870<br />
33<br />
1<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
PLACEMENT_NOTE=Place close to U1400<br />
R2825<br />
33<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
PLACEMENT_NOTE=Place close to U1400<br />
PLACEMENT_NOTE=Place close to U1400<br />
R2829<br />
22<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
Reset Button<br />
40B8 IN PM_SYSRST_L<br />
XDP<br />
R2898<br />
R2899 10K pull-up to 3.3V S0 inside MCP<br />
0<br />
33<br />
MCP_PS_PWRGD<br />
OUT 20B7<br />
12B3 9C6 IN<br />
XDP_DBRESET_L 1 2<br />
1<br />
2 PM_SYSRST_DEBOUNCE_L<br />
OUT 20C7<br />
5%<br />
NO STUFF<br />
5%<br />
1<br />
NO STUFF<br />
1/16W<br />
1/16W<br />
MF-LF<br />
R2890<br />
MF-LF<br />
1<br />
C2899<br />
402<br />
0<br />
402<br />
1UF<br />
5%<br />
10%<br />
10V<br />
MCP_CPU_VLD<br />
20B7<br />
MEM_VTT_EN_R<br />
LPC_CLK33M_SMC_R<br />
PM_CLK32K_SUSCLK_R<br />
1/16W<br />
MF-LF<br />
402<br />
MEM_VTT_EN<br />
MAKE_BASE=TRUE<br />
2<br />
SILK_PART=SYS RST<br />
R2826<br />
33<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
X5R<br />
402<br />
APPLE INC.<br />
2<br />
=DDRVTT_EN<br />
LPC_CLK33M_SMC<br />
SYNC_MASTER=RAYMOND<br />
LPC_CLK33M_LPCPLUS<br />
PM_CLK32K_SUSCLK<br />
SCALE<br />
NONE<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SB Misc<br />
DRAWING NUMBER<br />
SHT<br />
051-7898<br />
24<br />
61C8 67A3<br />
40C8 76C3<br />
42D3 76C3<br />
40C5 76A3<br />
SYNC_DATE=04/05/2008<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
B<br />
A
D<br />
C<br />
B<br />
8 7 6 5 4 3 2 1<br />
Page Notes<br />
Power aliases required by this page:<br />
- =PP3V3_S3_VREFMRGN<br />
- =PP3V3_S5_VREFMRGN<br />
- =PPVTT_S3_DDR_BUF<br />
Signal aliases required by this page:<br />
- =I2C_VREFDACS_SCL<br />
- =I2C_VREFDACS_SDA<br />
- =I2C_PCA9557D_SCL<br />
- =I2C_PCA9557D_SDA<br />
BOM options provided by this page:<br />
VREFMRGN<br />
NO_VREFMRGN<br />
=PP3V3_S3_VREFMRGN<br />
7D3<br />
43B3<br />
43B3<br />
IN<br />
BI<br />
VREFMRGN<br />
C2900<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
ADDR=0x98(WR)/0x99(RD)<br />
MEM A VREF DQ<br />
6 SCL<br />
7 SDA<br />
9 A0<br />
8<br />
VDD<br />
MSOP VOUTA 1<br />
VOUTB 2<br />
VOUTC 4<br />
10 A1<br />
VOUTD 5<br />
GND<br />
3<br />
MEM A VREF CA<br />
NC<br />
MEM B VREF DQ<br />
MEM B VREF CA<br />
CPU FSB VREF<br />
DAC channel A B A B C<br />
Min DAC code 0x00 0x00 0x00 0x00 0x00<br />
Max DAC code 0x87 0x87 0x87 0x87 0x55<br />
Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA<br />
Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA<br />
Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V<br />
Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V<br />
Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V<br />
Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV<br />
(per DAC LSB)<br />
VREFMRGN<br />
1 C2901<br />
0.1UF<br />
20%<br />
2<br />
10V<br />
CERM<br />
402<br />
=I2C_VREFDACS_SCL<br />
=I2C_VREFDACS_SDA<br />
DAC5574<br />
VREFMRGN<br />
U2900<br />
VREFMRGN_DQ_SODIMM<br />
VREFMRGN_CA_SODIMM<br />
VREFMRGN_CPUFSB<br />
1<br />
VREFMRGN<br />
C2903<br />
0.1UF<br />
20%<br />
10V<br />
2 CERM<br />
402<br />
VREFMRGN<br />
1 C2904<br />
0.1UF<br />
20%<br />
10V<br />
2 CERM<br />
402<br />
VREFMRGN<br />
1 C2905<br />
0.1UF<br />
20%<br />
2<br />
10V<br />
CERM<br />
402<br />
A3<br />
C3<br />
A3<br />
C3<br />
V-<br />
B4<br />
V-<br />
B4<br />
V-<br />
B4<br />
V-<br />
B4<br />
SO-DIMM A and SO-DIMM B Vref settings should be margined separately<br />
(i.e. not simultaneously) due to current limitation of TPS51116 regulator.<br />
U2902<br />
B1<br />
A2<br />
MAX4253<br />
V+ UCSP<br />
VREFMRGN<br />
A1<br />
A4<br />
U2902<br />
B1<br />
C2<br />
MAX4253<br />
V+ UCSP<br />
VREFMRGN<br />
C1<br />
C4<br />
U2903<br />
B1<br />
A2<br />
MAX4253<br />
V+ UCSP<br />
VREFMRGN<br />
A1<br />
A4<br />
U2903<br />
B1<br />
C2<br />
MAX4253<br />
V+ UCSP<br />
VREFMRGN<br />
C1<br />
C4<br />
U2904<br />
B1<br />
A2<br />
MAX4253<br />
V+ UCSP<br />
VREFMRGN<br />
A1<br />
NC<br />
A3<br />
A4<br />
V-<br />
B4<br />
=PPVTT_S3_DDR_BUF<br />
61D8 7C4<br />
10mA max load<br />
VREFMRGN_DQ_SODIMMA_BUF<br />
25A5 VREFMRGN_DQ_SODIMMA_EN<br />
R2901<br />
100K<br />
R2902<br />
100K<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
VREFMRGN_DQ_SODIMMB_BUF<br />
25A5 VREFMRGN_DQ_SODIMMB_EN<br />
2<br />
VREFMRGN<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
R2907<br />
100K<br />
1<br />
VREFMRGN_CA_SODIMMA_BUF<br />
25B5 VREFMRGN_CA_SODIMMA_EN<br />
2<br />
1<br />
VREFMRGN<br />
VREFMRGN<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
VREFMRGN_CA_SODIMMB_BUF<br />
25A5 VREFMRGN_CA_SODIMMB_EN<br />
R2908<br />
100K<br />
2<br />
VREFMRGN<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
R2903<br />
1<br />
R2904<br />
100<br />
1 2<br />
1<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
R2905<br />
R2906<br />
100<br />
1 2<br />
1<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
R2909<br />
R2910<br />
100<br />
1 2<br />
1<br />
200<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
200<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
200<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
R2911<br />
200<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
R2912<br />
100<br />
1 2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
2<br />
2<br />
2<br />
VREFMRGN<br />
VREFMRGN<br />
VREFMRGN<br />
VREFMRGN<br />
VREFMRGN<br />
VREFMRGN<br />
VREFMRGN<br />
VREFMRGN<br />
PP0V75_S3_MEM_VREFDQ_A<br />
MIN_LINE_WIDTH=0.3 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
Place close to J3100.1<br />
PP0V75_S3_MEM_VREFDQ_B<br />
Place close to J3200.1<br />
Place close to J3100.126<br />
Place close to J3200.126<br />
D<br />
C<br />
B<br />
IN<br />
BI<br />
ADDR=0x30(WR)/0x31(RD)<br />
1<br />
VREFMRGN<br />
C2902<br />
0.1UF<br />
20%<br />
2<br />
10V<br />
CERM<br />
402<br />
3 A0<br />
4 A1<br />
5 A2<br />
1 SCL<br />
2 SDA<br />
16<br />
VCC<br />
U2901<br />
PCA9557<br />
QFN<br />
VREFMRGN<br />
P0 6<br />
P1 7<br />
P2 9<br />
P3 10<br />
P4 11<br />
P5 12<br />
P6 13<br />
P7 14<br />
THRM RESET* 15<br />
PAD GND<br />
NC<br />
NC<br />
NC<br />
25B3<br />
25C3<br />
25D3<br />
25B3<br />
25C3<br />
IN<br />
C2<br />
C3<br />
U2904<br />
B1<br />
MAX4253<br />
V+ UCSP<br />
VREFMRGN<br />
C1<br />
C4<br />
V-<br />
B4<br />
R2914<br />
100<br />
1 2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
VREFMRGN<br />
Place close to U1000.AD26<br />
OUT<br />
17<br />
8<br />
MIN_LINE_WIDTH=0.3 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
PP0V75_S3_MEM_VREFCA_A<br />
MIN_LINE_WIDTH=0.3 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
PP0V75_S3_MEM_VREFCA_B<br />
MIN_LINE_WIDTH=0.3 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
26D5<br />
27D5<br />
26B3<br />
27B3<br />
43A3<br />
43A3<br />
=I2C_PCA9557D_SCL<br />
=I2C_PCA9557D_SDA<br />
VREFMRGN_CPUFSB_EN<br />
VREFMRGN_CA_SODIMMA_EN<br />
VREFMRGN_DQ_SODIMMA_EN<br />
VREFMRGN_CA_SODIMMB_EN<br />
VREFMRGN_DQ_SODIMMB_EN<br />
PCA9557D_RESET_L<br />
24C1<br />
VREFMRGN_CPUFSB_BUF<br />
25B5 VREFMRGN_CPUFSB_EN<br />
R2913<br />
100K<br />
1 2<br />
VREFMRGN<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
CPU_GTLREF<br />
9B4 73B3<br />
A<br />
FSB/DDR3 Vref Margining<br />
SYNC_MASTER=BEN<br />
SYNC_DATE=03/31/2008<br />
NOTICE OF PROPRIETARY PROPERTY<br />
A<br />
Required zero ohm resistors when no VREF margining circuit stuffed<br />
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION<br />
116S0004 1 RES,MTL FILM,0,5%,0402,SM,LF R2903 CRITICAL NO_VREFMRGN<br />
116S0004 1 RES,MTL FILM,0,5%,0402,SM,LF R2905 CRITICAL NO_VREFMRGN<br />
116S0004 1 RES,MTL FILM,0,5%,0402,SM,LF R2909 CRITICAL NO_VREFMRGN<br />
116S0004 1 RES,MTL FILM,0,5%,0402,SM,LF R2911 CRITICAL NO_VREFMRGN<br />
APPLE INC.<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
25<br />
81<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
Page Notes<br />
Power aliases required by this page:<br />
7D3 =PP1V5_S3_MEM_A<br />
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)<br />
- =PP1V5_S0_MEM_A<br />
- =PP1V5_S3_MEM_A<br />
- =PP0V75_S0_MEM_VTT_A<br />
- =PPSPD_S0_MEM_A (2.5 - 3.3V)<br />
Signal aliases required by this page:<br />
1<br />
C3100<br />
10UF<br />
2<br />
20%<br />
6.3V<br />
X5R<br />
603<br />
1<br />
2<br />
C3101<br />
10UF<br />
20%<br />
6.3V<br />
X5R<br />
603<br />
1<br />
C3110<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
1<br />
C3111<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
1<br />
C3112<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
1<br />
C3113<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
1<br />
C3114<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
1<br />
C3115<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
1<br />
C3116<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
1<br />
C3117<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
- =I2C_SODIMMA_SCL<br />
D<br />
- =I2C_SODIMMA_SDA<br />
BOM options provided by this page:<br />
(NONE)<br />
25D1 PP0V75_S3_MEM_VREFDQ_A<br />
D<br />
1<br />
C3130<br />
2.2UF<br />
20%<br />
6.3V<br />
2 CERM<br />
402-LF<br />
1<br />
C3131<br />
0.1UF<br />
20%<br />
10V<br />
2 CERM<br />
402<br />
C<br />
B<br />
A<br />
7C5 =PPSPD_S0_MEM_A<br />
1<br />
C3140<br />
2.2UF<br />
20%<br />
6.3V<br />
2<br />
CERM<br />
402-LF<br />
74D3 14A5<br />
74D3 14C5<br />
74D3 14C5<br />
74D3 14C5<br />
74D3 14C5<br />
74D3 14B5<br />
74D3 14B5<br />
74D3 14B5<br />
74D3 14B5<br />
74D3 14B5<br />
74D3 14C5<br />
74D3 14C5<br />
74D3 14C5<br />
74D3 14C5<br />
74D3 14C5<br />
74D3 14B5<br />
74D3 14C7<br />
74D3 14C7<br />
74C3 14D5<br />
74C3 14D5<br />
74D3 14C7<br />
74D3 14C7<br />
74D3 14C7<br />
74D3 14C7<br />
74C3 14B7<br />
74D3 14D7<br />
74D3 14D7<br />
74D3 14D7<br />
74D3 14D7<br />
74C3 14D5<br />
74C3 14D5<br />
74D3 14D7<br />
74D3 14D7<br />
74D3 14D7<br />
74D3 14D7<br />
74C3 14B7<br />
74D3 14D7<br />
74D3 14D7<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
BI<br />
BI<br />
1<br />
R3140<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
MEM_A_CKE<br />
MEM_A_BA<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_CLK_P<br />
MEM_A_CLK_N<br />
MEM_A_A<br />
MEM_A_BA<br />
MEM_A_WE_L<br />
MEM_A_CAS_L<br />
MEM_A_A<br />
MEM_A_CS_L<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DM<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DM<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_SA<br />
MEM_A_SA<br />
1<br />
R3141<br />
10K<br />
5%<br />
2<br />
1/16W<br />
MF-LF<br />
402<br />
73<br />
75<br />
77<br />
NC<br />
79<br />
81<br />
83<br />
85<br />
87<br />
89<br />
91<br />
93<br />
95<br />
97<br />
99<br />
101<br />
103<br />
105<br />
107<br />
109<br />
111<br />
113<br />
115<br />
117<br />
119<br />
121<br />
123<br />
125<br />
NC<br />
127<br />
129<br />
131<br />
133<br />
135<br />
137<br />
139<br />
141<br />
143<br />
145<br />
147<br />
149<br />
151<br />
153<br />
155<br />
157<br />
159<br />
161<br />
163<br />
165<br />
167<br />
169<br />
171<br />
173<br />
175<br />
177<br />
179<br />
181<br />
183<br />
185<br />
187<br />
189<br />
191<br />
193<br />
195<br />
197<br />
199<br />
201<br />
203<br />
CKE0<br />
VDD<br />
KEY<br />
CKE1<br />
VDD<br />
NC J3100 A15<br />
BA2 F-RT-THB A14<br />
VDD<br />
VDD<br />
A12/BC*<br />
A11<br />
A9<br />
A7<br />
VDD<br />
A8<br />
VDD<br />
A6<br />
A5<br />
VDD<br />
A4<br />
VDD<br />
A3<br />
A2<br />
A1<br />
VDD<br />
CK0<br />
A0<br />
VDD<br />
CK1<br />
CK0*<br />
VDD<br />
A10/AP<br />
BA0<br />
VDD<br />
CK1*<br />
VDD<br />
BA1<br />
RAS*<br />
VDD<br />
WE*<br />
CAS*<br />
S0*<br />
ODT0<br />
VDD<br />
A13<br />
S1*<br />
VDD<br />
ODT1<br />
NC<br />
VDD<br />
VDD<br />
TEST<br />
VREFCA<br />
VSS<br />
DQ32<br />
VSS<br />
DQ36<br />
DQ33<br />
DQ37<br />
VSS<br />
DQS4*<br />
DQS4<br />
VSS<br />
DQ34<br />
VSS<br />
DM4<br />
VSS<br />
DQ38<br />
DQ39<br />
DQ35<br />
VSS<br />
DQ40<br />
VSS<br />
DQ44<br />
DQ45<br />
DQ41<br />
VSS<br />
VSS<br />
DQS5*<br />
DM5<br />
VSS<br />
DQ42<br />
DQ43<br />
VSS<br />
DQS5<br />
VSS<br />
DQ46<br />
DQ47<br />
VSS<br />
DQ48<br />
DQ52<br />
DQ49<br />
VSS<br />
DQ53<br />
VSS<br />
DQS6*<br />
DQS6<br />
DM6<br />
VSS<br />
VSS<br />
DQ54<br />
DQ50<br />
DQ51<br />
DQ55<br />
VSS<br />
VSS<br />
DQ56<br />
DQ57<br />
DQ60<br />
DQ61<br />
VSS<br />
VSS<br />
DM7<br />
DQS7*<br />
DQS7<br />
VSS<br />
DQ58<br />
DQ59<br />
VSS<br />
DQ62<br />
DQ63<br />
VSS<br />
SA0<br />
VSS<br />
EVENT*<br />
VDDSPD<br />
SA1<br />
VTT<br />
SDA<br />
SCL<br />
VTT<br />
DDR3-SODIMM-DUAL-M97-3<br />
(SYMBOL 2 OF 2)<br />
74<br />
76<br />
78<br />
80<br />
82<br />
84<br />
86<br />
88<br />
90<br />
92<br />
94<br />
96<br />
98<br />
100<br />
102<br />
104<br />
106<br />
108<br />
110<br />
112<br />
114<br />
116<br />
118<br />
120<br />
122<br />
NC<br />
124<br />
126<br />
128<br />
130<br />
132<br />
134<br />
136<br />
138<br />
140<br />
142<br />
144<br />
146<br />
148<br />
150<br />
152<br />
154<br />
156<br />
158<br />
160<br />
162<br />
164<br />
166<br />
168<br />
170<br />
172<br />
174<br />
176<br />
178<br />
180<br />
182<br />
184<br />
186<br />
188<br />
190<br />
192<br />
194<br />
196<br />
198<br />
200<br />
202<br />
204<br />
MEM_A_CKE<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_A<br />
MEM_A_CLK_P<br />
MEM_A_CLK_N<br />
MEM_A_BA<br />
MEM_A_RAS_L<br />
MEM_A_CS_L<br />
MEM_A_ODT<br />
MEM_A_ODT<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DM<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DM<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_EVENT_L<br />
=I2C_SODIMMA_SDA<br />
=I2C_SODIMMA_SCL<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
BI<br />
BI<br />
IN<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
OUT<br />
BI<br />
IN<br />
14A5 74D3<br />
8D2<br />
14C5 74D3<br />
14C5 74D3<br />
14C5 74D3<br />
14B5 74D3<br />
14B5 74D3<br />
14B5 74D3<br />
14B5 74D3<br />
14B5 74D3<br />
14B5 74D3<br />
14C5 74D3<br />
14C5 74D3<br />
14B5 74D3<br />
14B5 74D3<br />
14B5 74D3<br />
14C7 74D3<br />
14C7 74D3<br />
14B7 74C3<br />
14C7 74D3<br />
14C7 74D3<br />
14C7 74D3<br />
14C7 74D3<br />
14D5 74C3<br />
14D5 74C3<br />
14C7 74D3<br />
14C7 74D3<br />
14D7 74D3<br />
14D7 74D3<br />
14B7 74C3<br />
14D7 74D3<br />
14D7 74D3<br />
14D7 74D3<br />
14D7 74D3<br />
14D5 74C3<br />
14D5 74C3<br />
14D7 74D3<br />
14D7 74D3<br />
20A4 20B3 27A5 40B8<br />
43D6<br />
43D6<br />
1<br />
C3150<br />
2<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
74D3 14B7<br />
74D3 14B7<br />
74D3 14A7<br />
74D3 14B7<br />
74D3 14B7<br />
74D3 14B7<br />
74D3 14B7<br />
74C3 14D5<br />
74C3 14D5<br />
74D3 14B7<br />
74D3 14B7<br />
74D3 14C7<br />
74D3 14C7<br />
74C3 14D5<br />
74C3 14D5<br />
74D3 14C7<br />
74D3 14C7<br />
74D3 14C7<br />
74D3 14C7<br />
74C3 14B7<br />
74D3 14C7<br />
74D3 14B7<br />
2<br />
BI<br />
BI<br />
IN<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
BI<br />
BI<br />
1<br />
C3135<br />
2<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
1<br />
C3151<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DM<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DM<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
1<br />
C3136<br />
0.1UF<br />
2<br />
20%<br />
10V<br />
CERM<br />
402<br />
=PP0V75_S0_MEM_VTT_A<br />
1<br />
3<br />
5<br />
7<br />
9<br />
11<br />
13<br />
15<br />
17<br />
19<br />
21<br />
23<br />
25<br />
27<br />
29<br />
31<br />
33<br />
35<br />
37<br />
39<br />
41<br />
43<br />
45<br />
47<br />
49<br />
51<br />
53<br />
55<br />
57<br />
59<br />
61<br />
63<br />
65<br />
67<br />
69<br />
71<br />
PP0V75_S3_MEM_VREFCA_A<br />
7C7<br />
VREFDQ<br />
VSS<br />
VSS<br />
DQ4<br />
DQ0<br />
DQ5<br />
CRITICAL<br />
DQ1<br />
VSS<br />
VSS<br />
DQS0*<br />
DM0 J3100 DQS0<br />
VSS<br />
DQ2<br />
F-RT-THB<br />
VSS<br />
DQ6<br />
DQ3<br />
DQ7<br />
VSS<br />
DQ8<br />
DQ9<br />
VSS<br />
DQ12<br />
DQ13<br />
VSS<br />
VSS<br />
DQS1*<br />
DM1<br />
DQS1<br />
RESET*<br />
VSS<br />
DQ10<br />
VSS<br />
DQ14<br />
DQ11<br />
DQ15<br />
VSS<br />
DQ16<br />
DQ17<br />
VSS<br />
DQ20<br />
DQ21<br />
VSS<br />
DQS2*<br />
VSS<br />
DM2<br />
DQS2<br />
VSS<br />
VSS<br />
DQ22<br />
DQ18<br />
DQ23<br />
DQ19<br />
VSS<br />
VSS<br />
DQ28<br />
DQ24<br />
DQ25<br />
VSS<br />
DQ29<br />
VSS<br />
DQS3*<br />
DM3<br />
VSS<br />
DQ26<br />
DQ27<br />
DQS3<br />
VSS<br />
DQ30<br />
DQ31<br />
VSS<br />
VSS<br />
DDR3-SODIMM-DUAL-M97-3<br />
(SYMBOL 1 OF 2)<br />
KEY<br />
516-0201<br />
25C1<br />
2<br />
4<br />
6<br />
8<br />
10<br />
12<br />
14<br />
16<br />
18<br />
20<br />
22<br />
24<br />
26<br />
28<br />
30<br />
32<br />
34<br />
36<br />
38<br />
40<br />
42<br />
44<br />
46<br />
48<br />
50<br />
52<br />
54<br />
56<br />
58<br />
60<br />
62<br />
64<br />
66<br />
68<br />
70<br />
72<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DM<br />
MEM_RESET_L<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DM<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
IN<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
14B7 74D3<br />
14B7 74D3<br />
14D5 74C3<br />
14D5 74C3<br />
14B7 74D3<br />
14B7 74D3<br />
14B7 74D3<br />
14B7 74D3<br />
14A7 74C3<br />
27C2 28C5<br />
14B7 74D3<br />
14B7 74D3<br />
14C7 74D3<br />
14C7 74D3<br />
14B7 74C3<br />
14C7 74D3<br />
14C7 74D3<br />
14B7 74D3<br />
14B7 74D3<br />
14D5 74C3<br />
14D5 74C3<br />
14B7 74D3<br />
14C7 74D3<br />
"Factory" (top) slot<br />
SYNC_MASTER=BEN<br />
DDR3 SO-DIMM Connector A<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
SYNC_DATE=06/30/2008<br />
C<br />
B<br />
A<br />
516-0201<br />
SPD ADDR=0xA0(WR)/0xA1(RD)<br />
APPLE INC.<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
26<br />
81<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
Page Notes<br />
Power aliases required by this page:<br />
7D3 =PP1V5_S3_MEM_B<br />
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)<br />
- =PP1V5_S0_MEM_B<br />
- =PP1V5_S3_MEM_B<br />
- =PP0V75_S0_MEM_VTT_B<br />
- =PPSPD_S0_MEM_B (2.5 - 3.3V)<br />
Signal aliases required by this page:<br />
1<br />
2<br />
C3200<br />
10UF<br />
20%<br />
6.3V<br />
X5R<br />
603<br />
1<br />
C3201<br />
10UF<br />
20%<br />
6.3V<br />
2<br />
X5R<br />
603<br />
1<br />
C3210<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
1<br />
C3211<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
1<br />
2<br />
C3212<br />
0.1UF<br />
20%<br />
6.3V<br />
X6S-CERM<br />
0204-1<br />
CRITICAL<br />
1<br />
C3213<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
C3214<br />
1<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
1<br />
C3215<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
1<br />
C3216<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
C3217<br />
1<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
- =I2C_SODIMMB_SCL<br />
D<br />
- =I2C_SODIMMB_SDA<br />
BOM options provided by this page:<br />
(NONE)<br />
25C1 PP0V75_S3_MEM_VREFDQ_B<br />
D<br />
1<br />
2<br />
C3230<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
1<br />
C3231<br />
0.1UF<br />
20%<br />
10V<br />
2 CERM<br />
402<br />
C<br />
B<br />
A<br />
7C5 =PPSPD_S0_MEM_B<br />
1<br />
R3240<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
2<br />
C3240<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
74B3 14A1 IN<br />
74B3 14C1 IN<br />
74B3 14C1 IN<br />
74B3 14C1 IN<br />
74B3 14C1 IN<br />
74B3 14B1 IN<br />
74B3 14B1 IN<br />
74B3 14B1 IN<br />
74C3 14B1 IN<br />
74C3 14B1 IN<br />
74B3 14C1 IN<br />
74B3 14C1 IN<br />
74B3 14C1 IN<br />
74B3 14C1 IN<br />
74B3 14C1 IN<br />
74B3 14B1 IN<br />
74B3 14C3 BI<br />
74B3 14C3 BI<br />
74A3 14D1 BI<br />
74A3 14D1 BI<br />
74B3 14C3 BI<br />
74B3 14C3 BI<br />
74B3 14C3 BI<br />
74B3 14C3 BI<br />
74B3 14B3 IN<br />
74B3 14D3 BI<br />
74B3 14D3 BI<br />
74B3 14D3 BI<br />
74B3 14D3 BI<br />
74A3 14D1 BI<br />
74A3 14D1 BI<br />
74B3 14D3 BI<br />
74B3 14D3 BI<br />
74B3 14D3 BI<br />
74B3 14D3 BI<br />
74B3 14B3 IN<br />
74B3 14D3 BI<br />
74B3 14D3 BI<br />
MEM_B_CKE<br />
MEM_B_BA<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_CLK_P<br />
MEM_B_CLK_N<br />
MEM_B_A<br />
MEM_B_BA<br />
MEM_B_WE_L<br />
MEM_B_CAS_L<br />
MEM_B_A<br />
MEM_B_CS_L<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DM<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DM<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
R3241<br />
10K<br />
1<br />
2<br />
MEM_B_SA<br />
MEM_B_SA<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
73<br />
75<br />
77<br />
79<br />
81<br />
83<br />
85<br />
87<br />
89<br />
91<br />
93<br />
95<br />
97<br />
99<br />
101<br />
103<br />
105<br />
107<br />
109<br />
111<br />
113<br />
115<br />
117<br />
119<br />
121<br />
123<br />
125<br />
127<br />
129<br />
131<br />
133<br />
135<br />
137<br />
139<br />
141<br />
143<br />
145<br />
153<br />
155<br />
169<br />
171<br />
173<br />
175<br />
177<br />
179<br />
181<br />
183<br />
185<br />
187<br />
189<br />
191<br />
193<br />
195<br />
197<br />
199<br />
201<br />
203<br />
KEY<br />
CKE0<br />
VDD<br />
NC<br />
BA2<br />
VDD<br />
A12/BC*<br />
A9<br />
VDD<br />
A8<br />
A5<br />
VDD<br />
A3<br />
A1<br />
VDD<br />
CK0<br />
CK0*<br />
VDD<br />
A10/AP<br />
BA0<br />
VDD<br />
WE*<br />
CAS*<br />
VDD<br />
A13<br />
S1*<br />
VDD<br />
TEST<br />
VSS<br />
DQ32<br />
DQ33<br />
VSS<br />
DQS4*<br />
DQS4<br />
VSS<br />
DQ34<br />
DQ35<br />
VSS<br />
DQ40<br />
DQ41<br />
VSS<br />
DM5<br />
VSS<br />
DQ42<br />
DQ43<br />
VSS<br />
DQ48<br />
DQ49<br />
VSS<br />
DQS6*<br />
DQS6<br />
VSS<br />
DQ50<br />
DQ51<br />
VSS<br />
DQ56<br />
DQ57<br />
VSS<br />
DM7<br />
VSS<br />
DQ58<br />
DQ59<br />
VSS<br />
SA0<br />
VDDSPD<br />
SA1<br />
VTT<br />
F-RT-BGA3<br />
DDR3-SODIMM<br />
(2 OF 2)<br />
CKE1<br />
VDD<br />
A15<br />
A14<br />
VDD<br />
A11<br />
A7<br />
VDD<br />
A6<br />
A4<br />
VDD<br />
A2<br />
A0<br />
VDD<br />
CK1<br />
CK1*<br />
VDD<br />
BA1<br />
RAS*<br />
VDD<br />
S0*<br />
ODT0<br />
VDD<br />
ODT1<br />
NC<br />
VDD<br />
VREFCA<br />
VSS<br />
DQ36<br />
DQ37<br />
VSS<br />
DM4<br />
VSS<br />
DQ38<br />
DQ39<br />
VSS<br />
DQ44<br />
DQ45<br />
VSS<br />
DQS5*<br />
DQS5<br />
VSS<br />
DQ46<br />
DQ47<br />
VSS<br />
DQ52<br />
DQ53<br />
VSS<br />
DM6<br />
VSS<br />
DQ54<br />
DQ55<br />
VSS<br />
DQ60<br />
DQ61<br />
VSS<br />
DQS7*<br />
DQS7<br />
VSS<br />
DQ62<br />
DQ63<br />
VSS<br />
EVENT*<br />
SDA<br />
SCL<br />
VTT<br />
76<br />
78<br />
80<br />
82<br />
84<br />
86<br />
88<br />
90<br />
92<br />
94<br />
96<br />
98<br />
100<br />
102<br />
104<br />
106<br />
108<br />
110<br />
112<br />
114<br />
116<br />
118<br />
120<br />
122<br />
126<br />
128<br />
132<br />
134<br />
136<br />
142<br />
144<br />
147 148<br />
149<br />
150<br />
151<br />
157<br />
159<br />
161<br />
163<br />
165<br />
167<br />
J3200<br />
74<br />
124<br />
130<br />
138<br />
140<br />
146<br />
152<br />
154<br />
156<br />
158<br />
160<br />
162<br />
164<br />
166<br />
168<br />
170<br />
172<br />
174<br />
176<br />
178<br />
180<br />
182<br />
184<br />
186<br />
188<br />
190<br />
192<br />
194<br />
196<br />
198<br />
200<br />
202<br />
204<br />
205<br />
MTG PINS<br />
MTG PIN MTG PIN<br />
206<br />
207<br />
MTG PIN MTG PIN<br />
208<br />
209<br />
MTG PIN MTG PIN<br />
210<br />
211<br />
MTG PIN MTG PIN<br />
212<br />
MEM_B_CKE<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_A<br />
MEM_B_CLK_P<br />
MEM_B_CLK_N<br />
MEM_B_BA<br />
MEM_B_RAS_L<br />
MEM_B_CS_L<br />
MEM_B_ODT<br />
MEM_B_ODT<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DM<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DM<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_EVENT_L<br />
=I2C_SODIMMB_SDA<br />
=I2C_SODIMMB_SCL<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
BI<br />
BI<br />
IN<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
OUT<br />
BI<br />
IN<br />
14A1 74B3<br />
8D2<br />
14C1 74B3<br />
14C1 74B3<br />
14C1 74B3<br />
14B1 74B3<br />
14B1 74B3<br />
14B1 74B3<br />
14B1 74B3<br />
14B1 74C3<br />
14B1 74C3<br />
14C1 74B3<br />
14C1 74B3<br />
14B1 74B3<br />
14B1 74B3<br />
14B1 74B3<br />
14C3 74B3<br />
14C3 74B3<br />
14B3 74B3<br />
14C3 74B3<br />
14C3 74B3<br />
14C3 74B3<br />
14C3 74B3<br />
14D1 74A3<br />
14D1 74A3<br />
14C3 74B3<br />
14C3 74B3<br />
14D3 74B3<br />
14D3 74B3<br />
14B3 74B3<br />
14D3 74B3<br />
14D3 74B3<br />
14D3 74B3<br />
14D3 74B3<br />
14D1 74A3<br />
14D1 74A3<br />
14D3 74B3<br />
14D3 74B3<br />
20A4 20B3 26A5 40B8<br />
43C6<br />
43C6<br />
1<br />
2<br />
C3250<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
74B3 14B3<br />
74B3 14B3<br />
74B3 14A3<br />
74B3 14B3<br />
74B3 14B3<br />
74B3 14B3<br />
74B3 14B3<br />
74A3 14D1<br />
74A3 14D1<br />
74B3 14B3<br />
74B3 14B3<br />
74B3 14C3<br />
74B3 14B3<br />
74A3 14D1<br />
74A3 14D1<br />
74B3 14C3<br />
74B3 14B3<br />
74B3 14C3<br />
74B3 14C3<br />
74B3 14B3<br />
74B3 14C3<br />
74B3 14C3<br />
1<br />
2<br />
1<br />
2<br />
BI<br />
BI<br />
IN<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
BI<br />
BI<br />
C3235<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
C3251<br />
2.2UF<br />
20%<br />
6.3V<br />
CERM<br />
402-LF<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DM<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DM<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
1<br />
2<br />
C3236<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
=PP0V75_S0_MEM_VTT_B<br />
1<br />
3<br />
5<br />
7<br />
9<br />
11<br />
13<br />
15<br />
17<br />
19<br />
21<br />
23<br />
25<br />
27<br />
29<br />
31<br />
33<br />
35<br />
37<br />
39<br />
41<br />
43<br />
45<br />
47<br />
49<br />
51<br />
53<br />
55<br />
57<br />
59<br />
61<br />
63<br />
65<br />
67<br />
69<br />
71<br />
PP0V75_S3_MEM_VREFCA_B<br />
7C7<br />
VREFDQ<br />
VSS<br />
VSS<br />
DQ4<br />
DQ0<br />
DQ5<br />
CRITICAL<br />
DQ1<br />
VSS<br />
VSS<br />
DQS0*<br />
DM0 J3200 DQS0<br />
VSS<br />
F-RT-BGA3<br />
VSS<br />
DQ2<br />
DQ3<br />
VSS<br />
DQ6<br />
DQ7<br />
VSS<br />
DQ8<br />
DQ9<br />
VSS<br />
DQ12<br />
DQ13<br />
VSS<br />
DQS1*<br />
DM1<br />
DQS1<br />
VSS<br />
RESET*<br />
VSS<br />
DQ10<br />
DQ11<br />
VSS<br />
DQ14<br />
DQ15<br />
VSS<br />
DQ16<br />
DQ17<br />
VSS<br />
DQ20<br />
DQ21<br />
VSS<br />
DQS2*<br />
DQS2<br />
VSS<br />
DQ18<br />
DQ19<br />
VSS<br />
DQ24<br />
DQ25<br />
DM2<br />
VSS<br />
DQ22<br />
DQ23<br />
VSS<br />
DQ28<br />
DQ29<br />
VSS<br />
VSS<br />
DM3<br />
VSS<br />
DQS3*<br />
DQS3<br />
VSS<br />
DQ26<br />
DQ27<br />
DQ30<br />
DQ31<br />
VSS<br />
VSS<br />
DDR3-SODIMM<br />
(1 OF 2)<br />
KEY<br />
516S0706<br />
25C1<br />
2<br />
4<br />
6<br />
8<br />
10<br />
12<br />
14<br />
16<br />
18<br />
20<br />
22<br />
24<br />
26<br />
28<br />
30<br />
32<br />
34<br />
36<br />
38<br />
40<br />
42<br />
44<br />
46<br />
48<br />
50<br />
52<br />
54<br />
56<br />
58<br />
60<br />
62<br />
64<br />
66<br />
68<br />
70<br />
72<br />
7B6 =PP1V5_S0_MEM_MCP<br />
C3222<br />
1<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DM<br />
MEM_RESET_L<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DM<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
IN<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
DDR3 GROUND RETURN CAPS (MCP SIDE)<br />
C3223<br />
1<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
1<br />
14B3 74B3<br />
14B3 74B3<br />
14D1 74A3<br />
14D1 74A3<br />
14B3 74B3<br />
14B3 74B3<br />
14B3 74B3<br />
14B3 74B3<br />
14A3 74B3<br />
26C2 28C5<br />
14B3 74B3<br />
14B3 74B3<br />
14B3 74B3<br />
14C3 74B3<br />
14B3 74B3<br />
14B3 74B3<br />
14C3 74B3<br />
14C3 74B3<br />
14C3 74B3<br />
14D1 74A3<br />
14D1 74A3<br />
14C3 74B3<br />
14C3 74B3<br />
C3224<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
1<br />
C3225<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
C3226<br />
1<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
SYNC_MASTER=BEN<br />
1<br />
C3227<br />
0.1UF<br />
20%<br />
2 6.3V<br />
X6S-CERM<br />
0204-1<br />
CRITICAL<br />
C3228<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
"Expansion" (bottom) slot<br />
DDR3 SO-DIMM Connector B<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
1<br />
1<br />
C3229<br />
0.1UF<br />
20%<br />
6.3V<br />
2 X6S-CERM<br />
0204-1<br />
CRITICAL<br />
SYNC_DATE=05/09/2008<br />
C<br />
B<br />
A<br />
II NOT TO REPRODUCE OR COPY IT<br />
516S0706<br />
SPD ADDR=0xA2(WR)/0xA3(RD)<br />
APPLE INC.<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
27 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
D<br />
7D3<br />
DDR3 RESET Support<br />
Required becaues MCP79 does not meet DDR3 spec power-up reset timing requirement.<br />
15C3<br />
IN<br />
=PP1V5_S3_MEMRESET<br />
MCP_MEM_RESET_L<br />
R3309<br />
0<br />
2 1<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
MEM_RESET_L<br />
OUT<br />
26C2 27C2<br />
C<br />
R3300<br />
10K<br />
1<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R3310 1<br />
1K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
MEM_RESET_RC_L<br />
6<br />
5<br />
D<br />
B<br />
Q3305<br />
DMB53D0UDW<br />
SOT-363<br />
Q1<br />
S<br />
G<br />
2 1<br />
R3305 1<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
MEM_RESET<br />
=PP3V3_S5_MEMRESET<br />
3.3V S5 is used because MEM_RESET<br />
must be high before 1.5V starts to<br />
rise to avoid glitch on MEM_RESET_L.<br />
7A3<br />
C<br />
R33011 20K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
C3300<br />
0.1UF<br />
20%<br />
2<br />
10V<br />
CERM<br />
402<br />
4<br />
E<br />
Q2<br />
C<br />
3<br />
B<br />
B<br />
A<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
DDR3 Support<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=04/04/2008<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
28<br />
81<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
16C6 OUT PCIE_MINI_PRSNT_L<br />
3 D Q3401<br />
SSM6N15FEAPE<br />
SOT563<br />
4<br />
S<br />
G<br />
5<br />
D<br />
16C6<br />
OUT<br />
MINI_CLKREQ_L<br />
6 D Q3401<br />
SSM6N15FEAPE<br />
SOT563<br />
AP_PWR_EN<br />
IN<br />
20A3 20C3 32C7<br />
5V S3 WLAN FET<br />
MOSFET<br />
TPCP8102<br />
CHANNEL<br />
P-TYPE<br />
RDS(ON)<br />
26 mOhm @4.5V<br />
LOADING<br />
0.8 A (EDP)<br />
D<br />
1<br />
S<br />
G<br />
2<br />
C<br />
CRITICAL<br />
518S0610<br />
J3401<br />
20347-325E-12<br />
F-RT-SM<br />
31<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10<br />
11<br />
12<br />
13<br />
75D3 6D5<br />
75D3 6D5<br />
75D3 6D5<br />
75D3 6D5<br />
PCIE_CLK100M_MINI_CONN_P<br />
PCIE_CLK100M_MINI_CONN_N<br />
6C5<br />
PCIE_MINI_D2R_P<br />
PCIE_MINI_D2R_N<br />
PCIE_MINI_R2D_P<br />
PCIE_MINI_R2D_N<br />
MINI_CLKREQ_Q_L<br />
PCIE_WAKE_L<br />
OUT<br />
OUT<br />
OUT<br />
6D5 16B6 75D3<br />
6D5 16B6 75D3<br />
6D5 16B6<br />
1 2 0.1uF<br />
10% 16V X5R 402<br />
C3430<br />
PLACEMENT_NOTE=Place close to J3401.<br />
C3431<br />
1 2 0.1uF<br />
10%<br />
16V<br />
PLACEMENT_NOTE=Place close to J3401.<br />
90-OHM-100MA<br />
DLP11S<br />
SYM_VER-1<br />
4 3<br />
1<br />
CRITICAL<br />
L3401<br />
2<br />
X5R<br />
402<br />
PLACEMENT_NOTE=Place close to J3401.<br />
PCIE_MINI_R2D_C_P<br />
PCIE_MINI_R2D_C_N<br />
AIRPORT<br />
PCIE_CLK100M_MINI_P<br />
PCIE_CLK100M_MINI_N<br />
IN<br />
IN<br />
1000 mA peak<br />
750 mA nominal max<br />
16B3 75D3<br />
16B3 75D3<br />
IN<br />
IN<br />
16C3<br />
75D3<br />
16C3<br />
75D3<br />
6C3<br />
6D5<br />
PP5V_WLAN<br />
MIN_LINE_WIDTH=1 mm<br />
MIN_NECK_WIDTH=0.5 mm<br />
VOLTAGE=5V<br />
C3422<br />
1<br />
0.1uF<br />
20%<br />
10V<br />
CERM<br />
2<br />
402<br />
L3404<br />
FERR-120-OHM-1.5A<br />
0402-LF<br />
2 1<br />
C3421<br />
0.1uF<br />
20%<br />
10V<br />
CERM<br />
402<br />
PLACEMENT_NOTE=Place close to J3401.<br />
1<br />
2<br />
1<br />
C3420<br />
2<br />
10UF<br />
20%<br />
10V<br />
X5R<br />
805<br />
29A5<br />
PLACEMENT_NOTE=Place close to Q3450.<br />
PP5V_WLAN_F<br />
MIN_LINE_WIDTH=1 mm<br />
MIN_NECK_WIDTH=0.5 mm<br />
VOLTAGE=5V<br />
PLACEMENT_NOTE=Place close to Q3450.<br />
5 6 7 8<br />
D<br />
C3450<br />
0.1UF<br />
1 2<br />
10%<br />
16V<br />
X5R<br />
402<br />
CRITICAL<br />
Q3450<br />
TPCP8102<br />
23V1K-SM<br />
G<br />
4<br />
S<br />
1 2 3<br />
C3451<br />
0.033UF<br />
10%<br />
16V<br />
X5R<br />
402<br />
P5VWLAN_SS<br />
1<br />
2<br />
1 R3451<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
R3450 2<br />
100K 1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
=PP5V_S3_WLAN<br />
MIN_LINE_WIDTH=1 mm<br />
MIN_NECK_WIDTH=0.5 mm<br />
VOLTAGE=5V<br />
PM_WLAN_EN_L<br />
IN<br />
7C3<br />
29A4 32C6<br />
C<br />
14<br />
B<br />
15<br />
16<br />
17<br />
18<br />
19<br />
20<br />
21<br />
22<br />
23<br />
24<br />
25<br />
26<br />
27<br />
28<br />
29<br />
30<br />
32<br />
NC<br />
NC<br />
76C3 6D5<br />
76C3 6D5<br />
6D5<br />
USB_CAMERA_CONN_P<br />
USB_CAMERA_CONN_N<br />
CONN_USB2_BT_P<br />
CONN_USB2_BT_N<br />
PP5V_S3_BTCAMERA_F<br />
=I2C_ALS_SDA<br />
=I2C_ALS_SCL<br />
BI<br />
IN<br />
43C1<br />
43C1<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.25 mm<br />
VOLTAGE=5V<br />
4<br />
CRITICAL<br />
L3402<br />
90-OHM<br />
DLP0NS<br />
SYM_VER-1<br />
1 2<br />
4<br />
90-OHM<br />
DLP0NS<br />
SYM_VER-1<br />
3<br />
PLACEMENT_NOTE=Place close to J3401.<br />
CRITICAL<br />
L3403<br />
3<br />
ALS<br />
CAMERA<br />
USB_CAMERA_P<br />
USB_CAMERA_N<br />
OUT<br />
OUT<br />
BLUETOOTH<br />
USB_BT_P<br />
275 mA peak<br />
206 mA nominal max<br />
BI<br />
C3452<br />
1<br />
0.1uF 20%<br />
10V<br />
CERM 2<br />
402<br />
19D3 76C3<br />
19D3 76C3<br />
19D3 76C3<br />
L3405<br />
2 1<br />
FERR-120-OHM-1.5A<br />
0402-LF<br />
=PP5V_S3_BTCAMERA<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.25 mm<br />
VOLTAGE=5V<br />
7C3<br />
B<br />
1 2<br />
PLACEMENT_NOTE=Place close to J3401.<br />
USB_BT_N<br />
BI<br />
19C3 76C3<br />
PP5V_WLAN_F<br />
29C3<br />
=PP3V3_S3_WLAN<br />
7D3<br />
1<br />
R3453<br />
33K<br />
5%<br />
A<br />
6C5<br />
TC7SZ08AFEAPE 5<br />
SOT665<br />
MINI_RESET_CONN_L<br />
4<br />
Y<br />
U3401<br />
3<br />
A<br />
B<br />
2<br />
1<br />
U3402<br />
74LVC1G17DRL 5<br />
SOT-553<br />
WLAN_SMIT_BUF<br />
4<br />
2<br />
NC<br />
3 1<br />
NC<br />
C3453<br />
MINI_RESET_L<br />
1UF<br />
IN 24C1<br />
10%<br />
6.3V<br />
CERM<br />
402<br />
1<br />
2<br />
2<br />
1/16W<br />
MF-LF<br />
402<br />
R3454<br />
62K<br />
1<br />
WLAN_SMIT_RC<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R3455<br />
1<br />
1<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
WLAN_SMIT_DISCHRG<br />
Q3455<br />
3 D SSM3K15FV<br />
SOD-VESM-HF<br />
2 S G 1<br />
PM_WLAN_EN_L<br />
29C1 32C6<br />
SYNC_MASTER=YITE<br />
Right Clutch Connector<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
SYNC_DATE=04/22/2008<br />
A<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
29<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
C<br />
B<br />
7C3<br />
76B3 19C3 BI<br />
76B3 19C3<br />
=PP3V3_S3_CARDREADER<br />
MIN_LINE_WIDTH=0.40MM<br />
MIN_NECK_WIDTH=0.20MM<br />
VOLTAGE=3.3V<br />
BI<br />
USB_CARDREADER_N<br />
USB_CARDREADER_P<br />
C3511<br />
33PF<br />
1 2<br />
5%<br />
50V<br />
CERM<br />
402<br />
NO STUFF<br />
R3503<br />
1M<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
CRITICAL<br />
Y3500<br />
12.000M-100PPM<br />
1 2<br />
8X4.5X1.4-SM<br />
C3512<br />
33PF<br />
1 2<br />
5%<br />
50V<br />
CERM<br />
402<br />
R3511<br />
0<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
C3500<br />
10UF<br />
CARDREADER_XTAL1<br />
CARDREADER_XTAL2<br />
1<br />
C3501<br />
0.1UF<br />
20%<br />
20%<br />
6.3V<br />
2 X5R<br />
10V<br />
2 CERM<br />
603<br />
402<br />
R3506<br />
715<br />
1<br />
1%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
30B4 30A7 PP3V3_S3_CARDREADER_DVDD<br />
PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN<br />
PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
1<br />
C3502<br />
0.1UF<br />
20%<br />
10V<br />
2 CERM<br />
402<br />
PP3V3_S3_CARDREADER_AVDD<br />
MIN_LINE_WIDTH=0.40MM<br />
MIN_NECK_WIDTH=0.20MM<br />
VOLTAGE=3.3V<br />
1<br />
C3514<br />
1<br />
C3504<br />
1<br />
C3508<br />
10UF 0.1UF 0.1UF<br />
20%<br />
20%<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
603<br />
2<br />
10V<br />
CERM<br />
402<br />
2<br />
10V<br />
CERM<br />
402<br />
1<br />
C3506<br />
0.1UF<br />
20%<br />
2<br />
10V<br />
CERM<br />
402<br />
CARDREADER_RREF<br />
1<br />
R3502<br />
1<br />
C3503<br />
0.1UF<br />
20%<br />
10V<br />
2 CERM<br />
402<br />
L3500<br />
0.22UH<br />
1 2<br />
0805-1<br />
PP1V8_S3_CARDREADER<br />
MIN_LINE_WIDTH=0.30MM<br />
MIN_NECK_WIDTH=0.20MM<br />
VOLTAGE=1.8V<br />
7<br />
DM<br />
8<br />
DP<br />
VDD18O<br />
10 RREF<br />
AVDD<br />
CARDREADER_RESET_L 18<br />
EXTRSTZ* /IPU<br />
NO STUFF<br />
1<br />
C3513<br />
0.1UF<br />
2<br />
20%<br />
10V<br />
CERM<br />
402<br />
MIN_LINE_WIDTH=0.40MM<br />
MIN_NECK_WIDTH=0.20MM<br />
VOLTAGE=3.3V<br />
48<br />
30A7 CARDREADER_GPIO1 GPIO1<br />
47<br />
30A6 CARDREADER_GPIO2 GPIO2<br />
46<br />
NC GPIO3<br />
19<br />
NC SK<br />
20<br />
NC CS<br />
21<br />
NC DO<br />
22<br />
NC DI /IPD<br />
13 X1<br />
14 X2<br />
CARDREADER_TEST_MOD<br />
4<br />
6<br />
DVDD<br />
IPD/<br />
IPD/<br />
17 TESTMOD /IPD<br />
5<br />
11<br />
VDD5V<br />
U3500<br />
GL137A<br />
9<br />
15<br />
26<br />
35<br />
CRITICAL<br />
PMOSO<br />
XD_CDZ<br />
XD_CE<br />
XD_WEZ<br />
XD_RBZ<br />
XD_WPZ<br />
D0<br />
40<br />
D1<br />
43<br />
D2 37<br />
D3<br />
29<br />
D4 28<br />
D5<br />
30<br />
D6<br />
32<br />
D7<br />
38<br />
SD_WP<br />
SD_CMD<br />
IPU/ PDMOD 2<br />
IPU/ SD_CDZ<br />
23<br />
IPU/ MS_INS<br />
24<br />
IPD/ MS_BS<br />
33<br />
12<br />
LQFP<br />
GND<br />
16<br />
IPU/<br />
IPD/<br />
IPD/<br />
IPD/<br />
27<br />
25<br />
34<br />
36<br />
CLK<br />
39<br />
3<br />
41<br />
1<br />
31<br />
42<br />
44<br />
45<br />
CARDREADER_PDMOD<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
1<br />
C3507<br />
2.2UF<br />
20%<br />
6.3V<br />
2 CERM1<br />
603<br />
1<br />
C3505<br />
0.1UF<br />
20%<br />
10V<br />
2 CERM<br />
402<br />
PART NUMBER<br />
PLACEMENT_NOTE=KEEP THIS NET AS SHORT AS POSSIBLE<br />
30D6 30A7<br />
1<br />
516-0225<br />
R3505<br />
39K<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
QTY<br />
DESCRIPTION REFERENCE DES CRITICAL BOM OPTION<br />
MAX CURRENT = 250MA<br />
PP3V3_SW_SD_PWR<br />
MIN_LINE_WIDTH=0.30MM<br />
MIN_NECK_WIDTH=0.20MM<br />
VOLTAGE=3.3V<br />
PDMOD: POWER DOWN MODES<br />
NC = DISABLE (DEFAULT)<br />
10K LOW = POWER SAVING MODE ENABLE<br />
10K HIGH = REMOTE WAKE UP ENABLE<br />
PP3V3_S3_CARDREADER_DVDD<br />
1<br />
CONN,SD CARD READER,OPTN B,HF,K19/<strong>K24</strong><br />
78C3 SD_CLK<br />
78C3 SD_CMD<br />
78D3 SD_D<br />
78D3 SD_D<br />
78C3 SD_D<br />
78C3 SD_D<br />
78C3 SD_D<br />
78C3 SD_D<br />
78C3 SD_D<br />
78C3 SD_D<br />
SD_CD_L<br />
SD_WP<br />
J3500<br />
OMIT<br />
J3500<br />
SD-CARD-K19<br />
F-RT-TH<br />
3<br />
6<br />
5<br />
2<br />
7<br />
8<br />
9<br />
1<br />
10<br />
11<br />
12<br />
13<br />
14<br />
15<br />
16<br />
4<br />
17<br />
18<br />
19<br />
20<br />
VSS<br />
VSS<br />
CLK<br />
CMD<br />
DAT0<br />
DAT1<br />
DAT2<br />
CD/DAT3<br />
DAT4<br />
DAT5<br />
DAT6<br />
DAT7<br />
CARD_DETECT_SW<br />
CARD_DETECT_GND<br />
WRITE_PROTECT_SW<br />
VDD<br />
SHLD_PIN<br />
SHLD_PIN<br />
SHLD_PIN<br />
SHLD_PIN<br />
CRITICAL<br />
D<br />
C<br />
B<br />
16B6<br />
24C1<br />
IN<br />
IN<br />
CARDREADER_RESET<br />
CARDREADER_PLT_RST_L<br />
Q3500<br />
SSM6N15FEAPE<br />
SOT563<br />
5 G<br />
D 3<br />
S 4<br />
Q3500<br />
D 6<br />
SSM6N15FEAPE<br />
SOT563<br />
2 G<br />
S 1<br />
CARDREADER_PLT_RST<br />
(PDMOD)<br />
1<br />
R3512<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
1 NO STUFF<br />
R3513<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
30D6 30B4 PP3V3_S3_CARDREADER_DVDD<br />
A<br />
30C6<br />
CARDREADER_GPIO1<br />
1<br />
R3507<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
1 NO STUFF<br />
R3508<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
CARDREADER_GPIO2<br />
30C6<br />
SECUREDIGITAL CARD READER<br />
SYNC_MASTER=VEMURI<br />
NOTICE OF PROPRIETARY PROPERTY<br />
SYNC_DATE=01/30/2009<br />
A<br />
1NO STUFF<br />
R3509<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
1<br />
R3510<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
30<br />
81<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
7B5 =PP3V3_ENET_PHY<br />
(43mA typ - 1000base-T)<br />
(19mA typ - Energy Detect)<br />
WF: Marvell numbers, update for Realtek<br />
1<br />
2<br />
CRITICAL<br />
L3705<br />
FERR-120-OHM-1.5A<br />
0402-LF<br />
PP3V3_ENET_PHYAVDD<br />
MIN_LINE_WIDTH=0.6 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=3.3V<br />
1<br />
C3700<br />
0.1UF<br />
2<br />
1<br />
C3705<br />
0.1UF<br />
2<br />
10%<br />
16V<br />
X5R<br />
402<br />
10%<br />
16V<br />
X5R<br />
402<br />
1<br />
C3701<br />
0.1UF<br />
2<br />
1<br />
C3706<br />
0.1UF<br />
2<br />
10%<br />
16V<br />
X5R<br />
402<br />
10%<br />
16V<br />
X5R<br />
402<br />
1<br />
C3702<br />
0.1UF<br />
2<br />
10%<br />
16V<br />
X5R<br />
402<br />
C3714<br />
0.1UF<br />
10%<br />
16V<br />
X5R<br />
402<br />
1<br />
2<br />
C3710<br />
0.1UF<br />
10%<br />
16V<br />
X5R<br />
402<br />
1<br />
2<br />
C3715 1<br />
2.2UF<br />
20%<br />
2<br />
6.3V<br />
CERM<br />
402-LF<br />
C3711<br />
0.1UF<br />
10%<br />
16V<br />
X5R<br />
402<br />
1<br />
2<br />
C3716 1<br />
2.2UF<br />
20%<br />
6.3V<br />
2<br />
CERM<br />
402-LF<br />
CRITICAL<br />
L3715<br />
FERR-120-OHM-1.5A<br />
0402-LF<br />
PP1V05_ENET_PHYAVDD<br />
MIN_LINE_WIDTH=0.6 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=1.05V<br />
1<br />
2<br />
=PP1V05_ENET_PHY<br />
(221mA typ - 1000base-T)<br />
( 7mA typ - Energy Detect)<br />
WF: Marvell numbers, update for Realtek<br />
7A5<br />
=PP3V3_ENET_PHY_VDDREG<br />
If internal switcher is used, must place 1x 22uF &<br />
1x 0.1uF caps within 5mm of U3700 pins 44 & 45.<br />
8D2<br />
D<br />
C<br />
77D3 17D3<br />
IN<br />
ENET_CLK125M_TXCLK<br />
R3796<br />
0<br />
1<br />
5%<br />
1/16W<br />
402<br />
MF-LF<br />
PLACE R3796 CLOSE TO U1400, PIN D24<br />
2<br />
Alias to =PP3V3_ENET_PHY for internal switcher.<br />
Alias to GND for external 1.05V supply.<br />
8D2<br />
77D3 17D3<br />
77D3 17D3<br />
77D3 17D3<br />
77D3 17D3<br />
IN<br />
77D3 ENET_CLK125M_TXCLK_R<br />
IN<br />
IN<br />
IN<br />
IN<br />
=RTL8211_ENSWREG<br />
ENET_TXD<br />
ENET_TXD<br />
ENET_TXD<br />
ENET_TXD<br />
R3720<br />
1<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
NO STUFF<br />
1<br />
R3725<br />
4.7K<br />
5%<br />
2<br />
1/16W<br />
MF-LF<br />
402<br />
39<br />
22<br />
23<br />
24<br />
25<br />
26<br />
6<br />
ENSWREG<br />
TXC<br />
41<br />
AVDD33<br />
TXD[0]<br />
TXD[1]<br />
TXD[2]<br />
TXD[3]<br />
15<br />
21<br />
37<br />
DVDD33<br />
44<br />
45<br />
VDDREG<br />
3<br />
RGMII/MII<br />
FB10<br />
CRITICAL<br />
U3700<br />
RTL8251CA-VB-GR<br />
TQFP<br />
28<br />
36<br />
DVDD10<br />
10<br />
40<br />
AVDD10<br />
REGOUT<br />
RXC<br />
RXD[0]<br />
RXD[1]/TXDLY<br />
RXD[2]/AN0<br />
RXD[3]/AN1<br />
R3750<br />
4.7K<br />
5%<br />
48<br />
19<br />
14<br />
16<br />
17<br />
18<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
2<br />
1<br />
R3751<br />
4.7K<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
77D3<br />
77D3<br />
77D3<br />
77D3<br />
77D3 ENET_CLK125M_RXCLK_R<br />
ENET_RXD_R<br />
ENET_RXD_R<br />
ENET_RXD_R<br />
ENET_RXD_R<br />
R3752<br />
1<br />
4.7K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.<br />
=RTL8211_REGOUT<br />
If internal switcher is used, must place inductor within 5mm<br />
of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.<br />
If internal switcher is not used, VDDREG and REGOUT can float.<br />
R3790<br />
22<br />
R3791 22<br />
R3792 22<br />
R3793 22<br />
R3794 22<br />
1<br />
1<br />
1<br />
1<br />
1<br />
2<br />
2<br />
2<br />
2<br />
2<br />
8D2<br />
5% 1/16W MF-LF<br />
402<br />
5% 1/16W MF-LF 402<br />
5% 1/16W MF-LF 402<br />
5% 1/16W MF-LF<br />
5% 1/16W MF-LF<br />
402<br />
402<br />
ENET_CLK125M_RXCLK<br />
ENET_RXD<br />
ENET_RXD<br />
ENET_RXD<br />
ENET_RXD<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
17D6 77D3<br />
17D6 77D3<br />
17D6 77D3<br />
17D6 77D3<br />
17D6 77D3<br />
C<br />
77C3 17D3<br />
IN<br />
ENET_TX_CTRL<br />
27<br />
TXCTL<br />
RXCTL<br />
13<br />
77D3<br />
ENET_RXCTL_R<br />
R3795<br />
22<br />
1<br />
2<br />
5% 1/16W MF-LF<br />
402<br />
ENET_RX_CTRL<br />
OUT<br />
17D6 77D3<br />
B<br />
77C3 17C3<br />
ENET_RESET_L IS NOT ASSERTED WHEN WOL IS ACTIVE.<br />
HENCE, RC (C3725 AND R3725) ARE NOT STUFFED.<br />
IN<br />
ENET_RESET_L<br />
R3724<br />
0<br />
1<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
2<br />
NO STUFF<br />
1<br />
C3725<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
R3730<br />
2.49K<br />
1/16W<br />
1%<br />
MF-LF<br />
402<br />
1<br />
2<br />
77D3 17D3<br />
77D3 17C3<br />
77D3 32A3<br />
IN<br />
BI<br />
IN<br />
8D2<br />
ENET_MDC<br />
ENET_MDIO<br />
RTL8211_PHYRST_L<br />
RTL8211_RSET<br />
TP_RTL8211_CLK125<br />
RTL8211_CLK25M_CKXTAL1<br />
TP_RTL8211_CKXTAL2<br />
30<br />
MDC<br />
31<br />
MDIO<br />
29<br />
46<br />
32<br />
42<br />
43<br />
PHYRSTB*<br />
RSET<br />
CLK125<br />
CKXTAL1<br />
CKXTAL2<br />
MANAGEMENT<br />
RESET MEDIA DEPENDENT<br />
REFERENCE<br />
CLOCK<br />
LED<br />
7<br />
GND<br />
20<br />
33<br />
47<br />
MDI+[0]<br />
1<br />
MDI-[0]<br />
2<br />
MDI+[1]<br />
MDI-[1]<br />
MDI+[2]<br />
MDI-[2]<br />
LED0/PHYAD0<br />
LED1/PHYAD1<br />
LED2/RXDLY<br />
4<br />
5<br />
8<br />
9<br />
MDI+[3]<br />
11<br />
MDI-[3]<br />
12<br />
34<br />
35<br />
38<br />
NO STUFF<br />
1<br />
C3790<br />
10PF<br />
5%<br />
50V<br />
CERM<br />
2<br />
402<br />
ENET_MDI_P<br />
ENET_MDI_N<br />
ENET_MDI_P<br />
ENET_MDI_N<br />
ENET_MDI_P<br />
ENET_MDI_N<br />
ENET_MDI_P<br />
ENET_MDI_N<br />
RTL8211_PHYAD0<br />
RTL8211_PHYAD1<br />
RTL8211_RXDLY<br />
R3755<br />
4.7K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
2<br />
BI 33B8 77C3<br />
BI 33B8 77C3<br />
BI 33C8 77C3<br />
BI 33C8 77C3<br />
BI 33C8 77C3<br />
BI 33C8 77C3<br />
BI 33C8 77C3<br />
BI 33C8 77C3<br />
R3756<br />
1<br />
4.7K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
R3757<br />
4.7K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
B<br />
Reserved for EMI<br />
per RealTek request.<br />
A<br />
Configuration Settings:<br />
PHYAD = 01 (PHY Address 00001)<br />
AN[1:0] = 11 (Full auto-negotiation)<br />
RXDLY = 0 (RXCLK transitions with data)<br />
TXDLY = 0 (No TXCLK Delay)<br />
8 7 6 5 4 3 2 1<br />
SYNC_MASTER=SUMA<br />
APPLE INC.<br />
Ethernet PHY (RTL8211CL)<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
31<br />
SYNC_DATE=05/23/2008<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
A
8 7 6 5 4 3 2 1<br />
3.3V ENET FET<br />
@ 2.5V Vgs:<br />
Rds(on) = 90mOhm max<br />
I(max) = 1.7A (85C)<br />
CRITICAL<br />
Q3810<br />
NTR4101P<br />
SOT-23-HF<br />
D<br />
7A3<br />
=PP3V3_S5_P3V3ENETFET<br />
R3800 1<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
P3V3ENET_EN_L<br />
R3810<br />
100K<br />
1 2<br />
1<br />
C3811<br />
0.033UF<br />
2 16V<br />
10%<br />
X5R<br />
402<br />
P3V3ENET_SS<br />
2<br />
S<br />
1<br />
G<br />
D<br />
3<br />
C3810<br />
0.01UF<br />
2<br />
1<br />
=PP3V3_ENET_FET<br />
7B6<br />
D<br />
Q3801<br />
SSM6N15FEAPE<br />
SOT563<br />
D<br />
3<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
10%<br />
16V<br />
CERM<br />
402<br />
5<br />
G<br />
S<br />
4<br />
8D2<br />
IN<br />
=P3V3ENET_EN<br />
MOBILE:<br />
WLAN Enable Generation<br />
"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))<br />
Recommend aliasing PM_SLP_RMGT_L and<br />
=P3V3ENET_EN. Nets separated on<br />
ARB for alternate power options.<br />
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.<br />
C<br />
PM_WLAN_EN_L OUT 29A4 29C1<br />
Pull-up is with power FET.<br />
Q3805 D 6<br />
SSM6N15FEAPE<br />
SOT563<br />
7B3<br />
1.05V ENET FET<br />
=PP1V05_ENET_P1V05ENETFET<br />
C<br />
2 G<br />
S 1<br />
1.8V Vgs<br />
29D5 20C3 20A3<br />
IN<br />
AP_PWR_EN<br />
AC_OR_S0_L<br />
Q3805 D 3<br />
SSM6N15FEAPE<br />
SOT563<br />
6 D<br />
Q3801<br />
SSM6N15FEAPE<br />
SOT563<br />
7A3<br />
=PP3V3_S5_P1V05ENETFET<br />
R3840<br />
100K 2<br />
1<br />
5%<br />
1/16W<br />
P1V05ENET_SS<br />
C3840 1<br />
0.1UF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
1<br />
G<br />
3<br />
D<br />
S<br />
CRITICAL<br />
Q3840<br />
SI2312BDS<br />
SOT23<br />
41B2 40D5 35B5 20C7<br />
70D8 66D5 40C5 35A5 20C3 6C3<br />
IN<br />
IN<br />
SMC_ADAPTER_EN<br />
PM_SLP_S3_L<br />
5 G<br />
S 4<br />
S 1<br />
G<br />
2<br />
R3842 1<br />
69.8K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
Q3841 D 3<br />
SSM6N15FEAPE<br />
SOT563<br />
P1V05ENET_EN_L<br />
MF-LF<br />
402<br />
R3841<br />
10K<br />
1 2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
Q3841 D 6<br />
SSM6N15FEAPE<br />
SOT563<br />
2<br />
G<br />
S<br />
P1V05ENET_EN_L_RC<br />
1<br />
2<br />
1<br />
2<br />
=PP1V05_ENET_FET<br />
C3841<br />
0.01UF<br />
10%<br />
16V<br />
CERM<br />
402<br />
7B6<br />
B<br />
8D2 IN =P1V05ENET_EN<br />
Non-ARB:<br />
5<br />
G<br />
S<br />
4<br />
B<br />
Recommend aliasing PM_SLP_RMGT_L and<br />
=P1V05ENET_EN. Nets separated on<br />
ARB for alternate power options.<br />
A<br />
IN<br />
RTL8211 25MHz Clock<br />
NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.<br />
Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.<br />
77D3 17C3<br />
MCP_CLK25M_BUF0_R<br />
R3895<br />
22<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
PLACEMENT_NOTE=Place close to U1400<br />
RTL8211_CLK25M_CKXTAL1<br />
OUT<br />
31B6 77D3<br />
Ethernet & AirPort Support<br />
SYNC_MASTER=SUMA<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=07/01/2008<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
32 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
- COPY THIS PAGE FROM K36 CSA.39<br />
D<br />
D<br />
ENET_CONN_CTAP<br />
PLACE ONE CAP EACH NEAR PINS 3 AND 4 OF T3901 AND T3902<br />
1 C3900<br />
1 C3901<br />
0.1UF<br />
2<br />
0.1UF<br />
10%<br />
16V<br />
X5R<br />
402<br />
2<br />
10%<br />
16V<br />
X5R<br />
402<br />
1<br />
C3902<br />
0.1UF<br />
10%<br />
2<br />
16V<br />
X5R<br />
402<br />
1<br />
2<br />
C3903<br />
0.1UF<br />
10%<br />
16V<br />
X5R<br />
402<br />
ETHERNET CONNECTOR<br />
C<br />
77C3 31B3 BI<br />
77C3 31B3 BI<br />
77C3 31B3 BI<br />
77C3 31B3 BI<br />
77C3 31B3 BI<br />
77C3 31B3 BI<br />
77C3 31B3 BI<br />
ENET_MDI_P<br />
ENET_MDI_N<br />
ENET_MDI_P<br />
ENET_MDI_N<br />
ENET_MDI_N<br />
ENET_MDI_P<br />
ENET_MDI_N<br />
1<br />
2<br />
3<br />
4<br />
5<br />
11<br />
10<br />
TX<br />
6 7<br />
RX<br />
1<br />
2<br />
3<br />
4<br />
5<br />
CRITICAL<br />
T3901<br />
SM<br />
TLA-6T213HF<br />
CRITICAL<br />
T3902<br />
SM<br />
11<br />
10<br />
TX<br />
TLA-6T213HF<br />
12<br />
9<br />
8<br />
12<br />
9<br />
8<br />
R3903<br />
ENET_CENTER_TAP 1 2<br />
1% 1/16W MF-LF 402<br />
R3902<br />
ENET_CENTER_TAP 1 2<br />
1% 1/16W MF-LF 402<br />
R3901<br />
ENET_CENTER_TAP 1 2<br />
1% 1/16W MF-LF 402<br />
R3900<br />
75<br />
75<br />
75<br />
ENET_CENTER_TAP 1 2 75<br />
1% 1/16W MF-LF 402<br />
77C3<br />
77C3<br />
ENET_MDI_TRAN_P<br />
ENET_MDI_TRAN_N<br />
77C3<br />
77C3<br />
ENET_MDI_TRAN_P<br />
ENET_MDI_TRAN_N<br />
77C3<br />
77C3<br />
77C3<br />
ENET_MDI_TRAN_N<br />
ENET_MDI_TRAN_P<br />
ENET_MDI_TRAN_N<br />
CRITICAL<br />
J3900<br />
RJ45-M97-3<br />
F-RT-TH<br />
9<br />
10<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
11<br />
12<br />
514-0636<br />
C<br />
77C3 31B3<br />
BI<br />
ENET_MDI_P<br />
6 7<br />
RX<br />
77C3<br />
ENET_MDI_TRAN_P<br />
ENET_BOB_SMITH_CAP<br />
MIN_LINE_WIDTH=0.6MM<br />
MIN_NECK_WIDTH=0.25MM<br />
B<br />
1<br />
C3911<br />
10PF<br />
5%<br />
50V<br />
2 CERM<br />
402-1<br />
CRITICAL<br />
1<br />
1<br />
C3915<br />
C3913<br />
10PF<br />
10PF<br />
5%<br />
5%<br />
50V<br />
50V<br />
2 CERM<br />
2 CERM<br />
402-1<br />
402-1<br />
CRITICAL<br />
CRITICAL<br />
CRITICAL<br />
1CRITICAL<br />
C3912<br />
1<br />
C3914<br />
10PF<br />
10PF<br />
5%<br />
5%<br />
2<br />
50V<br />
CERM<br />
2<br />
50V<br />
CERM<br />
402-1<br />
402-1<br />
1<br />
C3917<br />
10PF<br />
5%<br />
50V<br />
2 CERM<br />
402-1<br />
CRITICAL<br />
CRITICAL<br />
1<br />
C3916<br />
10PF<br />
5%<br />
50V<br />
2 CERM<br />
402-1<br />
CRITICAL<br />
1<br />
C3918<br />
10PF<br />
5%<br />
50V<br />
2 CERM<br />
402-1<br />
1<br />
2<br />
CRITICAL<br />
C3910<br />
1000PF<br />
10%<br />
2KV<br />
CERM<br />
1206<br />
B<br />
PLACEMENT_NOTE=PLACE C3911-C3918 ON MDI LINES WITHOUT ANY STUBS<br />
A<br />
SYNC_MASTER=SUMA<br />
ETHERNET CONNECTOR<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=04/04/2008<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
33<br />
81<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
7 mA I/O<br />
=PP3V3_FW_FWPHY<br />
138 mA<br />
7B1 34B1 35D8 36B6 36D5<br />
C4120 1 2<br />
1UF<br />
10%<br />
6.3V<br />
CERM<br />
402<br />
C4121 1<br />
1UF<br />
10%<br />
6.3V<br />
2<br />
CERM<br />
402<br />
C4122<br />
1UF<br />
10%<br />
6.3V<br />
CERM<br />
402<br />
1<br />
2<br />
C4123 1<br />
1UF<br />
10%<br />
6.3V<br />
2<br />
CERM<br />
402<br />
C4124 1<br />
1UF<br />
10%<br />
6.3V<br />
2<br />
CERM<br />
402<br />
D<br />
PART NUMBER<br />
114S0558<br />
35D3 7A1<br />
135 mA<br />
QTY<br />
DESCRIPTION REFERENCE DES CRITICAL BOM OPTION<br />
1 RES,0.68 OHM,1%,0402,SMD<br />
R4100<br />
CRITICAL<br />
=PP1V0_FW_FWPHY<br />
OMIT<br />
R4100<br />
0<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
PP1V0_FW_R<br />
L4110<br />
120-OHM-0.3A-EMI<br />
1<br />
0402-LF<br />
2<br />
PP1V0_FW_FWPHY_AVDD<br />
MIN_LINE_WIDTH=0.4 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=1.0V<br />
1<br />
2<br />
25 mA PCIe SerDes<br />
C4110<br />
1UF<br />
10%<br />
10%<br />
6.3V<br />
6.3V<br />
CERM<br />
2<br />
CERM<br />
402<br />
402<br />
1<br />
C4111<br />
1UF<br />
C4130<br />
1UF<br />
10%<br />
6.3V<br />
CERM<br />
402<br />
1<br />
2<br />
114 mA FireWire PHY<br />
C4131 1<br />
1UF<br />
10%<br />
6.3V<br />
CERM 2<br />
402<br />
17 mA PCIe SerDes<br />
C4135 1<br />
1UF<br />
C4132<br />
1UF<br />
10%<br />
6.3V<br />
CERM<br />
402<br />
C4136<br />
1UF<br />
10%<br />
10%<br />
6.3V 6.3V<br />
CERM 2<br />
CERM<br />
402<br />
402<br />
1<br />
2<br />
1<br />
2<br />
PP3V3_FW_FWPHY_VDDA<br />
MIN_LINE_WIDTH=0.4 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=3.3V<br />
PP3V3_FW_FWPHY_VP25<br />
MIN_LINE_WIDTH=0.4 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=3.3V<br />
L4130<br />
120-OHM-0.3A-EMI<br />
1 2<br />
0402-LF<br />
L4135<br />
120-OHM-0.3A-EMI<br />
1 2<br />
0402-LF<br />
D<br />
110 mA Digital Core<br />
0 mA VReg PWR<br />
1<br />
C4100<br />
1UF<br />
10%<br />
6.3V<br />
2<br />
CERM<br />
402<br />
1<br />
2<br />
C4101<br />
1UF<br />
10%<br />
6.3V<br />
CERM<br />
402<br />
1<br />
2<br />
C4102<br />
1UF<br />
10%<br />
6.3V<br />
CERM<br />
402<br />
1<br />
2<br />
C4103<br />
1UF<br />
10%<br />
6.3V<br />
CERM<br />
402<br />
1<br />
2<br />
C4104<br />
1UF<br />
10%<br />
6.3V<br />
CERM<br />
402<br />
1<br />
2<br />
C4105<br />
1UF<br />
10%<br />
6.3V<br />
CERM<br />
402<br />
1<br />
2<br />
C4106<br />
1UF<br />
10%<br />
6.3V<br />
CERM<br />
402<br />
C4141 1<br />
0.1UF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
1<br />
2<br />
C4140<br />
1UF<br />
10%<br />
6.3V<br />
CERM<br />
402<br />
C<br />
B<br />
A<br />
C4150<br />
22PF<br />
1 2<br />
5%<br />
50V<br />
CERM<br />
402<br />
C4151<br />
22PF<br />
1 2<br />
5%<br />
50V<br />
CERM<br />
402<br />
NC<br />
NC<br />
2 4<br />
1 3<br />
36C4 =PPVP_FW_PHY_CPS<br />
R4150<br />
412<br />
FW_CL<strong>K24</strong>P576M_XO<br />
1<br />
2<br />
CRITICAL<br />
1%<br />
1/16W<br />
Y4150<br />
MF-LF<br />
402<br />
24.576MHZ<br />
SM-3.2X2.5MM<br />
R4160 1<br />
200K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R4161 1<br />
2.94K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R4162 1<br />
470K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
R4170<br />
191<br />
1%<br />
1/16W<br />
MF-LF<br />
2 402<br />
1<br />
2<br />
C4162<br />
0.33UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
402<br />
36D3<br />
36D3<br />
36D3<br />
78D3 36C4<br />
78D3 36C4<br />
78D3 36B8<br />
78D3 36B8<br />
36C4<br />
36C4<br />
78D3 36C4<br />
78D3 36C4<br />
78D3 36B8<br />
78D3 36B8<br />
36C4<br />
36C4<br />
36D4<br />
36C8 35A4<br />
36D4<br />
IN<br />
IN<br />
IN<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
=FW_PHY_DS0<br />
=FW_PHY_DS1<br />
=FW_PHY_DS2<br />
FW_P0_TPA_N<br />
FW_P0_TPA_P<br />
FW_P1_TPA_N<br />
FW_P1_TPA_P<br />
FW_P2_TPA_N<br />
FW_P2_TPA_P<br />
FW_P0_TPB_N<br />
FW_P0_TPB_P<br />
FW_P1_TPB_N<br />
FW_P1_TPB_P<br />
FW_P2_TPB_N<br />
FW_P2_TPB_P<br />
FW_P0_TPBIAS<br />
FW_P1_TPBIAS<br />
FW_P2_TPBIAS<br />
FW643_R0<br />
FW643_TPCPS<br />
TP_FW643_NAND_TREE<br />
FW643_REXT<br />
FW_CL<strong>K24</strong>P576M_XO_R<br />
FW_CL<strong>K24</strong>P576M_XI<br />
TP_FW643_SE<br />
TP_FW643_SM<br />
TP_FW643_MODE_A<br />
TP_FW643_CE<br />
TP_FW643_FW620_L<br />
TP_FW643_JASI_EN<br />
TP_FW643_AVREG<br />
TP_FW643_VBUF<br />
FW643_PU_RST_L<br />
TP_FW643_OCR10_CTL<br />
NC<br />
NC<br />
NC<br />
NC<br />
A1<br />
B13 ATBUSB<br />
A13 ATBUSH<br />
A11 ATBUSN<br />
F12 DS0 (IPD) NT-19<br />
E12 DS1 (IPD) NT-20<br />
E13 DS2 (IPD) NT-21<br />
B8 TPA0N<br />
A8 TPA0P<br />
B5 TPA1N<br />
A5 TPA1P<br />
B3 TPA2N<br />
A3 TPA2P<br />
B9 TPB0N<br />
A9 TPB0P<br />
B6 TPB1N<br />
A6 TPB1P<br />
B4 TPB2N<br />
A4 TPB2P<br />
B7 TPBIAS0<br />
C3 TPBIAS1<br />
A2 TPBIAS2<br />
B11 R0<br />
B10 TPCPS<br />
E2<br />
H2<br />
VDD10<br />
M13 SE (IPD)<br />
N13 SM (IPD)<br />
J2 MODE_A (IPD) NT-18<br />
L13 CE (IPD)<br />
D12 FW620* (IPU)<br />
D1 JASI_EN (IPD) NT-11<br />
A10 AVREG<br />
H13 VBUF<br />
K13 FW_RESET* (IPU) NT-8<br />
VDD33<br />
1394 PHY<br />
K1 NAND_TREE NT-OUT<br />
L8 REXT<br />
NOTE: NT-xx notes show<br />
F13 XO<br />
NAND tree order.<br />
G13 XI NT-9<br />
B2<br />
B1<br />
J12 OCR_CTL_V10<br />
J13 OCR_CTL_V12 (Reserved)<br />
D4<br />
B12<br />
D7<br />
C13<br />
D9<br />
D10<br />
E10<br />
E4<br />
E5<br />
H12<br />
E9<br />
K2<br />
F4<br />
L1<br />
F6<br />
M12<br />
F7<br />
N3<br />
F8<br />
N11<br />
C1<br />
C12<br />
MISCELLANEOUS<br />
F10<br />
G4<br />
G6<br />
G7<br />
F1<br />
G8<br />
G12<br />
G10<br />
J1<br />
CRITICAL<br />
U4100<br />
FW643E<br />
VSS<br />
H4<br />
L3<br />
BGA<br />
H6<br />
L11<br />
H7<br />
M2<br />
H8<br />
A12<br />
VDDH VP VP25 VREG_PWR<br />
PCI EXPRESS PHY<br />
TEST CONTROLLER<br />
SCIF<br />
SERIAL EEPROM<br />
CONTROLLER<br />
CHIP RESET<br />
K8<br />
K9<br />
PCIE_RXD0N N8<br />
PCIE_RXD0P N7<br />
PCIE_TXD0N N5<br />
PCIE_TXD0P N6<br />
NT-10 (IPD) WAKE* C2<br />
FIXME!!! - TYPO IN SYMBOL REGCTL<br />
REGCLT D13<br />
POWER MANAGEMENT<br />
VAUX_DETECT E1<br />
NT-12 (IPD)<br />
VAUX_DISABLE D2<br />
NT-13<br />
(OD) CLKREQN L2<br />
H10<br />
D5<br />
J4<br />
D6<br />
J5<br />
D8<br />
J9<br />
J10<br />
L5<br />
K4<br />
L10<br />
K5<br />
L6<br />
K7<br />
L9<br />
NT-16 (IPD) SCIFCLK G2<br />
NT-14 (IPD) SCIFDAIN G1<br />
NT-17 SCIFDOUT H1<br />
NT-15 (IPD) SCIFMC F2<br />
L7<br />
K12<br />
NT-7 SCL<br />
NT-6 SDA<br />
NT-5<br />
REFCLKN N9<br />
REFCLKP N10<br />
NT-4 (IPU) TCK M4<br />
NT-3 (IPU) TDI N2<br />
(IPU) TDO M1<br />
NT-1 (IPU) TMS M3<br />
NT-2 (IPU) TRST* N1<br />
K6<br />
K10<br />
PERST*<br />
VREG_VSS<br />
L12<br />
N12<br />
M11<br />
N4<br />
75D3 PCIE_FW_R2D_N<br />
75D3 PCIE_FW_R2D_P<br />
75D3 PCIE_FW_D2R_C_N<br />
75D3 PCIE_FW_D2R_C_P<br />
PCIE_CLK100M_FW_N<br />
PCIE_CLK100M_FW_P<br />
TP_FW643_TCK<br />
TP_FW643_TDI<br />
TP_FW643_TDO<br />
TP_FW643_TMS<br />
FW643_TRST_L<br />
=FW_PME_L<br />
FW643_REGCTL<br />
FW643_VAUX_DETECT<br />
TP_FW643_VAUX_ENABLE<br />
=FW_CLKREQ_L<br />
TP_FW643_SCIFCLK<br />
TP_FW643_SCIFDAIN<br />
TP_FW643_SCIFDOUT<br />
TP_FW643_SCIFMC<br />
FW643_SCL<br />
TP_FW643_SDA<br />
FW_RESET_L<br />
1<br />
R4163<br />
10K<br />
5%<br />
1/16W<br />
2 402<br />
MF-LF<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
16C3<br />
16C3<br />
8C2 35C8<br />
35C4<br />
35C1<br />
C4170<br />
1 10% 2<br />
0.1UF<br />
X5R<br />
C41711 10% 2<br />
0.1UF<br />
X5R<br />
C41751 10% 2<br />
0.1UF<br />
X5R<br />
C41761 10% 2<br />
0.1UF<br />
PLACEMENT_NOTE=Place C4170 close to U1400<br />
PLACEMENT_NOTE=Place C4171 close to U1400<br />
X5R<br />
FW643_LDO<br />
R4165 1<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
R4164<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
16V<br />
402<br />
16V<br />
402<br />
16V<br />
402<br />
16V<br />
402<br />
PCIE_FW_R2D_C_N<br />
PCIE_FW_R2D_C_P<br />
PCIE_FW_D2R_N<br />
PCIE_FW_D2R_P<br />
PLACEMENT_NOTE=Place C4175 close to U4000<br />
PLACEMENT_NOTE=Place C4176 close to U4000<br />
1<br />
R4166<br />
10K<br />
5%<br />
1/16W<br />
2 402<br />
MF-LF<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
16B3 75D3<br />
16B3 75D3<br />
16B6 75D3<br />
16B6 75D3<br />
FireWire LLC/PHY (FW643)<br />
SYNC_MASTER=K19_<strong>MLB</strong><br />
=PP3V3_FW_FWPHY<br />
7B1 34D2 35D8 36B6 36D5<br />
NOTICE OF PROPRIETARY PROPERTY<br />
SYNC_DATE=11/02/2008<br />
C<br />
B<br />
A<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
34 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
E<br />
D<br />
C<br />
8 7 6 5 4 3 2 1<br />
Page Notes<br />
3.3V FW FET<br />
Power aliases required by this page:<br />
- =PPBUS_S5_FWPWRSW (system supply for bus power)<br />
- =PP3V3_FW_LATEVG_ACTIVE<br />
- =PPVP_FW_SUMNODE (power passthru summation node)<br />
Signal aliases required by this page:<br />
(NONE)<br />
BOM options provided by this page:<br />
1<br />
R4277<br />
10K 5%<br />
1/16W<br />
MF-LF<br />
4022<br />
FWPHY_WAKE_YES<br />
8C2<br />
34B2<br />
36B6<br />
34D2<br />
34B1<br />
7B1<br />
36D5<br />
=PP3V3_FW_FWPHY<br />
=FW_PME_L<br />
CRITICAL<br />
2 G<br />
FWPHY_WAKE_YES<br />
1R4276<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
6<br />
D<br />
S<br />
1<br />
FW_WAKE<br />
Q4276<br />
DMB53D0UV<br />
SOT-563<br />
5<br />
7A3<br />
FWPHY_WAKE_YES<br />
FW_PLUG_DET_L<br />
Q4293<br />
SSM6N15FEAPE<br />
SOT563<br />
8C1 35B1<br />
3 CRITICAL<br />
Q4276<br />
DMB53D0UV<br />
SOT-563<br />
4 FWPHY_WAKE_YES<br />
=PP3V3_S5_P1V05FWFET<br />
35C7 35C4 35A4 18D7 18D2<br />
R4295 1 10K 5%<br />
1/16W<br />
MF-LF<br />
4022<br />
D 3<br />
7B1<br />
IN<br />
7B5<br />
P1V05_FW_EN_L<br />
=PP3V3_S0_P3V3FWFET<br />
FW_PWR_EN<br />
=PP3V3_S0_P1V05FWFET<br />
R4296<br />
100K<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2 G<br />
R4290 1<br />
Q4290<br />
SSM6N15FEAPE<br />
SOT563<br />
10K 5%<br />
1/16W<br />
MF-LF<br />
4022<br />
5 G<br />
D 6<br />
S 1<br />
D 3<br />
S 4<br />
@ 2.5V Vgs:<br />
Rds(on) = 90mOhm max<br />
I(max) = 1.7A (85C)<br />
1.05V FW FET<br />
7C7 =PP1V05_FW_P1V05FWFET<br />
C4296<br />
1<br />
0.1UF<br />
20%<br />
R4297<br />
1 220K 10V<br />
CERM 2<br />
2<br />
402<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
Q4293<br />
SSM6N15FEAPE<br />
SOT563<br />
P1V05FW_SS<br />
P1V05_FW_EN_L_RC<br />
P3V3FW_EN_L<br />
1<br />
G<br />
C4295<br />
1<br />
0.068UF<br />
10%<br />
2<br />
10V<br />
CERM<br />
402<br />
R4291<br />
100K<br />
1 2<br />
3<br />
D<br />
S<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1 C4290<br />
CRITICAL<br />
Q4295<br />
SI2312BDS<br />
SOT23<br />
0.033UF<br />
10%<br />
2<br />
16V<br />
X5R<br />
402<br />
=PP1V0_FW_FET<br />
P3V3FW_SS<br />
CRITICAL<br />
Q4291<br />
NTR4101P<br />
SOT-23-HF<br />
2<br />
S<br />
1<br />
G<br />
35D6 35C7 35A4 18D7 18D2<br />
7B2<br />
34B2<br />
IN<br />
D<br />
3<br />
C4291<br />
0.01UF<br />
2 1<br />
10%<br />
16V<br />
CERM<br />
402<br />
Q4264<br />
SSM6N15FEAPE<br />
SOT563<br />
FW_PWR_EN<br />
5 G<br />
=FW_CLKREQ_L<br />
=PP3V3_FW_FET<br />
D 3<br />
S 4<br />
7B2<br />
PCIE_FW_PRSNT_L<br />
OUT<br />
MAKE_BASE=TRUE<br />
Q4264<br />
SSM6N15FEAPE<br />
SOT563<br />
2 G<br />
D 6<br />
S 1<br />
FW_CLKREQ_PHY_L<br />
MAKE_BASE=TRUE<br />
8C6 16C6<br />
FW_CLKREQ_L<br />
OUT<br />
16C6<br />
34D8 7A1<br />
35B1 7B5<br />
=PP1V0_FW_FWPHY<br />
P1V0_FW_RC<br />
C4281 1<br />
1UF<br />
10%<br />
6.3V<br />
CERM<br />
402<br />
CRITICAL<br />
2 G<br />
FireWire Port Power Switch<br />
=PP3V3_S0_FWPWRCTL<br />
2<br />
R4280<br />
1<br />
10K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
6<br />
D<br />
S<br />
1<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
Q4299<br />
DMB53D0UV<br />
SOT-563<br />
1<br />
R4281<br />
100K<br />
3 CRITICAL<br />
5 Q4299<br />
P1V0_RESET_GATE<br />
DMB53D0UV<br />
SOT-563<br />
4<br />
R4283<br />
10K<br />
1 2 =FW_RESET_L<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
FW_RESET_L<br />
PP1V05_FW PGOOD/FW_RESET_L<br />
OUT<br />
34A2<br />
IN<br />
24C1<br />
D<br />
C<br />
35D6 35C4 35A4 18D7 18D2<br />
FW_PWR_EN<br />
5 G<br />
Late-VG Event Detection<br />
7C1<br />
S 4<br />
=PPBUS_S5_FWPWRSW<br />
CRITICAL<br />
Q4262<br />
DMB54D0UV<br />
SOT-563<br />
1<br />
R4260<br />
300K C4260<br />
5%<br />
0.1UF<br />
1/16W<br />
10%<br />
25V<br />
MF-LF<br />
X5R<br />
2402<br />
402<br />
FWPWR_EN_L_DIV<br />
1<br />
2<br />
4<br />
CRITICAL<br />
Q4260<br />
FDC638P_G<br />
3<br />
SM<br />
6<br />
5<br />
2<br />
1<br />
PPBUS_FW_FWPWRSW_F<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.25 mm<br />
VOLTAGE=12.6V<br />
CRITICAL<br />
F4260<br />
1.1A-24V<br />
1 2<br />
MINISMDC110H24<br />
PPBUS_FW_FWPWRSW_D<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.25 mm<br />
VOLTAGE=12.6V<br />
CRITICAL<br />
D4260<br />
SM<br />
1 2 =PPBUS_S5_FW_FET<br />
CRS08-1.5A-30V<br />
7B2<br />
=PP3V3_S0_FWPWRCTL<br />
7B5 35D2<br />
B<br />
A<br />
C4263 1<br />
1UF<br />
2<br />
7A3<br />
36C5 36A5<br />
10%<br />
10V<br />
X5R<br />
402<br />
LATEVG_RETRY_RC<br />
NOSTUFF<br />
=PP3V3_FW_LATEVG_ACTIVE<br />
PP2V4_FW_LATEVG<br />
1<br />
R4211<br />
10K 5%<br />
1/16W<br />
MF-LF<br />
4022<br />
C4211<br />
1<br />
100pF<br />
5%<br />
50V<br />
CERM 2<br />
402<br />
NOSTUFF<br />
R4263<br />
1<br />
100<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R4212<br />
1<br />
10K<br />
1%<br />
1/16W<br />
MF-LF<br />
2402<br />
FWLATEGV_3V_REF<br />
1<br />
R4213<br />
80.6K<br />
1%<br />
1/16W<br />
MF-LF<br />
2402<br />
R4265<br />
10K<br />
2 1<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
P2V4_FWLATEVG_RC<br />
LATEVG_FAULT_EVENT_PNP<br />
LATEVG_FAULT_EVENT<br />
3<br />
4<br />
V+<br />
V-<br />
R4210<br />
200K<br />
1<br />
2<br />
5<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
U4210<br />
2<br />
4<br />
6 5<br />
B<br />
D<br />
1 C4210<br />
0.1UF<br />
20%<br />
2<br />
10V CERM<br />
402<br />
LMC7211<br />
SM-HF<br />
1 LATEVG_EVENT<br />
FWLATEVG Hysteresis:<br />
Q2<br />
Q1<br />
C<br />
G<br />
S<br />
3<br />
1 2<br />
3.08V when port power is on<br />
2.91V when late Vg event and port power is off<br />
40D5<br />
20C7<br />
32B7<br />
41B2<br />
70D8 66D5 40C5 32B7 20C3 6C3<br />
IN<br />
IN<br />
SMC_ADAPTER_EN<br />
PM_SLP_S3_L<br />
2 G<br />
Enables port power when machine<br />
is running or on AC.<br />
D<br />
S<br />
1R4261<br />
470K<br />
5%<br />
1/16W<br />
MF-LF<br />
2402<br />
FWPWR_EN_L<br />
6<br />
Q4261<br />
1<br />
2N7002DW-X-G<br />
SOT-363<br />
5<br />
35D6 35C7 35C4 18D7 18D2<br />
36C8 34B6<br />
G<br />
IN<br />
IN<br />
D<br />
S<br />
3<br />
4<br />
7C7<br />
Q4261<br />
SOT-363<br />
FW_PWR_EN<br />
=PP1V05_FWPWRCTL<br />
2N7002DW-X-G<br />
FW_P1_TPBIAS<br />
FW_PWR_EN_L<br />
CRITICAL<br />
2 G<br />
R4275<br />
1K<br />
1<br />
5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
6<br />
D<br />
S<br />
1<br />
CRITICAL<br />
Q4270<br />
BC847CDXV6TXG<br />
SOT563<br />
FW_P1_TPBIAS_R<br />
Q4275<br />
DMB53D0UV<br />
SOT-563<br />
3<br />
4<br />
R4270<br />
1<br />
330K<br />
5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
5<br />
1<br />
R4272<br />
1K 5%<br />
1/16W<br />
MF-LF<br />
2402<br />
FW_DET_MIRROR<br />
2<br />
FW_DET_EMIT<br />
1<br />
56K<br />
5%<br />
1/16W<br />
MF-LF<br />
2402<br />
6 CRITICAL<br />
Q4270<br />
BC847CDXV6TXG<br />
SOT563<br />
1<br />
R4271<br />
FW_PLUG_DET<br />
1<br />
R4273<br />
12K<br />
5%<br />
1/16W<br />
MF-LF<br />
2402<br />
1 C4270<br />
0.1UF<br />
10%<br />
2<br />
16V<br />
X5R<br />
402<br />
APPLE INC.<br />
5<br />
SYNC_MASTER=YUN_K19_<strong>MLB</strong><br />
1<br />
R4274<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
2402<br />
FW_PLUG_DET_L<br />
3 CRITICAL<br />
4<br />
Q4275<br />
DMB53D0UV<br />
SOT-563<br />
SCALE<br />
OUT<br />
FireWire Port Power<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
DRAWING NUMBER<br />
SHT<br />
8C1 35D7<br />
OF<br />
SYNC_DATE=12/22/2008<br />
REV.<br />
051-7898 4.7.0<br />
B<br />
A<br />
NONE<br />
35<br />
81<br />
8 7 6 5 4 3 2 1
5<br />
4<br />
3<br />
D<br />
8 7 6 5 4 3 2 1<br />
Page Notes<br />
Power aliases required by this page:<br />
- =PPVP_FW_PORT1<br />
- =PP3V3_FW_LATEVG<br />
- =GND_CHASSIS_FW_PORT1<br />
- =GND_CHASSIS_FW_EMI_R<br />
Signal aliases required by this page:<br />
(NONE)<br />
NOTE: This page is expected to contain<br />
the necessary aliases to map the<br />
FireWire TPA/TPB pairs to their<br />
appropriate connectors and/or to<br />
properly terminate unused signals.<br />
BOM options provided by this page:<br />
(NONE)<br />
FireWire PHY Config Straps<br />
Configures PHY for:<br />
- 1-port Portable Power Class (0)<br />
- Port "1" Bilingual (1394B)<br />
36B6 35D8 34D2 34B1 7B1<br />
=PP3V3_FW_FWPHY<br />
R4382 1<br />
10K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R4380 1<br />
10K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R4381 1<br />
10K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
FWPHY_DS0<br />
MAKE_BASE=TRUE<br />
FWPHY_DS2<br />
MAKE_BASE=TRUE<br />
FWPHY_DS1<br />
MAKE_BASE=TRUE<br />
=FW_PHY_DS0<br />
=FW_PHY_DS2<br />
=FW_PHY_DS1<br />
34C6<br />
34C6<br />
34C6<br />
D<br />
NOTE: FireWire TPA/TPB pairs are NOT<br />
constrained on this page. It is<br />
assumed that FireWire PHY page will<br />
provide the appropriate constraints<br />
to apply to entire TPA/TPB XNets.<br />
1394b implementation based on Apple<br />
FireWire Design Guide (FWDG 0.6, 5/14/03)<br />
34B6 FW_P0_TPBIAS<br />
34B6 FW_P2_TPBIAS<br />
78D3 34C6 FW_P0_TPA_N<br />
78D3 34B6 FW_P0_TPA_P<br />
34B6 FW_P2_TPA_N<br />
34B6 FW_P2_TPA_P<br />
NC_FW0_TPBIAS<br />
NC_FW2_TPBIAS<br />
NC_FW0_TPAN<br />
NC_FW0_TPAP<br />
NC_FW2_TPAN<br />
NC_FW2_TPAP<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
Termination<br />
Place close to FireWire PHY<br />
78D3 34B6 FW_P0_TPB_N<br />
78D3 34B6 FW_P0_TPB_P<br />
34B6 FW_P2_TPB_N<br />
34B6 FW_P2_TPB_P<br />
NC_FW0_TPBN<br />
NC_FW0_TPBP<br />
NC_FW2_TPBN<br />
NC_FW2_TPBP<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
C<br />
B<br />
35A4 34B6 FW_P1_TPBIAS<br />
78D3 34B6 FW_P1_TPA_P<br />
78D3 34B6 FW_P1_TPA_N<br />
78D3 34B6 FW_P1_TPB_P<br />
78D3 34B6 FW_P1_TPB_N<br />
TI PHYs require 1uF even though<br />
FW spec calls out 0.33uF<br />
SIGNAL_MODEL=EMPTY<br />
SIGNAL_MODEL=EMPTY<br />
1<br />
SIGNAL_MODEL=EMPTY<br />
R4362<br />
56.2<br />
1<br />
2<br />
1<br />
1<br />
2<br />
R4360<br />
56.2<br />
2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
SIGNAL_MODEL=EMPTY<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
C4364<br />
220pF<br />
2 25V<br />
5%<br />
CERM<br />
402<br />
C4360<br />
0.33UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
402<br />
FW_PORT1_TPB_C<br />
R4361 1<br />
56.2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R4363 1<br />
56.2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R4364 1<br />
4.99K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
FW_PORT1_TPA_P<br />
MAKE_BASE=TRUE<br />
FW_PORT1_TPA_N<br />
MAKE_BASE=TRUE<br />
FW_PORT1_TPB_P<br />
MAKE_BASE=TRUE<br />
FW_PORT1_TPB_N<br />
MAKE_BASE=TRUE<br />
7B1 =PPVP_FW_PHY_CPS_FET<br />
R4311 1<br />
470K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
36B5<br />
36B5<br />
36B5<br />
36D5 35D8 34D2 34B1 7B1<br />
36B5<br />
CPS_EN_L_DIV<br />
R4312 1<br />
330K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2 CPS_EN_L<br />
=PP3V3_FW_FWPHY<br />
2<br />
G<br />
(SYM-VER2)<br />
SOT-363<br />
BSS8402DW<br />
S<br />
Q4300<br />
G<br />
6<br />
D<br />
S<br />
1<br />
D<br />
Q4300<br />
BSS8402DW<br />
SOT-363<br />
(SYM-VER1)<br />
PPVP_FW_CPS<br />
MIN_LINE_WIDTH=0.4 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=12.6V<br />
MAKE_BASE=TRUE<br />
"Snapback" & "Late VG" Protection<br />
36A5 35A8 PP2V4_FW_LATEVG<br />
C4310 1<br />
0.01uF<br />
10%<br />
50V<br />
2<br />
36B7 FW_PORT1_TPB_N<br />
36B7 FW_PORT1_TPB_P<br />
36B7 FW_PORT1_TPA_N<br />
36B7 FW_PORT1_TPA_P<br />
=PPVP_FW_PHY_CPS<br />
X7R<br />
402<br />
C4312 1<br />
0.01uF<br />
10%<br />
50V<br />
2<br />
X7R<br />
402<br />
DP4310<br />
BAV99DW-X-G<br />
SOT-363<br />
2<br />
1<br />
2<br />
C4311 1<br />
0.01uF<br />
10%<br />
50V<br />
2<br />
6<br />
DP4311<br />
BAV99DW-X-G<br />
SOT-363<br />
1<br />
34B7<br />
6<br />
X7R<br />
402<br />
C4313 1<br />
0.01uF<br />
10%<br />
50V<br />
2<br />
X7R<br />
402<br />
DP4310<br />
BAV99DW-X-G<br />
SOT-363<br />
5 CRITICAL<br />
4<br />
3<br />
CRITICAL<br />
DP4311<br />
BAV99DW-X-G<br />
SOT-363<br />
5<br />
4<br />
3<br />
Cable Power<br />
7B1 =PPVP_FW_PORT1<br />
C4319 1<br />
0.1uF<br />
10%<br />
50V<br />
2<br />
1<br />
R4319<br />
1M<br />
X7R<br />
603-1<br />
PLACEMENT_NOTE=Place C4319 close to connector pin 5.<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
2<br />
CRITICAL<br />
L4310<br />
FERR-250-OHM<br />
C4314<br />
0.01UF<br />
10%<br />
50V<br />
X7R<br />
402<br />
1 2<br />
SM<br />
(FW_PORT1_BREF)<br />
(GND_FW_PORT1_VG)<br />
AREF needs to be isolated from all<br />
local grounds per 1394b spec<br />
Note: Trace PPVP_FW_PORT1 must handle up to 5A<br />
PPVP_FW_PORT1_F<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.25 mm<br />
VOLTAGE=33V<br />
FW_PORT1_AREF<br />
When a bilingual device is connected to a<br />
beta-only device, there is no DC path<br />
between them (to avoid ground offset issue)<br />
BREF should be hard-connected to logic<br />
ground for speed signaling and connection<br />
NC 7<br />
PORT 1<br />
BILINGUAL<br />
1<br />
9<br />
2<br />
8<br />
6<br />
3<br />
5<br />
4<br />
10<br />
11<br />
12<br />
13<br />
CRITICAL<br />
J4310<br />
1394B-M97<br />
TPB+<br />
F-RT-TH<br />
TPA+<br />
TPB<br />
TPB+ VP<br />
VP<br />
NCSC/NC<br />
VG<br />
TPB-<br />
TPA-<br />
TPB(R)<br />
TPB-<br />
TPA- VG<br />
TPA<br />
TPA(R)<br />
TPA+<br />
CHASSIS<br />
GND<br />
OUTPUT<br />
INPUT<br />
514S0605<br />
C<br />
B<br />
A<br />
Late-VG Protection Power<br />
7A3 =PP3V3_FW_LATEVG<br />
PP2V4_FWLATEVG needs to be biased<br />
to at least 2.1V for FW signal integrity<br />
and should be biased to 2.4V for margin<br />
R4390 should be 390 Ohms max for a 3.3V rail<br />
R4390<br />
332<br />
1 2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
3<br />
1<br />
PP2V4_FW_LATEVG<br />
MIN_LINE_WIDTH=0.38 mm<br />
MIN_NECK_WIDTH=0.25 mm<br />
VOLTAGE=2.4V<br />
ESD and late-VG rail<br />
CRITICAL<br />
for snap-back diodes<br />
D4390 (Common to all ports)<br />
MMBZ5227BLT1H<br />
SOT23<br />
35A8 36C5<br />
SYNC_MASTER=K19_<strong>MLB</strong><br />
APPLE INC.<br />
FireWire Ports<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
36<br />
SYNC_DATE=11/02/2008<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
A<br />
8 7 6 5 4 3 2 1
S<br />
D<br />
8 7 6 5 4 3 2 1<br />
ODD Power Control<br />
NOTE: 3.3V must be S0 if 5V is S3 or S5 to<br />
ensure the drive is unpowered in S3/S5.<br />
37C7 7C5<br />
=PP3V3_S0_ODD<br />
R4597<br />
100K<br />
1/16W<br />
5%<br />
MF-LF<br />
402<br />
7C3<br />
=PP5V_S3_ODD<br />
R4596<br />
100K<br />
1/16W<br />
5%<br />
MF-LF<br />
402<br />
Q4596<br />
D 6<br />
SSM6N15FEAPE<br />
SOT563<br />
ODD_PWR_EN<br />
ODD_PWR_EN_LS5V_L<br />
R4595<br />
100K<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1 C4595<br />
1 2 3<br />
0.068UF<br />
10%<br />
2<br />
10V CERM<br />
402<br />
ODD_PWR_SS<br />
CRITICAL<br />
Q4590<br />
TPCP8102<br />
23V1K-SM<br />
G<br />
4<br />
D<br />
5 6 7 8<br />
C4596<br />
0.01UF<br />
1 2<br />
10%<br />
16V<br />
CERM<br />
402<br />
6C3 6B7 PP5V_SW_ODD<br />
MIN_LINE_WIDTH=0.6mm<br />
MIN_NECK_WIDTH=0.4mm<br />
VOLTAGE=5V<br />
D<br />
D 3<br />
Q4596<br />
SSM6N15FEAPE<br />
SOT563<br />
2 G<br />
S 1<br />
20B3<br />
IN<br />
ODD_PWR_EN_L<br />
5 G<br />
S 4<br />
C<br />
37D6 7C5<br />
40B8 6B7 OUT<br />
=PP3V3_S0_ODD<br />
R4590<br />
SMC_ODD_DETECT<br />
1<br />
33K<br />
1/16W<br />
5%<br />
MF-LF<br />
4022<br />
SATA ODD<br />
CRITICAL<br />
J4500<br />
54722-0164<br />
F-ST-SM<br />
2<br />
4<br />
6<br />
8<br />
10<br />
12<br />
14<br />
16<br />
1<br />
3<br />
5<br />
7<br />
9<br />
11<br />
13<br />
15<br />
516S0616<br />
75A3 6B7<br />
75A3 6B7 6A7<br />
75A3 6B7<br />
75A3 6B7<br />
SATA_ODD_R2D_P<br />
SATA_ODD_R2D_N<br />
SATA_ODD_D2R_C_N<br />
SATA_ODD_D2R_C_P<br />
CRITICAL<br />
FL4520<br />
90-OHM-100MA<br />
DLP11S<br />
SYM_VER-1<br />
3 4 75A3 SATA_ODD_R2D_UF_P 1 2<br />
0.01UF 10% 16V CERM 402<br />
2<br />
1 75A3 SATA_ODD_R2D_UF_N<br />
0.01UF<br />
PLACEMENT_NOTE=Place FL4520 close to J4500<br />
PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500<br />
PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526<br />
C4526<br />
1 2 75A3 SATA_ODD_D2R_UF_N<br />
0.01UF 10% 16V CERM 402<br />
C4525 1 2<br />
0.01UF<br />
75A3 SATA_ODD_D2R_UF_P<br />
10% 16V CERM 402<br />
PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79<br />
PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520<br />
C4521<br />
1 2C4520<br />
10% 16V CERM 402<br />
FL4525<br />
90-OHM-100MA<br />
DLP11S<br />
SYM_VER-1<br />
4 CRITICAL 3 SATA_ODD_D2R_N<br />
1 2<br />
SATA_ODD_R2D_C_P<br />
SATA_ODD_R2D_C_N<br />
SATA_ODD_D2R_P<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
19D6 75A3<br />
19D6 75A3<br />
19D6 75A3<br />
19D6 75A3<br />
C<br />
Indicates disc presence<br />
PLACEMENT_NOTE=Place FL4525 close to J4500<br />
B<br />
SATA HDD/IR/SIL<br />
6C3 6B7 PP5V_S0_HDD_FLT<br />
MIN_LINE_WIDTH=0.6mm<br />
MIN_NECK_WIDTH=0.2MM<br />
VOLTAGE=5V<br />
C4501<br />
1<br />
0.1UF<br />
20%<br />
2<br />
10V<br />
CERM<br />
402 CRITICAL<br />
L4500<br />
FERR-70-OHM-4A<br />
1<br />
2<br />
0603<br />
PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501<br />
C4502<br />
1<br />
0.1UF<br />
20%<br />
2<br />
10V<br />
CERM<br />
402<br />
PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501<br />
PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501<br />
=PP5V_S0_HDD<br />
7D5<br />
B<br />
A<br />
7D3<br />
=PP1V5_S3_HDD<br />
41A6<br />
39D7 7C3<br />
SYS_LED_ANODE<br />
=PP5V_S3_IR<br />
L4502<br />
FERR-220-OHM<br />
1<br />
2<br />
PP1V5_S3_HDD_FLT<br />
0402<br />
1 C4503<br />
1UF<br />
2 6.3V 10%<br />
CERM<br />
402<br />
PLACEMENT_NOTE=PLACE C4503 CLOSE TO J4501<br />
R4532<br />
10<br />
2 1<br />
402<br />
1/16W<br />
5%<br />
MF-LF<br />
R4531<br />
4.7<br />
2<br />
402<br />
1<br />
2<br />
1<br />
5% 1/16W<br />
MF-LF<br />
C4532<br />
0.1UF<br />
10%<br />
16V<br />
X7R-CERM<br />
402<br />
6A7 SYS_LED_ANODE_R<br />
6A7 IR_RX_OUT<br />
39D4<br />
6A7 PP5V_S3_IR_R<br />
1<br />
C4531<br />
0.001UF<br />
10%<br />
50V<br />
2 CERM<br />
402<br />
CRITICAL<br />
J4501<br />
54722-0224<br />
1<br />
3<br />
5<br />
7<br />
9<br />
11<br />
13<br />
15<br />
17<br />
19<br />
21<br />
F-ST-SM<br />
2<br />
4<br />
6<br />
8<br />
10<br />
12<br />
14<br />
16<br />
18<br />
20<br />
22<br />
516S0687<br />
75A3 6B7<br />
75A3 6B7<br />
75A3<br />
75A3 6B7<br />
6B7<br />
SATA_HDD_D2R_C_N<br />
SATA_HDD_D2R_C_P<br />
SATA_HDD_R2D_N<br />
90-OHM-100MA<br />
DLP11S<br />
3<br />
C4515 1<br />
0.01UF<br />
C4516 1<br />
CRITICAL<br />
FL4501<br />
SYM_VER-1<br />
4<br />
2<br />
75A3 SATA_HDD_D2R_UF_N<br />
10% 16V CERM 402<br />
CRITICAL<br />
FL4502<br />
90-OHM-100MA<br />
DLP11S<br />
SYM_VER-1<br />
4 3<br />
2<br />
75A3 SATA_HDD_D2R_UF_P 1<br />
2<br />
SATA_HDD_D2R_P<br />
0.01UF 10% 16V CERM 402<br />
PLACEMENT_NOTE=Place C4515 next to C4516<br />
PLACEMENT_NOTE=Place C4516 close to J4501<br />
PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501<br />
SATA_HDD_R2D_UF_N<br />
SATA_HDD_R2D_P<br />
2<br />
1<br />
75A3 SATA_HDD_R2D_UF_P<br />
PLACEMENT_NOTE=Place FL4501 close to J4501<br />
75A3<br />
PLACEMENT_NOTE=Place C4511 next to C4510<br />
PLACEMENT_NOTE=Place C4510 close to MCP79<br />
C4511 1 2 SATA_HDD_R2D_C_N<br />
0.01UF 10% 16V CERM 402<br />
C4510 1 2<br />
0.01UF<br />
SATA_HDD_D2R_N<br />
SATA_HDD_R2D_C_P<br />
10% 16V CERM 402<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
19D6 75A3<br />
19D6 75A3<br />
19D6 75A3<br />
SATA Connectors<br />
SYNC_MASTER=K19_<strong>MLB</strong><br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
SYNC_DATE=12/04/2008<br />
A<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
37<br />
81<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
D<br />
Port Power Switch<br />
USB PORT A (FRONT PORT)<br />
C<br />
7C3 =PP5V_S3_EXTUSB<br />
19C2 OUT USB_EXTA_OC_L<br />
19C2 OUT USB_EXTB_OC_L<br />
NOSTUFF<br />
1<br />
C4690<br />
10UF<br />
20%<br />
6.3V<br />
X5R<br />
2<br />
603<br />
We can remove C4690 later if the output cap of the 5V_S5 regulator is close enough.<br />
1<br />
2<br />
C4691<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
2<br />
8<br />
3<br />
5<br />
4<br />
CRITICAL<br />
U4690<br />
TPS2064DGN<br />
IN<br />
7<br />
OUT1<br />
MSOP<br />
OC1*<br />
EN1 OUT2<br />
6<br />
OC2*<br />
EN2<br />
GND TPAD<br />
1 9<br />
C4695<br />
1<br />
10UF<br />
20%<br />
6.3V<br />
X5R 2<br />
603<br />
1<br />
2<br />
PP5V_S3_RTUSB_A_ILIM<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.5 mm<br />
VOLTAGE=5V<br />
PP5V_S3_RTUSB_B_ILIM<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.5 mm<br />
VOLTAGE=5V<br />
CRITICAL<br />
C4696<br />
100UF<br />
20%<br />
6.3V<br />
POLY-TANT<br />
CASE-B2-SM<br />
C4617<br />
1<br />
CRITICAL<br />
1<br />
C4616<br />
10UF<br />
100UF<br />
6.3V<br />
20% 20%<br />
X5R<br />
2 2 6.3V<br />
POLY-TANT<br />
603<br />
CASE-B2-SM<br />
76C3 USB_EXTA_MUXED_N<br />
76C3 USB_EXTA_MUXED_P<br />
C4605<br />
0.01uF<br />
20%<br />
16V<br />
CERM<br />
402<br />
1<br />
2<br />
PLACEMENT_NOTE=NEAR J4600<br />
CRITICAL<br />
L4605<br />
FERR-220-OHM-2.5A<br />
1<br />
1<br />
0603<br />
PLACEMENT_NOTE=NEAR J4600<br />
CRITICAL<br />
L4600<br />
90-OHM<br />
DLP0NS<br />
SYM_VER-1<br />
2<br />
4 3<br />
2<br />
PP5V_S3_RTUSB_A_F<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.5 mm<br />
VOLTAGE=5V<br />
76C3 CONN_USB_EXTA_N<br />
76C3 CONN_USB_EXTA_P<br />
6 VBUS<br />
2 5 3 4<br />
NC<br />
IO<br />
NC<br />
IO<br />
CRITICAL<br />
J4600<br />
USB<br />
F-RT-TH-M97-4<br />
5<br />
6<br />
1<br />
2<br />
3<br />
4<br />
7<br />
8<br />
C<br />
66B6<br />
IN<br />
=USB_PWR_EN<br />
CAN NOSTUFF C4696 AND C4616 AFTER CHARACTERIZATION<br />
1 GND<br />
514-0638<br />
B<br />
A<br />
42C3 41B2 40C5 40B8<br />
42C5 41C2 40C5 40B8<br />
USB/SMC Debug Mux<br />
7D1<br />
76C3 19D3<br />
76C3 19D3<br />
=PP3V42_G3H_SMCUSBMUX<br />
IN<br />
OUT<br />
BI<br />
BI<br />
SMC_RX_L<br />
SMC_TX_L<br />
USB_EXTA_P<br />
USB_EXTA_N<br />
SMC_DEBUG_YES<br />
C4650<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
1<br />
2<br />
SMC_DEBUG_NO<br />
R4651<br />
0<br />
1<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
STUFF R4691 IF USING TPS2060(ACTIVE LOW ENABLE)<br />
STUFF R4690 IF USING TPS2064(ACTIVE HIGH ENABLE)<br />
VCC<br />
5 SMC_DEBUG_YES<br />
M+<br />
Y+ 1<br />
4 M-<br />
U4650<br />
Y- 2<br />
PI3USB102ZLE<br />
7 D+<br />
TQFN<br />
6 D-<br />
CRITICAL<br />
8 OE*<br />
SEL 10<br />
2<br />
3 9<br />
GND<br />
SMC_DEBUG_NO<br />
R4652<br />
0<br />
1 2<br />
1<br />
R4650<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
USB_DEBUGPRT_EN_L<br />
SEL=0 Choose SMC<br />
SEL=1 Choose USB<br />
IN<br />
40B8<br />
76B3 19C3 BI<br />
76B3 19C3 BI<br />
USB_EXTB_N<br />
USB_EXTB_P<br />
PLACEMENT_NOTE=NEAR J4610<br />
CRITICAL<br />
CRITICAL<br />
We can add protection to 5V if we want, but leaving NC for now<br />
L4615<br />
FERR-220-OHM-2.5A<br />
Place L4600 and L4605 at connector pin<br />
1<br />
2 PP5V_S3_RTUSB_B_F<br />
MIN_LINE_WIDTH=0.5 mm<br />
0603<br />
MIN_NECK_WIDTH=0.5 mm<br />
VOLTAGE=5V<br />
1<br />
C4615<br />
0.01uF<br />
20%<br />
16V<br />
2<br />
CERM<br />
402<br />
CRITICAL<br />
PLACEMENT_NOTE=NEAR J4610<br />
CRITICAL<br />
L4610<br />
90-OHM<br />
DLP0NS<br />
SYM_VER-1<br />
4 3<br />
1 2<br />
D4600<br />
RCLAMP0502N<br />
SLP1210N6<br />
6 VBUS<br />
1 GND<br />
2 5 3 4<br />
NC<br />
IO<br />
NC<br />
IO<br />
D4610<br />
RCLAMP0502N<br />
SLP1210N6<br />
CRITICAL<br />
USB PORT B (BACK PORT)<br />
76B3<br />
76B3 CONN_USB_EXTB_N<br />
CONN_USB_EXTB_P<br />
J4610<br />
USB<br />
F-RT-TH-M97-4<br />
5<br />
6<br />
1<br />
2<br />
3<br />
4<br />
7<br />
8<br />
514-0638<br />
External USB Connectors<br />
SYNC_MASTER=YUAN.MA<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
SYNC_DATE=01/18/2008<br />
B<br />
A<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
38 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
37A8 7C3<br />
=PP5V_S3_IR<br />
1<br />
C4801<br />
0.1UF<br />
10%<br />
16V<br />
2<br />
X7R-CERM<br />
402<br />
D<br />
D<br />
BI<br />
BI<br />
14 P1_0/D+<br />
15 P1_1/D-<br />
18 P1_2/VREG<br />
20 P1_3/SSEL<br />
23 P1_4/SCLK<br />
24 P1_5/SMOSI<br />
25 P1_6/MISO<br />
26 P1_7<br />
21 P3_0<br />
22 P3_1<br />
VDD<br />
P0_0 7<br />
P0_1 6<br />
P0_2/INT0 5<br />
P0_3/INT1 4<br />
P0_4/INT2 3<br />
P0_5/TIO0 2<br />
P0_6/TIO1 1<br />
P0_7 32<br />
P2_0 9<br />
P2_1 8<br />
IN 6A7 37A7<br />
29<br />
NC<br />
30<br />
31<br />
12<br />
NC<br />
17<br />
19<br />
THRM_PAD<br />
VSS<br />
33<br />
13<br />
16<br />
76B3 19D3<br />
76B3 19D3<br />
DIFFERENTIAL_PAIR=USB2_IR<br />
DIFFERENTIAL_PAIR=USB2_IR<br />
USB_IR_P<br />
USB_IR_N<br />
1<br />
2<br />
IR_VREF_FILTER<br />
C4803<br />
1UF<br />
10%<br />
10V<br />
X5R<br />
402-1<br />
27<br />
28<br />
U4800<br />
CY7C63833<br />
QFN<br />
CRITICAL<br />
OMIT<br />
P/N 338S0375<br />
10<br />
11<br />
IR_RX_OUT_RC<br />
1<br />
C4804<br />
0.001UF<br />
10%<br />
50V<br />
2<br />
CERM<br />
402<br />
R4800<br />
100<br />
1<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
IR_RX_OUT<br />
C<br />
CYPRESS ’ENCORE II’ USB CONTROLLER<br />
C<br />
B<br />
B<br />
A<br />
SYNC_MASTER=YUAN.MA<br />
Front Flex Support<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=05/28/2008<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
39 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
NOTE: Unused pins have "SMC_Pxx" names. Unused<br />
pins designed as outputs can be left floating,<br />
those designated as inputs require pull-ups.<br />
D<br />
C<br />
41D5<br />
41D5<br />
66A4 24B8<br />
66B1<br />
20B7<br />
62C7<br />
20C7<br />
41D5<br />
76C3 42D5 18B3<br />
76C3 42D5 18B3<br />
76C3 42D3 18B3<br />
76C3 42D3 18B3<br />
76C3 42D5 18C3<br />
24D1<br />
76C3 24B1<br />
42D3 18B7<br />
43B5<br />
50B7<br />
41D5<br />
49A6<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
IN<br />
IN<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
OUT<br />
SMC_EXCARD_PWR_EN<br />
SMC_RSTGATE_L<br />
ALL_SYS_PWRGD<br />
RSMRST_PWRGD<br />
PM_RSMRST_L<br />
IMVP_VR_ON<br />
PM_PWRBTN_L<br />
41D5<br />
41D5<br />
ESTARLDO_EN<br />
SMC_P24<br />
SMC_P26<br />
LPC_AD<br />
LPC_AD<br />
LPC_AD<br />
LPC_AD<br />
LPC_FRAME_L<br />
SMC_LRESET_L<br />
LPC_CLK33M_SMC<br />
LPC_SERIRQ<br />
41D5 SMC_P41<br />
SMB_MGMT_DATA<br />
SMS_ONOFF_L<br />
SMC_GFX_THROTTLE_L<br />
SMC_SYS_KBDLED<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
(OC)<br />
NC<br />
NC<br />
B12<br />
A13<br />
A12<br />
B13<br />
D11<br />
C13<br />
C12<br />
D10<br />
D13<br />
E11<br />
D12<br />
F11<br />
E13<br />
E12<br />
F13<br />
E10<br />
A9<br />
D9<br />
C8<br />
B7<br />
A8<br />
D8<br />
D7<br />
D6<br />
D4<br />
A5<br />
B4<br />
A1<br />
C2<br />
B2<br />
C1<br />
C3<br />
P10<br />
P11<br />
P12<br />
P13<br />
P14<br />
P15<br />
P16<br />
P17<br />
P20<br />
P21<br />
P22<br />
P23<br />
P24<br />
P25<br />
P26<br />
P27<br />
P30<br />
P31<br />
P32<br />
P33<br />
P34<br />
P35<br />
P36<br />
P37<br />
P40<br />
P41<br />
P42<br />
P43<br />
P44<br />
P45<br />
P46<br />
P47<br />
U4900<br />
H8S2117<br />
LGA-HF<br />
(1 OF 3)<br />
OMIT<br />
P60<br />
P61<br />
P62<br />
P63<br />
P64<br />
P70<br />
P71<br />
P72<br />
P73<br />
P74<br />
P75<br />
P76<br />
P77<br />
P80<br />
P81<br />
P82<br />
P83<br />
P84<br />
P85<br />
P86<br />
P90<br />
P91<br />
P92<br />
P93<br />
P94<br />
P95<br />
P96<br />
P97<br />
L13<br />
K12<br />
K11<br />
J12<br />
K13<br />
J10<br />
P65<br />
P66 J11<br />
P67 H12<br />
N10<br />
M11<br />
L10<br />
N11<br />
N12<br />
M13<br />
N13<br />
L12<br />
A7<br />
B6<br />
C7<br />
D5<br />
A6<br />
B5<br />
C6<br />
J4<br />
G3<br />
H2<br />
G1<br />
H4<br />
G4<br />
F4<br />
F1<br />
NC<br />
NC<br />
NC<br />
NC<br />
(OC)<br />
SMC_PM_G2_EN<br />
SMC_ADAPTER_EN<br />
SMC_PROCHOT_3_3_L<br />
SMC_BIL_BUTTON_L<br />
SMC_CPU_ISENSE<br />
SMC_CPU_VSENSE<br />
SMC_GPU_ISENSE<br />
SMC_GPU_VSENSE<br />
SMC_DCIN_ISENSE<br />
SMC_PBUS_VSENSE<br />
SMC_BATT_ISENSE<br />
SMC_NB_MISC_ISENSE<br />
SMC_WAKE_SCI_L<br />
NC<br />
PM_CLKRUN_L<br />
LPC_PWRDWN_L<br />
SMC_TX_L<br />
SMC_RX_L<br />
(OC) SMB_MGMT_CLK<br />
SMC_ONOFF_L<br />
SMC_BC_ACOK<br />
SMC_BS_ALRT_L<br />
PM_SLP_S3_L<br />
PM_SLP_S4_L<br />
PM_SLP_S5_L<br />
PM_CLK32K_SUSCLK<br />
SMB_0_S0_DATA<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
BI<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
BI<br />
6C3 60C5 66D8<br />
20C7 32B7 35B5 41B2<br />
41D1<br />
6A7 58C4<br />
45B1<br />
44D6<br />
41B2<br />
41D5<br />
45B1<br />
44B4<br />
45A4<br />
41B2<br />
20C7<br />
18B7 42D5<br />
18C3 42D3<br />
38A8 40B8 41C2 42C5<br />
38A8 40B8 41B2 42C3<br />
43B5<br />
41A3 41C2 41C7 48C3<br />
41B2 41D5 58D2<br />
41B2<br />
6C3<br />
6C3<br />
41A2<br />
20C3<br />
20C3 41A2<br />
24B1 76A3<br />
43D6<br />
32B7 35A5 66D5<br />
66C8<br />
41C6 6C2 PP3V3_S5_AVREF_SMC<br />
41D8 41C7 41C3 41C1 7D1 =PP3V3_S5_SMC<br />
70D8<br />
C4902 1<br />
22UF<br />
20%<br />
6.3V<br />
CERM<br />
2<br />
805<br />
1<br />
C4903<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
NOTE: P94 and P95 are shorted, P95 could be spare.<br />
2<br />
R4999<br />
4.7<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
PLACEMENT_NOTE=PLACE R4999 CLOSE TO U4900 PINS M12<br />
PLACEMENT_NOTE=PLACE C4920 CLOSE TO U4900 PINS M12<br />
42D3 41D6<br />
1<br />
2<br />
PP3V3_S5_SMC_AVCC<br />
MIN_LINE_WIDTH=0.25 MM<br />
MIN_NECK_WIDTH=0.20 MM<br />
VOLTAGE=3.3V<br />
C4920<br />
1<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
2<br />
402<br />
IN<br />
C4904<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
1<br />
2<br />
SMC_RESET_L<br />
41A6 SMC_XTAL<br />
41A6 SMC_EXTAL<br />
C4905<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
1<br />
2<br />
C4906<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
D3<br />
A3<br />
A2<br />
M12<br />
AVCC<br />
RES*<br />
XTAL<br />
EXTAL<br />
D2<br />
L3<br />
B1<br />
M1<br />
H10<br />
VSS<br />
VCC<br />
U4900<br />
H8S2117<br />
F10<br />
B11<br />
C5<br />
E1<br />
LGA-HF<br />
(3 OF 3)<br />
OMIT<br />
VCL AVREF<br />
NC E5 NC<br />
MD1<br />
MD2<br />
NMI<br />
ETRST<br />
AVSS<br />
XW4900<br />
SM<br />
2<br />
L11<br />
1<br />
PLACEMENT_NOTE=PLACE C4907 CLOSE TO U4900 PIN E1<br />
SMC_VCL<br />
D1<br />
H1<br />
E3<br />
H3<br />
L9<br />
C4907<br />
1<br />
0.47UF<br />
10%<br />
6.3V<br />
CERM-X5R 2<br />
402<br />
1<br />
R4902<br />
10K<br />
5%<br />
1/16W<br />
2<br />
SMC_KBC_MDE<br />
MF-LF<br />
402<br />
GND_SMC_AVSS<br />
1<br />
R4909 1<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R4998<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
1<br />
R4901<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
SMC_MD1<br />
SMC_NMI<br />
SMC_TRST_L<br />
NO STUFF<br />
1<br />
R4903<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
IN<br />
IN<br />
IN<br />
41B6 44B5 44C6 44D6 45A1 45A4 45B2 45B5 45C5 45D7<br />
42C5<br />
42C3<br />
42D5<br />
D<br />
C<br />
42C5<br />
41C2<br />
40C5 38A8<br />
42C3 41B2 40C5 38A8<br />
43D6<br />
OUT<br />
IN<br />
BI<br />
SMC_TX_L<br />
SMC_RX_L<br />
SMB_0_S0_CLK<br />
(OC)<br />
G2<br />
F3<br />
E4<br />
P50<br />
P51<br />
P52<br />
B<br />
A<br />
(DEBUG_SW_1)<br />
(DEBUG_SW_2)<br />
24B3<br />
38A6<br />
27A5 26A5 20B3 20A4<br />
58D5<br />
20C7<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
SMC_PB3:<br />
(OC)<br />
(OC)<br />
(OC)<br />
(OC)<br />
(OC)<br />
(OC)<br />
NC<br />
20C7 OUT SMC_RUNTIME_SCI_L<br />
37C7 6B7 IN SMC_ODD_DETECT<br />
41C5 SMC_PB3 (See below)<br />
41B2 IN SMC_EXCARD_CP<br />
NC<br />
41C6 IN SMC_EXCARD_OC_L<br />
41B2 IN SMC_GFX_OVERTEMP_L<br />
47B5<br />
41D5<br />
41D5<br />
41D5<br />
47C5<br />
41B2<br />
41B2<br />
41B2<br />
50B4<br />
50B4<br />
50B4<br />
41C5<br />
41D5<br />
41D5<br />
41D5<br />
41C5<br />
41C2 SMC_PA0<br />
41C2 SMC_PA1<br />
PM_SYSRST_L<br />
USB_DEBUGPRT_EN_L<br />
MEM_EVENT_L<br />
41A2 SMC_PA5<br />
SYS_ONEWIRE<br />
PM_BATLOW_L<br />
SMC_FAN_0_CTL<br />
SMC_FAN_1_CTL<br />
SMC_FAN_2_CTL<br />
SMC_FAN_3_CTL<br />
SMC_FAN_0_TACH<br />
SMC_FAN_1_TACH<br />
SMC_FAN_2_TACH<br />
SMC_FAN_3_TACH<br />
SMS_X_AXIS<br />
SMS_Y_AXIS<br />
SMS_Z_AXIS<br />
SMC_ANALOG_ID<br />
SMC_NB_CORE_ISENSE<br />
SMC_NB_DDR_ISENSE<br />
ALS_LEFT<br />
ALS_RIGHT<br />
SMC_IG_THROTTLE_L for MG systems.<br />
Otherwise, TP/NC okay (was ISENSE_CAL_EN)<br />
N3<br />
N1<br />
M3<br />
M2<br />
N2<br />
L1<br />
K3<br />
L2<br />
B8<br />
C9<br />
B9<br />
A10<br />
C10<br />
B10<br />
C11<br />
A11<br />
G11<br />
G13<br />
F12<br />
H13<br />
G10<br />
G12<br />
H11<br />
J13<br />
M10<br />
N9<br />
K10<br />
L8<br />
M9<br />
N8<br />
K9<br />
L7<br />
PA0<br />
PA1<br />
PA2<br />
PA3<br />
PA4<br />
PA5<br />
PA6<br />
PA7<br />
PB0<br />
PB1<br />
PB2<br />
PB3<br />
PB4<br />
PB5<br />
PB6<br />
PB7<br />
PC0<br />
PC1<br />
PC2<br />
PC3<br />
PC4<br />
PC5<br />
PC6<br />
PC7<br />
PD0<br />
PD1<br />
PD2<br />
PD3<br />
PD4<br />
PD5<br />
PD6<br />
PD7<br />
U4900<br />
H8S2117<br />
LGA-HF<br />
(2 OF 3)<br />
OMIT<br />
PE0<br />
PE1<br />
PE2<br />
PE3<br />
PE4<br />
PF0<br />
PF1<br />
PF2<br />
PF3<br />
PF4<br />
PF5<br />
PF6<br />
PF7<br />
PG0<br />
PG1<br />
PG2<br />
PG3<br />
PG4<br />
PG5<br />
PG6<br />
PG7<br />
PH0<br />
PH1<br />
PH2<br />
PH3<br />
PH4<br />
PH5<br />
K1<br />
J3<br />
K2<br />
J1<br />
K4<br />
K5<br />
N5<br />
M6<br />
L5<br />
M5<br />
N4<br />
L4<br />
M4<br />
M8<br />
N7<br />
K8<br />
K7<br />
K6<br />
N6<br />
M7<br />
L6<br />
E2<br />
F2<br />
J2<br />
A4<br />
B3<br />
C4<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
(OC)<br />
(OC)<br />
(OC)<br />
(OC)<br />
(OC)<br />
(OC)<br />
NC<br />
NC<br />
SMC_CASE_OPEN<br />
SMC_TCK<br />
SMC_TDI<br />
SMC_TDO<br />
SMC_TMS<br />
SMC_SYS_LED<br />
SMC_LID<br />
SMC_MCP_SAFE_MODE<br />
=SMC_SMS_INT<br />
SMB_BSA_DATA<br />
SMB_BSA_CLK<br />
SMB_A_S3_DATA<br />
SMB_A_S3_CLK<br />
SMB_B_S0_DATA<br />
SMB_B_S0_CLK<br />
SMC_PROCHOT<br />
SMC_THRMTRIP<br />
SMC_PH2<br />
ALS_GAIN<br />
IN 41B2<br />
IN 41B2 42D3<br />
IN 41B2 42D3<br />
OUT 41B2 42D5<br />
IN 41B2 42D5<br />
OUT 41A8<br />
IN 41C2 48A5 58C1<br />
OUT 41C4<br />
IN 41C6<br />
BI 43C6<br />
BI 43C6<br />
BI 43D3<br />
BI 43D3<br />
BI 43C3<br />
BI 43C3<br />
OUT 41C2<br />
OUT 41C2<br />
41C2<br />
OUT 41C5<br />
NOTE: SMS Interrupt can be active high or low, rename net accordingly.<br />
If SMS interrupt is not used, pull up to SMC rail.<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
APPLE INC.<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SMC<br />
SHT<br />
SYNC_DATE=06/26/2008<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
40<br />
81<br />
B<br />
A<br />
8 7 6 5 4 3 2 1
TABLE_ALT_HEAD<br />
TABLE_ALT_ITEM<br />
8 7 6 5 4 3 2 1<br />
41A1 7C5<br />
SMC FSB to 3.3V Level Shifting<br />
=PP3V3_S0_SMC<br />
D<br />
C<br />
SILK_PART=SMC_RST<br />
7D1<br />
=PPVIN_S5_SMCVREF<br />
41C7 41C3 41C1 40D4 7D1<br />
2<br />
0<br />
SMC_MANUAL_RST_L<br />
NOSTUFF<br />
1 R5001<br />
5%<br />
1/10W<br />
MF-LF<br />
603<br />
=PP3V3_S5_SMC<br />
48B1<br />
48C3 41C2 41A3 40C5<br />
SMC Reset "Button" / Brownout Detect<br />
IN<br />
GND<br />
OUT<br />
CD<br />
NC<br />
SMC AVREF Supply<br />
1<br />
1 C5020<br />
0.47UF<br />
10%<br />
6.3V<br />
2<br />
CERM-X5R<br />
402<br />
C5001<br />
0.01UF<br />
10%<br />
16V<br />
CERM<br />
402<br />
C5000<br />
0.1uF<br />
20%<br />
10V<br />
CERM<br />
402<br />
41D8 41C3 41C1 40D4 7D1<br />
CRITICAL<br />
VR5020<br />
REF3333<br />
SOT23-3<br />
3<br />
1<br />
2<br />
SMC_TPAD_RST_L<br />
SMC_ONOFF_L<br />
1<br />
2<br />
NC<br />
2<br />
5<br />
4<br />
=PP3V3_S5_SMC<br />
C5025 1<br />
10uF<br />
20%<br />
6.3V<br />
2<br />
X5R<br />
603<br />
CRITICAL<br />
U5000<br />
NCP303LSN<br />
SOT23-5-HF<br />
1<br />
2<br />
GND<br />
3<br />
1<br />
2<br />
C5026<br />
0.01UF<br />
10%<br />
16V<br />
CERM<br />
402<br />
OUT<br />
IN<br />
5<br />
02<br />
3<br />
1<br />
2<br />
PP3V3_S5_AVREF_SMC<br />
MIN_LINE_WIDTH=0.4 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=3.3V<br />
GND_SMC_AVSS<br />
MIN_LINE_WIDTH=0.4 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=0V<br />
U5001<br />
SN74LVC1G02<br />
SOT553-5<br />
4<br />
1<br />
R5000<br />
1K<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
Q5032<br />
SSM6N15FEAPE<br />
SMC_TPAD_RST<br />
SMC_RESET_L<br />
SOT563<br />
5<br />
6C2 40D4<br />
G<br />
OUT<br />
D<br />
S<br />
3<br />
4<br />
40C3 42D3<br />
40C2 44B5 44C6 44D6 45A1 45A4 45B2 45B5 45C5 45D7<br />
40B8<br />
40B5<br />
OUT<br />
OUT<br />
40A8<br />
40A8<br />
40A8<br />
40C8<br />
40C8<br />
58D2 41B2 40C5<br />
40C8<br />
40C8<br />
40C8<br />
40A8<br />
40A8<br />
40A8<br />
40C5<br />
40D8<br />
40D8<br />
40B8<br />
40A5<br />
40A8<br />
40A8<br />
SMC_FAN_1_CTL<br />
SMC_FAN_2_CTL<br />
SMC_FAN_3_CTL<br />
SMC_GFX_THROTTLE_L<br />
ESTARLDO_EN<br />
SMC_BC_ACOK<br />
MAKE_BASE=TRUE<br />
SMC_P24<br />
SMC_P26<br />
SMC_P41<br />
SMC_NB_CORE_ISENSE<br />
SMC_NB_DDR_ISENSE<br />
ALS_LEFT<br />
SMC_GPU_VSENSE<br />
SMC_EXCARD_PWR_EN<br />
SMC_RSTGATE_L<br />
SMC_PB3<br />
ALS_GAIN<br />
SMC_ANALOG_ID<br />
ALS_RIGHT<br />
SMC_EXCARD_OC_L<br />
=SMC_SMS_INT<br />
R5095<br />
0<br />
1<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
MCP_SAFE_MODE SIGNAL TO SUPPORT ROM FAILURE OVERRIDE<br />
20C3<br />
MCP_SPKR<br />
NC_SMC_FAN_1_CTL<br />
MAKE_BASE=TRUE<br />
NC_SMC_FAN_2_CTL<br />
MAKE_BASE=TRUE<br />
NC_SMC_FAN_3_CTL<br />
MAKE_BASE=TRUE<br />
SMC_IG_THROTTLE_L<br />
MAKE_BASE=TRUE<br />
NC_ESTARLDO_EN<br />
MAKE_BASE=TRUE<br />
=CHGR_ACOK<br />
TP_SMC_P24<br />
MAKE_BASE=TRUE<br />
SMC_BMON_MUX_SEL<br />
MAKE_BASE=TRUE<br />
TP_SMC_P41<br />
MAKE_BASE=TRUE<br />
SMC_MCP_CORE_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_MCP_DDR_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_CPU_FSB_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_MCP_VSENSE<br />
MAKE_BASE=TRUE<br />
TP_SMC_EXCARD_PWR_EN<br />
MAKE_BASE=TRUE<br />
TP_SMC_RSTGATE_L<br />
MAKE_BASE=TRUE<br />
NC_SMC_PB3<br />
MAKE_BASE=TRUE<br />
NC_ALS_GAIN<br />
MAKE_BASE=TRUE<br />
NC_SMC_ANALOG_ID<br />
MAKE_BASE=TRUE<br />
NC_ALS_RIGHT<br />
MAKE_BASE=TRUE<br />
SMS_INT_L<br />
MAKE_BASE=TRUE<br />
RADAR 5925345<br />
R5011<br />
0<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
EXCARD_OC_L<br />
SMC_MCP_SAFE_MODE<br />
20A4 20B3<br />
59C5<br />
45A5<br />
45D7<br />
45C5<br />
45B5<br />
44D6<br />
IN<br />
19C2<br />
73C3 62C8 13B6 9C5<br />
IN<br />
40B5<br />
TO CPU<br />
BI<br />
73B3 13B7 9C6<br />
1<br />
R5010<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
OUT<br />
CPU_PROCHOT_L<br />
=PP3V3_S5_SMC<br />
PM_THRMTRIP_L<br />
IN<br />
7D1 40D4 41C1 41C7<br />
41D8<br />
6 D<br />
1 S<br />
3 D<br />
4<br />
R5062<br />
3.3K<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
S<br />
Q5059<br />
G 2<br />
Q5059<br />
SSM6N15FEAPE<br />
SOT563<br />
G<br />
5<br />
CPU_PROCHOT_L_R<br />
SSM6N15FEAPE<br />
SOT563<br />
SMC_PROCHOT<br />
SMC_THRMTRIP<br />
40B8<br />
40B8<br />
48C3 41C7 41A3 40C5<br />
58C1 48A5 40B5<br />
40A5<br />
42C5 40C5 40B8 38A8<br />
42C3 40C5 40B8 38A8<br />
IN<br />
SMC_PA0<br />
SMC_PA1<br />
IN<br />
5<br />
40A5<br />
SMC_ONOFF_L<br />
SMC_LID<br />
SMC_PH2<br />
SMC_TX_L<br />
SMC_RX_L<br />
40A5<br />
1<br />
R5061<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
3<br />
CPU_PROCHOT_BUF<br />
Q5060<br />
DMB53D0UV<br />
SOT-563<br />
4<br />
R5091<br />
R5092<br />
R5070<br />
R5071<br />
R5072<br />
R5073<br />
R5074<br />
2 G<br />
100K<br />
100K<br />
10K<br />
100K<br />
10K<br />
10K<br />
100K<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
TO SMC<br />
SMC_PROCHOT_3_3_L<br />
OUT<br />
1<br />
1<br />
1<br />
1<br />
1<br />
1<br />
1<br />
1<br />
R5060<br />
6<br />
D<br />
S<br />
1<br />
41D8 41C7 41C3 40D4<br />
Q5060<br />
DMB53D0UV<br />
SOT-563<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
7D1<br />
5% 1/16W<br />
5% 1/16W MF-LF 402<br />
5% 1/16W MF-LF 402<br />
5% 1/16W MF-LF 402<br />
5% 1/16W MF-LF<br />
5%<br />
=PP3V3_S5_SMC<br />
MF-LF<br />
5% 1/16W MF-LF<br />
1/16W MF-LF<br />
402<br />
402<br />
402<br />
402<br />
40D5<br />
D<br />
C<br />
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:<br />
PART NUMBER<br />
353S1381<br />
353S1912<br />
ALL<br />
ISL60002-33, INTERSIL<br />
42D5 40B5 SMC_TMS<br />
42D5 40B5 SMC_TDO<br />
42D3 40B5 SMC_TDI<br />
42D3 40B5 SMC_TCK<br />
58D2 41D5 40C5 SMC_BC_ACOK<br />
40B8 SMC_GFX_OVERTEMP_L<br />
R5077<br />
R5078<br />
R5079<br />
R5080<br />
R5087<br />
R5050<br />
10K 1<br />
2<br />
10K 1<br />
2<br />
10K 1 2<br />
10K 1 2<br />
470K 1<br />
2<br />
10K 1 2<br />
5%<br />
5%<br />
5%<br />
1/16W MF-LF<br />
1/16W<br />
MF-LF<br />
402<br />
402<br />
1/16W MF-LF 402<br />
5% 1/16W MF-LF 402<br />
5%<br />
5%<br />
1/16W<br />
1/16W<br />
MF-LF 402<br />
MF-LF<br />
402<br />
B<br />
40C5<br />
SMC_BS_ALRT_L<br />
R5076<br />
100K<br />
1 2<br />
5% 1/16W<br />
MF-LF<br />
402<br />
B<br />
A<br />
7C3<br />
=PP5V_S3_SYSLED<br />
40B5<br />
IN<br />
System (Sleep) LED Circuit<br />
1<br />
R5031<br />
523<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
R5032<br />
1.47K<br />
1%<br />
1/16W<br />
MF-LF<br />
402 2<br />
SMC_SYS_LED<br />
1<br />
R5030<br />
20<br />
1%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
SYS_LED_ILIM<br />
SYS_LED_L_VDIV<br />
SYS_LED_L<br />
Q5032<br />
SSM6N15FEAPE<br />
SOT563<br />
2<br />
G<br />
D<br />
S<br />
6<br />
1<br />
1<br />
2<br />
3<br />
CRITICAL<br />
SOD<br />
2SA2154MFV-YAE<br />
Q5030<br />
SYS_LED_ANODE<br />
OUT<br />
37A8<br />
40C3 SMC_XTAL<br />
40C3 SMC_EXTAL<br />
SMC Crystal Circuit<br />
CRITICAL<br />
1<br />
Y5010<br />
20.00MHZ<br />
5X3.2-SM<br />
2<br />
C5010<br />
15pF<br />
1 2<br />
C5011<br />
15pF<br />
1<br />
5%<br />
50V<br />
CERM<br />
402<br />
5%<br />
50V<br />
CERM<br />
402<br />
2<br />
SILK_PART=PWR_BTN<br />
Debug Power "Button"<br />
1<br />
R5015<br />
2<br />
NOSTUFF<br />
0<br />
SMC_ONOFF_L<br />
5%<br />
1/10W<br />
MF-LF<br />
603<br />
1<br />
R5016<br />
2<br />
NOSTUFF<br />
0<br />
OUT<br />
PLACE R5015,R5001 ON BOTTOM SIDE<br />
PLACE R5016 ON TOP SIDE<br />
5%<br />
1/10W<br />
MF-LF<br />
603<br />
SILK_PART=PWR_BTN<br />
40C5 41C2 41C7 48C3<br />
40A8 SMC_FAN_1_TACH<br />
40A8 SMC_FAN_2_TACH<br />
40A8 SMC_FAN_3_TACH<br />
40C5 SMC_GPU_ISENSE<br />
40C5 SMC_NB_MISC_ISENSE<br />
40D5 35B5 32B7 20C7 SMC_ADAPTER_EN<br />
40B5 SMC_CASE_OPEN<br />
40B8 SMC_EXCARD_CP<br />
40C5 PM_SLP_S5_L<br />
66C8 40C5 20C3 6C3 PM_SLP_S4_L<br />
40B8 SMC_PA5<br />
R5051 10K 1<br />
2<br />
R5052<br />
R5053<br />
R5054<br />
R5055<br />
R5085<br />
R5086<br />
R5088<br />
R5090<br />
R5089<br />
10K<br />
10K<br />
10K<br />
10K<br />
100K<br />
10K<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
1<br />
1<br />
10K 1<br />
2<br />
10K<br />
10K<br />
SYNC_MASTER=YUAN.MA<br />
1<br />
1<br />
1<br />
1<br />
1<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
2<br />
2<br />
1 2<br />
41D3 7C5<br />
2<br />
2<br />
2<br />
2<br />
2<br />
5%<br />
5%<br />
5%<br />
5%<br />
5%<br />
5% 1/16W MF-LF 402<br />
5%<br />
1/16W MF-LF 402<br />
5% 1/16W MF-LF<br />
5%<br />
SMC Support<br />
1/16W<br />
1/16W<br />
1/16W<br />
1/16W<br />
402<br />
1/16W MF-LF 402<br />
1/16W<br />
MF-LF<br />
MF-LF<br />
MF-LF<br />
MF-LF<br />
402<br />
402<br />
402<br />
5% 1/16W MF-LF 402<br />
=PP3V3_S0_SMC<br />
MF-LF 402<br />
402<br />
SYNC_DATE=05/28/2008<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
41 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
LPC+SPI Connector<br />
D<br />
Alternate SPI ROM Support<br />
42C8 42C7 7D1<br />
76C3 40C8 18B3<br />
76C3 40C8 18B3<br />
76A3 42C5<br />
76A3 42B5<br />
76C3 40C8 18C3<br />
40C5 18B7<br />
41B2 40B5<br />
40C1<br />
40C1<br />
41C2 40C5 40B8 38A8<br />
7D5<br />
=PP3V3_S5_LPCPLUS<br />
=PP5V_S0_LPCPLUS<br />
BI<br />
BI<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
LPC_AD<br />
LPC_AD<br />
SPI_ALT_MOSI<br />
SPI_ALT_MISO<br />
LPC_FRAME_L<br />
PM_CLKRUN_L<br />
SMC_TMS<br />
DEBUG_RESET_L<br />
SMC_TDO<br />
SMC_TRST_L<br />
SMC_MD1<br />
SMC_TX_L<br />
CRITICAL<br />
LPCPLUS<br />
J5100<br />
55909-0374<br />
M-ST-SM<br />
31 32<br />
1 2<br />
3 4<br />
5 6<br />
7 8<br />
9 10<br />
11 12<br />
13 14<br />
15 16<br />
17 18<br />
19 20<br />
21 22<br />
23 24<br />
25 26<br />
27 28<br />
29 30<br />
LPC_CLK33M_LPCPLUS<br />
LPC_AD<br />
LPC_AD<br />
SPIROM_USE_<strong>MLB</strong><br />
SPI_ALT_CLK<br />
SPI_ALT_CS_L<br />
LPC_SERIRQ<br />
LPC_PWRDWN_L<br />
SMC_TDI<br />
SMC_TCK<br />
SMC_RESET_L<br />
SMC_NMI<br />
SMC_RX_L<br />
LPCPLUS_GPIO<br />
IN 24B1 76C3<br />
BI 18B3 40C8 76C3<br />
BI 18B3 40C8 76C3<br />
OUT 42B7<br />
IN 42C5 76A3<br />
IN 42B5<br />
BI<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
18B7 40C8<br />
18C3 40C5<br />
40B5 41B2<br />
40B5 41B2<br />
40C3 41D6<br />
40C1<br />
38A8 40B8 40C5 41B2<br />
17B7<br />
D<br />
C<br />
76A3 42A5 20B3<br />
IN<br />
SPI_CLK_R<br />
R5191 1<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402 2<br />
51C6 42B5 7A3<br />
76A3 42A5 20B3<br />
42D5 42C8 7D1 =PP3V3_S5_LPCPLUS<br />
=PP3V3_S5_ROM<br />
IN<br />
R5190 1<br />
10K 5%<br />
1/16W<br />
MF-LF<br />
402 2<br />
SPI_MOSI_R<br />
LPCPLUS<br />
1<br />
2<br />
10 SEL<br />
9<br />
VCC<br />
Y+<br />
Y-<br />
U5110<br />
M+<br />
M-<br />
5<br />
4<br />
PI3USB102ZLE<br />
TQFN D+ 7<br />
D-<br />
CRITICAL<br />
6<br />
GND<br />
OE*<br />
8<br />
LPCPLUS<br />
C5114<br />
1<br />
0.1UF<br />
20%<br />
2 10V<br />
CERM<br />
402<br />
SPI_ALT_CLK<br />
SPI_ALT_MOSI<br />
SPI_CLK_MUX<br />
SPI_MOSI_MUX<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
42D3 76A3<br />
42D5 76A3<br />
42A8 51C6<br />
42A8 51C3<br />
33 34<br />
516S0573<br />
C<br />
3<br />
SEL HIGH OUTPUTS TO D (ON BOARD ROM)<br />
SEL LOW OUTPUTS TO M (FRANKCARD ROM)<br />
B<br />
42D5 42C7 7D1<br />
20C7<br />
BI<br />
=PP3V3_S5_LPCPLUS<br />
1<br />
R5140<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
76A3 42A5 20B3<br />
76A3 20B3<br />
=SPI_CS1_R_L_USE_<strong>MLB</strong><br />
OUT<br />
IN<br />
SPI_MISO<br />
SPI_CS0_R_L<br />
SPIROM_USE_<strong>MLB</strong><br />
MAKE_BASE=TRUE<br />
LPCPLUS<br />
LPCPLUS_NOT<br />
9<br />
VCC<br />
1 Y+<br />
M+ 5<br />
2 Y-<br />
M- 4<br />
U5120<br />
PI3USB102ZLE<br />
TQFN<br />
D+<br />
D-<br />
7<br />
6<br />
CRITICAL<br />
10 SEL<br />
OE* 8<br />
R5146<br />
0<br />
1 2<br />
GND<br />
3<br />
LPCPLUS<br />
C5124<br />
1<br />
0.1UF<br />
20%<br />
10V<br />
2 CERM 402<br />
5% PLACEMENT_NOTE=PLACE NEXT TO U1400<br />
1/16W<br />
MF-LF<br />
402<br />
SPI_ALT_MISO<br />
IN 42D5 76A3<br />
Pull-up on debug card<br />
SPI_ALT_CS_L<br />
42D3<br />
SPI_MISO_MUX<br />
R5144<br />
1<br />
20K 5%<br />
1/16W<br />
MF-LF<br />
402 2<br />
OUT<br />
IN 42A8 51C3<br />
SPI_<strong>MLB</strong>_CS_L<br />
OUT 51C6<br />
=PP3V3_S5_ROM 7A3 42C7 51C6<br />
B<br />
SPI MUX BYPASS<br />
A<br />
51C6 42C5 OUT<br />
51C3 42C5 OUT<br />
51C3 42B5 IN<br />
SPI_CLK_MUX<br />
SPI_MOSI_MUX<br />
SPI_MISO_MUX<br />
LPCPLUS_NOT<br />
R5156<br />
0<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
LPCPLUS_NOT<br />
R5158<br />
0<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
LPCPLUS_NOT<br />
R5157<br />
0<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
SPI_CLK_R<br />
SPI_MOSI_R<br />
SPI_MISO<br />
IN 20B3 42C8 76A3<br />
IN 20B3 42C7 76A3<br />
OUT 20B3 42B7 76A3<br />
LPC+SPI Debug Connector<br />
SYNC_MASTER=CHANGZHANG<br />
NOTICE OF PROPRIETARY PROPERTY<br />
SYNC_DATE=05/09/2008<br />
A<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
42 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
MCP79 SMBUS "0" CONNECTIONS<br />
7C5 =PP3V3_S0_SMBUS_MCP_0<br />
SMC "0" SMBus Connections<br />
7C5 =PP3V3_S0_SMBUS_SMC_0_S0<br />
SMC "A" SMBus Connections<br />
NOTE: SMC RMT bus remains powered and may be active in S3 state<br />
7D3 =PP3V3_S3_SMBUS_SMC_A_S3<br />
D<br />
MCP79<br />
U1400<br />
(MASTER)<br />
R5200 1<br />
1K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
R5201<br />
1K<br />
5%<br />
1/16W<br />
2<br />
MF-LF<br />
402<br />
SO-DIMM "A"<br />
J3100<br />
(Write: 0xA0 Read: 0xA1)<br />
SMC<br />
U4900<br />
(MASTER)<br />
R5250<br />
4.7K<br />
5%<br />
1/16W<br />
1<br />
MF-LF<br />
402 2<br />
R5251<br />
4.7K<br />
1<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
MCP Temp<br />
EMC1403-5: U5535<br />
(Write: 0x98 Read: 0x99)<br />
SMC<br />
U4900<br />
(MASTER)<br />
R5270<br />
1<br />
1K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
R5271<br />
1K<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
TRACKPAD<br />
J5800<br />
(Write: 0x90 Read: 0x91)<br />
20C3 12B6<br />
76B3<br />
20C3 12B6<br />
76B3<br />
SMBUS_MCP_0_CLK<br />
MAKE_BASE=TRUE<br />
SMBUS_MCP_0_DATA<br />
MAKE_BASE=TRUE<br />
=I2C_SODIMMA_SCL<br />
=I2C_SODIMMA_SDA<br />
26A5<br />
26A5<br />
40B8 SMB_0_S0_CLK<br />
40C5 SMB_0_S0_DATA<br />
79D3<br />
SMBUS_SMC_0_S0_SCL<br />
MAKE_BASE=TRUE<br />
=I2C_MCPTHMSNS_SCL<br />
SMBUS_SMC_0_S0_SDA<br />
=I2C_MCPTHMSNS_SDA<br />
79D3 46B3 40A5<br />
MAKE_BASE=TRUE<br />
46B3<br />
40A5 SMB_A_S3_CLK<br />
SMB_A_S3_DATA<br />
79D3 6D5 6C5<br />
79D3 6D5 6C5<br />
SMBUS_SMC_A_S3_SCL<br />
MAKE_BASE=TRUE<br />
SMBUS_SMC_A_S3_SDA<br />
MAKE_BASE=TRUE<br />
=I2C_TPAD_SCL<br />
=I2C_TPAD_SDA<br />
49C1<br />
49C1<br />
SO-DIMM "B"<br />
J3200<br />
(Write: 0xA2 Read: 0xA3)<br />
ALS<br />
J3401<br />
(Write: 0x52 Read: 0x53)<br />
=I2C_SODIMMB_SCL<br />
27A5<br />
=I2C_ALS_SCL<br />
29B6<br />
=I2C_SODIMMB_SDA<br />
27A5<br />
=I2C_ALS_SDA<br />
29B6<br />
C<br />
SMC "Battery A" SMBus Connections<br />
7D1 =PP3V42_G3H_SMBUS_SMC_BSA<br />
SMC "B" SMBus Connections<br />
7C5 =PP3V3_S0_SMBUS_SMC_B_S0<br />
C<br />
MCP79 SMBUS "1" CONNECTIONS<br />
7C5 =PP3V3_S0_SMBUS_MCP_1<br />
SMC<br />
U4900<br />
(MASTER)<br />
40B5 SMB_BSA_CLK<br />
40B5 SMB_BSA_DATA<br />
79D3 6A7<br />
79D3 6A7<br />
SMBUS_SMC_BSA_SCL<br />
MAKE_BASE=TRUE<br />
SMBUS_SMC_BSA_SDA<br />
MAKE_BASE=TRUE<br />
R5280<br />
2.0K<br />
1<br />
5%<br />
1/16W<br />
MF-LF<br />
402 2<br />
R5281<br />
2.0K<br />
1<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
BATTERY & BIL<br />
J6950 & J6955<br />
(See Table)<br />
=SMBUS_BATT_SCL<br />
58A6 58C3<br />
=SMBUS_BATT_SDA<br />
58A6 58C3<br />
SMC<br />
U4900<br />
(MASTER)<br />
40A5 SMB_B_S0_CLK<br />
40A5 SMB_B_S0_DATA<br />
79D3<br />
79D3<br />
SMBUS_SMC_B_S0_SCL<br />
MAKE_BASE=TRUE<br />
SMBUS_SMC_B_S0_SDA<br />
MAKE_BASE=TRUE<br />
R5260 1<br />
4.7K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
R5261<br />
4.7K<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
CPU Temp<br />
EMC1403-5: U5515<br />
(Write: 0x98 Read: 0x99)<br />
=I2C_CPUTHMSNS_SCL<br />
=I2C_CPUTHMSNS_SDA<br />
46D3<br />
46D3<br />
MCP79<br />
U1400<br />
(MASTER?)<br />
76B3 20C3 SMBUS_MCP_1_CLK<br />
MAKE_BASE=TRUE<br />
76B3 20C3 SMBUS_MCP_1_DATA<br />
MAKE_BASE=TRUE<br />
R5230<br />
2.0K<br />
1<br />
5%<br />
1/16W<br />
MF-LF<br />
402 2<br />
1<br />
R5231<br />
2.0K<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
Mikey<br />
U6860<br />
(WRITE: 0X72 READ: 0X73)<br />
=I2C_MIKEY_SCL<br />
=I2C_MIKEY_SDA<br />
57D3<br />
57D3<br />
Battery<br />
Battery Manager - (Write: 0x16 Read: 0x17)<br />
Battery LED Driver - (Write: 0x36 Read: 0x37)<br />
Battery Temp - (Write: 0x90 Read: 0x91)<br />
Battery Charger<br />
ISL6258A - U7000<br />
(Write: 0x12 Read: 0x13)<br />
=SMBUS_CHGR_SCL<br />
59C6<br />
=SMBUS_CHGR_SDA<br />
59C6<br />
B<br />
LED BACKLIGHT<br />
U9701<br />
(WRITE: ?? READ: 0X??)<br />
=I2C_BKL_1_SCL<br />
71B7<br />
=I2C_BKL_1_SDA<br />
71B7<br />
SMC "Management" SMBus Connections<br />
The bus formerly known as "Battery B"<br />
7D3 =PP3V3_S3_SMBUS_SMC_MGMT<br />
B<br />
SMC<br />
U4900<br />
(MASTER)<br />
R5290 1<br />
4.7K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
R5291<br />
4.7K<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
Vref DACs<br />
U2900<br />
(Write: 0x98 Read: 0x99)<br />
40C5 SMB_MGMT_CLK<br />
40C8 SMB_MGMT_DATA<br />
79D3<br />
79D3<br />
SMBUS_SMC_MGMT_SCL<br />
MAKE_BASE=TRUE<br />
SMBUS_SMC_MGMT_SDA<br />
MAKE_BASE=TRUE<br />
=I2C_VREFDACS_SCL<br />
=I2C_VREFDACS_SDA<br />
25C7<br />
25C7<br />
Margin Control<br />
U2901<br />
(Write: 0x30 Read: 0x31)<br />
=I2C_PCA9557D_SCL<br />
=I2C_PCA9557D_SDA<br />
25A8<br />
25A8<br />
A<br />
SYNC_MASTER=BEN<br />
<strong>K24</strong> SMBUS CONNECTIONS<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=04/21/2008<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
43<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
CPU Voltage Sense / Filter<br />
D<br />
7D7<br />
=PPVCORE_S0_CPU_VSENSE<br />
XW5309<br />
SM<br />
PLACEMENT_NOTE=Place near U1000 center<br />
1<br />
2<br />
CPUVSENSE_IN<br />
R5309<br />
4.53K<br />
1<br />
2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
Place RC close to SMC<br />
2<br />
SMC_CPU_VSENSE<br />
1<br />
C5309<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
402<br />
GND_SMC_AVSS<br />
OUT<br />
40C5<br />
40C2 41B6 44B5 44C6 45A1 45A4 45B2 45B5 45C5 45D7<br />
D<br />
MCP Voltage Sense / Filter<br />
7C6 =PPVCORE_S0_MCP_VSENSE<br />
XW5359<br />
SM<br />
1<br />
2 MCPVSENSE_IN<br />
PLACEMENT_NOTE=Place near U1400 center<br />
R5359<br />
4.53K<br />
1 2 SMC_MCP_VSENSE<br />
1%<br />
1/16W<br />
MF-LF<br />
1<br />
C5359<br />
402<br />
0.22UF<br />
20%<br />
6.3V<br />
2<br />
X5R<br />
402<br />
GND_SMC_AVSS<br />
Place RC close to SMC<br />
OUT 41D4<br />
40C2 41B6 44B5 44D6 45A1 45A4 45B2 45B5 45C5 45D7<br />
C<br />
C<br />
PBUS VOLTAGE SENSE ENABLE & FILTER<br />
Q5315<br />
NTUD3127CXXG<br />
SOT-963<br />
N-CHANNEL<br />
6<br />
PBUSVSENS_EN_L<br />
D<br />
B<br />
66C1 IN =PBUSVSENS_EN<br />
Enables PBUS VSense<br />
divider when high.<br />
7C1 =PPBUS_G3HRS5<br />
R5315<br />
1<br />
100K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
PBUSVSENS_EN_L_DIV<br />
2<br />
1<br />
5<br />
4<br />
G<br />
S<br />
D<br />
G<br />
S<br />
P-CHANNEL<br />
3<br />
R5316 1<br />
100K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
PPBUS_G3HRS5_VSENSE<br />
MIN_LINE_WIDTH=0.20 mm<br />
MIN_NECK_WIDTH=0.20 mm<br />
VOLTAGE=18.5V<br />
R5385<br />
1<br />
27.4K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R5386<br />
1<br />
5.49K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
RTHEVENIN = 4573 OHMS<br />
SMC_PBUS_VSENSE<br />
OUT 40C5<br />
1<br />
C5385<br />
0.22UF<br />
20%<br />
6.3V<br />
2 X5R<br />
402<br />
GND_SMC_AVSS 40C2 41B6 44C6 44D6 45A1 45A4 45B2 45B5 45C5 45D7<br />
B<br />
Place RC close to SMC<br />
A<br />
SYNC_MASTER=YUNWU<br />
VOLTAGE SENSING<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=02/04/2008<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
44 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
MCP VCore Current Sense Filter<br />
R5416<br />
D<br />
63D8<br />
MCPCORES0_IMON<br />
1 4.53K 2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
C5472<br />
0.22UF<br />
20%<br />
6.3V<br />
2<br />
X5R<br />
402<br />
Place RC close to SMC<br />
SMC_MCP_CORE_ISENSE<br />
GND_SMC_AVSS<br />
OUT 41D4<br />
40C2 41B6 44B5 44C6 44D6 45A1 45A4 45B2 45B5 45C5<br />
D<br />
MCP MEM VDD Current Sense<br />
7B5<br />
=PP3V3_S0_MCPDDRISNS<br />
67D1<br />
IN<br />
P1V5_S0_KELVIN<br />
C<br />
67D1<br />
IN<br />
P1V5_S0_SENSE<br />
R5410<br />
0<br />
1<br />
5%<br />
1/16W<br />
2 402<br />
MF-LF<br />
C5434<br />
0.1UF<br />
10%<br />
P1V5_S0_SENSE_E<br />
16V<br />
X5R<br />
402<br />
Q5401<br />
2 2SA2154MFV-YAE<br />
CRITICAL SOD<br />
1 P1V5_S0_SENSE_B<br />
3<br />
1<br />
R5412<br />
118<br />
1%<br />
1/16W<br />
MF-LF<br />
2 402<br />
Gain: 50x<br />
R5411<br />
0<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
3<br />
U5400<br />
5 OPA348<br />
SC70-5<br />
4<br />
2<br />
P1V5_S0_SENSE_AMP<br />
P1V5_S0_SENSE_C<br />
C5400<br />
0.1uF<br />
20%<br />
10V<br />
CERM<br />
402<br />
MCP MEM VDD Current Sense Filter<br />
R5417<br />
4.53K<br />
1 2<br />
SMC_MCP_DDR_ISENSE<br />
OUT 41D4<br />
1%<br />
1/16W<br />
MF-LF<br />
1<br />
C5435<br />
402<br />
0.22UF<br />
20%<br />
6.3V<br />
2 X5R<br />
402<br />
GND_SMC_AVSS 40C2 41B6 44B5 44C6 44D6 45A1 45A4 45B2 45B5 45D7<br />
Place RC close to SMC<br />
C<br />
CPU 1.05V AND CPU VCORE HIGH SIDE CURRENT SENSE<br />
7C1<br />
IN<br />
R5492<br />
0.01<br />
0.5%<br />
CRITICAL<br />
1W<br />
MF<br />
0612-1<br />
=PPCPUVCORE_VTT_ISNS_R 1 2 =PPCPUVCORE_VTT_ISNS OUT<br />
3 4<br />
7C5<br />
80D3 ISNS_CPUVTT_N<br />
80D3 ISNS_CPUVTT_P<br />
=PP3V3_S0_CPUVTTISNS<br />
C5417<br />
1<br />
0.1uF<br />
20%<br />
10V<br />
2 CERM<br />
402<br />
7C2<br />
5 IN-<br />
4 IN+<br />
3<br />
V+<br />
U5402<br />
INA213<br />
SC70<br />
GND<br />
2<br />
OUT<br />
6<br />
REF 1<br />
CPUVTT_IOUT<br />
R5418<br />
4.53K<br />
1 2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
C5436<br />
0.22UF<br />
20%<br />
6.3V<br />
2 X5R<br />
402<br />
SMC_CPU_FSB_ISENSE<br />
OUT<br />
41D4<br />
CPU VCore Load Side Current Sense / Filter<br />
R5471<br />
6.19K<br />
62C7 IMVP6_IMON<br />
1<br />
2<br />
IN<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
R5480<br />
17.4K<br />
Place RC close to SMC<br />
1<br />
1%<br />
1/16W<br />
MF-LF<br />
402 2<br />
SMC_CPU_ISENSE<br />
OUT 40C5<br />
1<br />
C5470<br />
0.22UF<br />
20%<br />
6.3V<br />
2<br />
X5R<br />
402<br />
GND_SMC_AVSS<br />
40C2 41B6 44B5 44C6 44D6 45A1 45A4 45B5 45C5 45D7<br />
B<br />
GND_SMC_AVSS<br />
Place RC close to SMC<br />
40C2 41B6 44B5 44C6 44D6 45A1 45A4 45B2 45C5 45D7<br />
B<br />
BMON CURRENT SENSE<br />
DC-IN (AMON) CURRENT SENSE<br />
A<br />
80D3 59B3<br />
80D3 59B3<br />
OUT<br />
IN<br />
REGULATOR SIDE<br />
LOAD SIDE<br />
NOTE: MONITORING CURRENT FROM<br />
BATTERY TO PBUS (BATTERY DISCHARGE)<br />
ACROSS R7008<br />
7D1<br />
CHGR_CSO_R_P<br />
CHGR_CSO_R_N<br />
=PP3V42_G3H_BMON_ISNS<br />
BMON_ENG<br />
1<br />
C5418<br />
0.1uF<br />
20%<br />
10V<br />
2 CERM<br />
402<br />
V+<br />
BMON_ENG<br />
5 IN-<br />
4 IN+<br />
3<br />
U5403<br />
INA213<br />
SC70 OUT 6<br />
GND<br />
2<br />
REF 1<br />
BMON_INA_OUT<br />
59C5<br />
IN<br />
CHGR_BMON<br />
PLACE U5413, R5423, R5431, C5459 NEAR SMC (U4900)<br />
NC7SB3157P6XG<br />
1 B1<br />
SC70<br />
SEL 6<br />
2 GND<br />
VCC 5<br />
0<br />
3<br />
4<br />
B0 BMON_ENG A<br />
VER 1<br />
BMON_PROD<br />
R5431<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
U5413<br />
1<br />
SMC_BMON_MUX_SEL<br />
1 BMON_ENG<br />
R5423<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
IN<br />
BMON_AMUX_OUT<br />
41D4<br />
R5401<br />
4.53K<br />
1 2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
BMON_ENG<br />
1<br />
C5459<br />
0.1uF<br />
20%<br />
10V<br />
2 CERM<br />
402<br />
1<br />
2<br />
SMC_BATT_ISENSE<br />
C5490<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
402<br />
OUT<br />
PLACE R5491 AND C5390 CLOSE TO SMC<br />
40C5<br />
GND_SMC_AVSS 40C2 41B6 44B5 44C6 44D6 45A1 45B2 45B5 45C5<br />
45D7<br />
IN<br />
CHGR_AMON<br />
R5481<br />
4.53K<br />
1 2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
SMC_DCIN_ISENSE<br />
C5487<br />
1<br />
0.22UF<br />
20%<br />
6.3V<br />
2 X5R<br />
402<br />
GND_SMC_AVSS<br />
SYNC_MASTER=YUNWU<br />
OUT<br />
40C5<br />
40C2 41B6 44B5 44C6 44D6 45A4 45B2 45B5 45C5 45D7<br />
Current Sensing<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
SYNC_DATE=12/17/2008<br />
A<br />
II NOT TO REPRODUCE OR COPY IT<br />
INA213 has gain of 50V/V<br />
PLACE U5403 AND C5418 NEAR R7008<br />
For engineering, stuff U5313 and unstuff R5330<br />
For production, stuff R5330 and unstuff U5313<br />
APPLE INC.<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
45<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
7C5<br />
=PP3V3_S0_CPUTHMSNS<br />
80D3 9C6<br />
CPU T-Diode Thermal Sensor<br />
BI<br />
R5515<br />
47<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
CPU_THERMD_P<br />
SIGNAL_MODOL=EMPTY<br />
C5521<br />
1<br />
DETECT CPU DIE TEMPERATURE<br />
0.0022uF<br />
10%<br />
50V<br />
CERM 2<br />
402<br />
80D3 9C6 BI CPU_THERMD_N<br />
PP3V3_S0_CPUTHMSNS_R<br />
MIN_LINE_WIDTH=0.25 mm<br />
MIN_NECK_WIDTH=0.25 mm<br />
VOLTAGE=3.3V<br />
4 DP2/DN3<br />
5<br />
DN2/DP3<br />
GND<br />
6<br />
INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE<br />
1<br />
VDD<br />
U5515<br />
EMC1413<br />
DFN<br />
2<br />
DP1 THERM*/ADDR<br />
7<br />
3 CRITICAL<br />
DN1<br />
ALERT*<br />
8<br />
SMDATA<br />
SMCLK<br />
THRM_PAD<br />
11<br />
9<br />
10<br />
1<br />
C5515<br />
0.1uF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
CPUTHMSNS_THERM_L<br />
CPUTHMSNS_ALERT_L<br />
=I2C_CPUTHMSNS_SDA<br />
=I2C_CPUTHMSNS_SCL<br />
1<br />
R5516<br />
10K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
R5517<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
BI<br />
BI<br />
43C1<br />
43C1<br />
D<br />
DETECT FIN-STACK TEMPERATURE<br />
Q5501<br />
1<br />
BC846BMXXH<br />
3<br />
SOT732-3<br />
2<br />
80D3 CPUTHMSNS_D2_P<br />
SIGNAL_MODOL=EMPTY<br />
C5520 1<br />
0.0022uF<br />
10%<br />
50V<br />
CERM<br />
2<br />
402<br />
80D3 CPUTHMSNS_D2_N<br />
PLACEMENT NOTE: PLACE U5515 NEAR CPU<br />
C<br />
C<br />
MCP T-Diode Thermal Sensor<br />
B<br />
CRITICAL<br />
J5590<br />
78171-0002<br />
M-RT-SM<br />
3<br />
1<br />
2<br />
4<br />
NOSTUFF<br />
7C5<br />
=PP3V3_S0_MCPTHMSNS<br />
DETECT HEAT-PIPE TEMPERATURE<br />
80D3 20C3<br />
BI<br />
R5535<br />
47<br />
SIGNAL_MODOL=EMPTY<br />
C5522<br />
1<br />
DETECT MCP DIE TEMPERATURE<br />
0.0022uF<br />
10%<br />
50V<br />
CERM 2<br />
402<br />
80D3 20C3 BI MCP_THMDIODE_N<br />
1<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
MCP_THMDIODE_P<br />
80D3 6C7 MCPTHMSNS_D2_P<br />
80D3 6C7<br />
SIGNAL_MODOL=EMPTY<br />
C5540<br />
0.0022uF<br />
10%<br />
NOSTUFF 50V<br />
MCPTHMSNS_D2_N<br />
2<br />
PP3V3_S0_MCPTHMSNS_R<br />
MIN_LINE_WIDTH=0.25 mm<br />
MIN_NECK_WIDTH=0.25 mm<br />
VOLTAGE=3.3V<br />
CERM<br />
402<br />
1<br />
2<br />
2<br />
DP1<br />
4<br />
DP2/DN3<br />
5<br />
DN2/DP3<br />
GND<br />
6<br />
INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE<br />
1<br />
VDD<br />
U5535<br />
EMC1413<br />
DFN<br />
THERM*/ADDR<br />
7<br />
3<br />
DN1 CRITICAL ALERT*<br />
8<br />
SMDATA<br />
SMCLK<br />
THRM_PAD<br />
11<br />
9<br />
10<br />
1<br />
C5535<br />
0.1uF<br />
20%<br />
10V<br />
2<br />
CERM<br />
402<br />
MCPTHMSNS_THERM_L<br />
MCPTHMSNS_ALERT_L<br />
=I2C_MCPTHMSNS_SDA<br />
=I2C_MCPTHMSNS_SCL<br />
R5536<br />
10K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
PLACEMENT NOTE: PLACE U5535 NEAR MCP<br />
1<br />
2<br />
1 R5537<br />
10K<br />
2<br />
BI<br />
BI<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
43D3<br />
43D3<br />
B<br />
REPLACED 518S0521 WITH 518S0519<br />
A<br />
SYNC_MASTER=YUNWU<br />
Thermal Sensors<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=03/20/2008<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
46<br />
81<br />
8 7 6 5 4 3 2 1
D<br />
8 7 6 5 4 3 2 1<br />
D<br />
D<br />
7D5<br />
7C5<br />
=PP5V_S0_FAN_RT<br />
=PP3V3_S0_FAN_RT<br />
C<br />
40A8<br />
SMC_FAN_0_TACH<br />
R5665<br />
47K<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
6D7<br />
R5660 1<br />
47K<br />
5%<br />
1/16W<br />
MF-LF 2<br />
402<br />
FAN_RT_TACH<br />
78171-0004<br />
M-RT-SM<br />
NC 5<br />
NC<br />
CRITICAL<br />
J5601<br />
1<br />
2<br />
3<br />
4<br />
6<br />
5V DC<br />
TACH<br />
MOTOR CONTROL<br />
GND<br />
C<br />
40B8<br />
R5661 1<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
SMC_FAN_0_CTL<br />
1<br />
2<br />
G<br />
S<br />
3<br />
Q5660<br />
SSM3K15FV<br />
SOD-VESM-HF<br />
6D7 FAN_RT_PWM<br />
518S0521<br />
B<br />
B<br />
A<br />
Fan<br />
SYNC_MASTER=CHANGZHANG SYNC_DATE=01/18/2008<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
47<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
8 7 6 5 4 3 2 1
TABLE_ALT_HEAD<br />
TABLE_ALT_ITEM<br />
8 7 6 5 4 3 2 1<br />
D<br />
C<br />
B<br />
PSOC USB CONTROLLER<br />
49C1 6C5 PICKB_L<br />
48A5 BUTTON_DISABLE<br />
49C3 6C5 Z2_HOST_INTN<br />
48C4 WS_LEFT_SHIFT_KEY<br />
48B4 WS_LEFT_OPTION_KEY<br />
48B4 WS_CONTROL_KEY<br />
49C1 6C5 Z2_KEY_ACT_L<br />
TP_P4_5<br />
49C3 6C5 Z2_DEBUG3<br />
49C1 6C5 Z2_RESET<br />
49C1 6C5 PSOC_MISO<br />
49C1 6C5 PSOC_F_CS_L<br />
49C1 6C5 PSOC_MOSI<br />
49C1 6C5 PSOC_SCLK<br />
49C3 6C5 Z2_MISO<br />
49C3 6C5 Z2_CS_L<br />
49C3 6C5 Z2_MOSI<br />
49C3 6C5 Z2_SCLK<br />
76B3 19D3<br />
TO <strong>MLB</strong> CONNECTOR<br />
76B3 19D3<br />
USB_TPAD_P<br />
USB_TPAD_N<br />
USB INTERFACES TO <strong>MLB</strong><br />
SPI HOST TO Z2<br />
P2_5<br />
P2_7<br />
P0_1<br />
P0_3<br />
P0_5<br />
P0_7<br />
VSS<br />
VDD<br />
P0_6<br />
P0_4<br />
P0_2<br />
P0_0<br />
P2_6<br />
P2_4<br />
1<br />
P2_3<br />
42<br />
P2_2<br />
2<br />
P2_1<br />
41<br />
P2_0<br />
NC 3<br />
CRITICAL<br />
40<br />
P4_7<br />
P4_6<br />
4<br />
39<br />
P4_5 U5701<br />
P4_4<br />
5<br />
P4_3 CY8C24794<br />
38<br />
P4_2<br />
6<br />
P4_1<br />
MLF<br />
37<br />
P4_0<br />
7<br />
P3_7<br />
(SYM-VER2)<br />
36<br />
P3_6<br />
8<br />
P3_5<br />
APN 337S2983<br />
35<br />
P3_4<br />
9<br />
P3_3<br />
P3_2<br />
34<br />
10<br />
OMIT<br />
33<br />
P3_1<br />
P3_0<br />
11<br />
P5_7<br />
32<br />
P5_6<br />
12<br />
P5_5<br />
31<br />
P5_4<br />
13<br />
P5_3<br />
30<br />
P5_2<br />
14<br />
P5_1<br />
29<br />
P5_0<br />
THRML<br />
57<br />
PAD<br />
TP_PSOC_SCL<br />
TP_PSOC_SDA<br />
TP_PSOC_P1_3<br />
TP_ISSP_SCLK_P1_1<br />
P1_7<br />
P1_5<br />
P1_3<br />
P1_1<br />
VSS<br />
D+<br />
D-<br />
VDD<br />
P7_7<br />
ISSP SCLK/I2C SCL<br />
R5702<br />
24<br />
76B3 1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
56<br />
15<br />
55<br />
16<br />
54<br />
17<br />
53<br />
18<br />
52<br />
19<br />
TRACKPAD PICK BUTTONS<br />
KEYBOARD SCANNER<br />
51<br />
20<br />
DIFFERENTIAL_PAIR=USB2_TPAD<br />
R5701<br />
24<br />
76B3 1 2 USB_TPAD_R_P<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
USB_TPAD_R_N<br />
50<br />
21<br />
DIFFERENTIAL_PAIR=USB2_TPAD<br />
49<br />
22<br />
PP3V3_S3_PSOC<br />
WS_KBD23<br />
WS_KBD22<br />
WS_KBD21<br />
WS_KBD20<br />
WS_KBD19<br />
WS_KBD18<br />
48<br />
23<br />
47<br />
P7_0<br />
P1_0<br />
P1_2<br />
P1_4<br />
P1_6<br />
24<br />
46<br />
25<br />
45<br />
26<br />
44<br />
27<br />
43<br />
28<br />
PP3V3_S3_PSOC<br />
48A8 48B6<br />
TP_ISSP_SDATA_P1_0<br />
ISSP SDATA/I2C SDA<br />
WS_KBD17 6B5 48C2<br />
WS_KBD16N 48C3<br />
WS_KBD15_C 48D3<br />
WS_KBD14 6B5 48C2<br />
WS_KBD13 6B5 48D2<br />
WS_KBD12 6B5 48D2<br />
WS_KBD11 6B5 48D2<br />
WS_KBD10 6B5 48D2<br />
WS_KBD9 6B5 48D2<br />
WS_KBD8 6B5 48D2<br />
WS_KBD7 6B5 48D2<br />
WS_KBD1 6B5 48D2<br />
WS_KBD2 6B5 48D2<br />
WS_KBD3 6B5 48D2<br />
WS_KBD4 6B5 48D2<br />
WS_KBD5 6B5 48D2<br />
WS_KBD6 6B5 48D2<br />
Z2_CLKIN<br />
TP_P7_7<br />
48A8 48D7<br />
6C5 49C3<br />
TMP102<br />
3V3 LDO<br />
PSOC<br />
IC<br />
18V BOOSTER<br />
48D2 48B5 48A6 7C3<br />
48C2 48B3 6A5<br />
48D2 48C5 48B5 48A6 7C3<br />
48C2 48B3 6A5<br />
48D2 48C5 48B5 48A6 7C3<br />
PIN NAME<br />
V+<br />
VDD<br />
VOUT<br />
VDD<br />
VIN<br />
CURRENT<br />
10UA<br />
80UA<br />
60MA MAX<br />
60MA MAX<br />
8MA (TYP)<br />
14MA (MAX)<br />
4MA (MAX)<br />
R_SNS<br />
2.55 KOHM<br />
10 OHM<br />
0.2 OHM<br />
1.5 OHM<br />
4.7 OHM<br />
A<br />
B<br />
A<br />
B<br />
A<br />
B<br />
Y<br />
Y<br />
V_SNS<br />
0.0255 V<br />
0.204 V<br />
0.6 V<br />
0.012 V<br />
0.012 V<br />
0.021 V<br />
0.0188 V<br />
ISOLATION CIRCUIT<br />
=PP3V3_S3_TPAD<br />
WS_LEFT_SHIFT_KBD<br />
48C5 48C3 48C2 48B5 7D1<br />
48C2 48B3 6A5<br />
48C3 48C2 48B5 7D1<br />
=PP3V3_S3_TPAD<br />
WS_LEFT_OPTION_KBD<br />
48C5 48C3 48C2 48B5 7D1<br />
=PP3V3_S3_TPAD<br />
WS_CONTROL_KBD<br />
2<br />
1<br />
2<br />
1<br />
2<br />
1<br />
CRITICAL<br />
5 TC7SZ08AFEAPE<br />
SOT665<br />
U5725<br />
3<br />
CRITICAL<br />
5 TC7SZ08AFEAPE<br />
SOT665<br />
U5726<br />
3<br />
Y<br />
4<br />
CRITICAL<br />
5 TC7SZ08AFEAPE<br />
SOT665<br />
U5727<br />
4<br />
=PP3V42_G3H_TPAD<br />
=PP3V42_G3H_TPAD<br />
4<br />
20%<br />
10V<br />
CERM<br />
402<br />
POWER<br />
C5725<br />
0.1UF<br />
=PP3V42_G3H_TPAD 2 1<br />
0.255E-6 W<br />
16.32E-6 W<br />
C5726<br />
0.1UF<br />
2 1<br />
20%<br />
10V<br />
CERM<br />
402<br />
36E-3 W<br />
0.72E-3 W<br />
96E-6 W<br />
294E-6 W<br />
75.2E-6 W<br />
C5727<br />
0.1UF<br />
2 1<br />
20%<br />
10V<br />
CERM<br />
402<br />
WS_LEFT_SHIFT_KEY<br />
48D8<br />
WS_LEFT_OPTION_KEY 48D8<br />
WS_CONTROL_KEY<br />
48D8<br />
41C7 41C2 41A3 40C5<br />
OUT<br />
48C6<br />
48C6<br />
SMC_ONOFF_L<br />
WS_KBD15_C<br />
WS_KBD16N<br />
R5714<br />
470<br />
1<br />
2<br />
1<br />
1<br />
C5710<br />
2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
R5715<br />
10K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
PLACEMENT_NOTE=NEAR J5713<br />
2<br />
KEYBOARD CONNECTOR<br />
IN<br />
SMC_MANUAL_RESET LOGIC<br />
1<br />
R5769<br />
33K<br />
5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
R5710<br />
1K<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
48C5 48C2 48B5 7D1<br />
48C2 48B5 6A5 WS_LEFT_SHIFT_KBD<br />
48C2 48B5 6A5 WS_LEFT_OPTION_KBD<br />
48C2 48B5 6A5 WS_CONTROL_KBD<br />
48C5 48C3 48B5 7D1<br />
48B5 48B3 6A5<br />
48B5 48B3 6A5<br />
48B5 48B3 6A5<br />
=PP3V42_G3H_TPAD<br />
1<br />
R5770<br />
33K<br />
5%<br />
1/16W<br />
2 402<br />
MF-LF<br />
48C6 6B5 WS_KBD1<br />
48C6 6B5 WS_KBD2<br />
48C6 6B5 WS_KBD3<br />
48C6 6B5 WS_KBD4<br />
48C6 6B5 WS_KBD5<br />
48C6 6B5 WS_KBD6<br />
48C6 6B5 WS_KBD7<br />
48C6 6B5 WS_KBD8<br />
48C6 6B5 WS_KBD9<br />
48C6 6B5 WS_KBD10<br />
48C6 6B5 WS_KBD11<br />
48C6 6B5 WS_KBD12<br />
48C6 6B5 WS_KBD13<br />
48C6 6B5 WS_KBD14<br />
6B5 WS_KBD15_CAP<br />
6B5 WS_KBD16_NUM<br />
48D6 6B5 WS_KBD17<br />
48D7 6B5 WS_KBD18<br />
48D7 6B5 WS_KBD19<br />
48D7 6B5 WS_KBD20<br />
48D7 6B5 WS_KBD21<br />
48D7 6A5 WS_KBD22<br />
48D7 6A5 WS_KBD23<br />
6A5 WS_KBD_ONOFF_L<br />
=PP3V42_G3H_TPAD<br />
WS_LEFT_SHIFT_KBD<br />
WS_LEFT_OPTION_KBD<br />
WS_CONTROL_KBD<br />
1<br />
48C5 48B5 48A6 7C3<br />
R5771<br />
33K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
=PP3V3_S3_TPAD<br />
1<br />
A<br />
3<br />
B<br />
6<br />
C<br />
2<br />
APN 518S0637<br />
NC<br />
NC<br />
APN 311S0406<br />
CRITICAL<br />
5<br />
SN74LVC1G10<br />
SC70<br />
4<br />
U5703 Y<br />
CRITICAL<br />
J5713<br />
32<br />
30<br />
29<br />
28<br />
27<br />
26<br />
25<br />
24<br />
23<br />
22<br />
21<br />
20<br />
19<br />
18<br />
17<br />
16<br />
15<br />
14<br />
13<br />
12<br />
11<br />
10<br />
9<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
1<br />
31<br />
F-RT-SM<br />
FF14-30A-R11B-B-3H<br />
1<br />
C5758<br />
0.1UF<br />
10%<br />
2 X7R-CERM<br />
16V<br />
402<br />
SMC_TPAD_RST_L<br />
41C7<br />
D<br />
C<br />
B<br />
A<br />
48B6<br />
48D7<br />
U5701 CHIP DECOUPLING<br />
PLACE C5701, C5702 & C5703<br />
CLOSE TO U5701 VDD PIN 22<br />
PP3V3_S3_PSOC<br />
C5701<br />
1<br />
4.7UF<br />
20%<br />
6.3V<br />
2 X5R<br />
603<br />
C5702<br />
1<br />
100PF<br />
5%<br />
50V<br />
2 CERM<br />
402<br />
MIN_LINE_WIDTH=0.50MM<br />
MIN_NECK_WIDTH=0.20MM<br />
1<br />
C5703<br />
0.1UF<br />
10%<br />
16V<br />
2<br />
X7R-CERM<br />
402<br />
PLACE C5704, C5705 & C5706<br />
CLOSE TO U5701 VDD PIN 49<br />
C5704<br />
1<br />
100PF<br />
5%<br />
50V<br />
2 CERM<br />
402<br />
1<br />
C5705<br />
0.1UF<br />
10%<br />
16V<br />
2 X7R-CERM<br />
402<br />
5%<br />
1/16W<br />
MF-LF<br />
1<br />
C5706 402<br />
4.7UF<br />
20%<br />
6.3V<br />
2 X5R<br />
603<br />
R5704<br />
1.5 =PP3V3_S3_TPAD<br />
1<br />
2<br />
7C3 48B5 48C5 48D2<br />
TPAD BUTTONS DISABLE<br />
58C1 41C2 40B5<br />
IN<br />
BUTTON_DISABLE<br />
48D8<br />
SMC_LID<br />
Q5701<br />
SSM3K15FV D 3<br />
SOD-VESM-HF<br />
1 G<br />
3<br />
S 2<br />
PLACE THESE COMPONENTS CLOSE TO J5800<br />
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON <strong>MLB</strong><br />
THE TPAD BUTTONS WILL BE DISABLE<br />
WHEN THE LID IS CLOSED<br />
LID OPEN => SMC_LID_LC ~ 3.42V<br />
LID CLOSE => SMC_LID_LC < 0.50V<br />
Alternate Parts<br />
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:<br />
PART NUMBER<br />
311S0406 311S0447 ALL NXP PART AS ALTERNATE<br />
SYNC_MASTER=YUAN.MA<br />
WELLSPRING 1<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
SYNC_DATE=04/22/2008<br />
A<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
48 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
BOOSTER +18.5VDC FOR SENSORS<br />
D<br />
R5805<br />
0<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
APN 152S0504<br />
BOOSTER DESIGN CONSIDERATION:<br />
- POWER CONSUMPTION<br />
- DROOP LINE REGULATION<br />
- RIPPLE TO MEET ERS<br />
- 100-300 KHZ CLEAN SPECTRUM<br />
- STARTUP TIME LESS THAN 2MS<br />
- R5812,R5813,C5818 MODIFIED<br />
CRITICAL<br />
D5802<br />
SOD-323<br />
B0520WSXG<br />
APN 371S0313<br />
R5806<br />
0<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
IPD FLEX CONNECTOR<br />
D<br />
1 C5816<br />
0.1UF<br />
10%<br />
16V<br />
2 X7R-CERM<br />
402<br />
THRML<br />
PAD<br />
PGND<br />
APN 353S1401<br />
GND<br />
SW<br />
1 C5819<br />
1UF<br />
2<br />
10%<br />
25V<br />
X5R<br />
603-1<br />
APN 516S0689<br />
NC 18<br />
20<br />
CRITICAL<br />
J5800<br />
55560-0228<br />
2<br />
4<br />
6<br />
8<br />
10<br />
12<br />
14<br />
16<br />
22<br />
M-ST-SM<br />
1<br />
3<br />
5<br />
7<br />
9<br />
11<br />
13<br />
15<br />
17<br />
19<br />
21<br />
C<br />
1<br />
4<br />
2<br />
=PP5V_S3_TPAD<br />
49B6 7C3<br />
INPUT_SW<br />
0.50MM<br />
0.20MM<br />
CRITICAL<br />
L5801<br />
3.3UH-870MA<br />
VLF3010AT-SM-HF<br />
BOOST_SW<br />
MIN_LINE_WIDTH=0.50MM<br />
MIN_NECK_WIDTH=0.20MM<br />
SWITCH_NODE=TRUE<br />
MIN_LINE_WIDTH=0.50MM<br />
MIN_NECK_WIDTH=0.20MM<br />
PP18V5_S3_SW<br />
PP18V5_S3<br />
6C3 6C5 49C1<br />
1<br />
C5800<br />
0.1UF<br />
20%<br />
10V<br />
2 CERM<br />
402<br />
PLACEMENT_NOTE=NEAR J5800<br />
MIN_LINE_WIDTH=0.50MM<br />
MIN_NECK_WIDTH=0.20MM<br />
PP5V_S3_BOOSTER<br />
1 C5817<br />
2.2UF<br />
10%<br />
16V<br />
2 X5R<br />
603<br />
VIN<br />
U5805<br />
1 L<br />
FB 4<br />
TPS61045<br />
3 DO<br />
QFN<br />
CTRL 5<br />
9<br />
2<br />
CRITICAL<br />
7<br />
6<br />
8<br />
BOOST_FB<br />
Z2_BOOST_EN 6C5 49C3<br />
1<br />
R5811<br />
100K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
2<br />
C5818<br />
39PF<br />
5%<br />
50V<br />
CERM<br />
402<br />
1<br />
R5812<br />
1M<br />
1%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
R5813<br />
71.5K<br />
1<br />
2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
49B4<br />
48C8 6C5<br />
48C8 6C5<br />
48C8 6C5<br />
48C8 6C5<br />
48C8 6C5<br />
49C5 6C5<br />
48D8 6C5<br />
48C6 6C5<br />
6C5 6C3<br />
Z2_CS_L<br />
Z2_DEBUG3<br />
Z2_MOSI<br />
Z2_MISO<br />
Z2_SCLK<br />
Z2_BOOST_EN<br />
Z2_HOST_INTN<br />
Z2_CLKIN<br />
PP3V3_S3_LDO<br />
0.50MM<br />
0.20MM<br />
0.50MM<br />
0.20MM<br />
0.50MM<br />
0.20MM<br />
Z2_KEY_ACT_L<br />
Z2_RESET<br />
PSOC_F_CS_L<br />
PICKB_L<br />
PSOC_MISO<br />
PSOC_MOSI<br />
PSOC_SCLK<br />
=I2C_TPAD_SDA<br />
=I2C_TPAD_SCL<br />
PP18V5_S3<br />
6C5 48C8<br />
6C5 48C8<br />
6C5 48C8<br />
6C5 48D8<br />
6C5 48C8<br />
6C5 48C8<br />
6C5 48C8<br />
43D1<br />
43D1<br />
6C3 6C5 49D3<br />
C<br />
3V3 LDO FOR IPD<br />
=PP5V_S3_TPAD<br />
49D7 7C3<br />
R5873<br />
10<br />
1 2<br />
PP5V_S3_VR<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
49C3 6C5 6C3<br />
PP3V3_S3_LDO<br />
B<br />
1<br />
C5853<br />
2.2UF<br />
10%<br />
2<br />
16V<br />
X5R<br />
603<br />
1<br />
CE<br />
CRITICAL<br />
APN 353S1364<br />
R5836<br />
0.2<br />
1 2<br />
1%<br />
1/6W<br />
MF<br />
402-HF<br />
VDD<br />
VR5802<br />
MM3243DRRE<br />
MLF<br />
VOUT 3 PP3V3_S3_LDO_R<br />
GND<br />
C5838<br />
1<br />
0.1UF<br />
10%<br />
16V<br />
2 X7R-CERM<br />
402<br />
1<br />
C5854<br />
4.7UF<br />
20%<br />
6.3V<br />
2 X5R<br />
603<br />
B<br />
KEYBOARD BACKLIGHT DRIVNG AND DETECTION<br />
A<br />
To detect Keyboard backlight, SMC will<br />
tristate SMC_SYS_KBDLED:<br />
LOW = keyboard backlight present<br />
HIGH= keyboard backlight not present<br />
BOM OPTION: KBDLED_YES<br />
TURNED ON FOR BEST <strong>MLB</strong> CONFIG<br />
R5853 ALWAYS PRESENT<br />
=PP3V3_S0_TPAD<br />
7C5<br />
IN<br />
40C8<br />
SMC_SYS_KBDLED<br />
SMC_KDBLED_PRESENT_L<br />
49A4 6A5<br />
R5853<br />
470K<br />
1/16W<br />
5%<br />
MF-LF<br />
402<br />
1<br />
2<br />
KB_BL 1<br />
R5854<br />
4.7K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
7D5<br />
=PP5V_S0_KBDLED<br />
KB_BL<br />
C5850<br />
1<br />
1UF<br />
10%<br />
10V<br />
X5R<br />
402-1<br />
NO STUFF<br />
1<br />
R5852<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402 2<br />
2<br />
GND<br />
VIN<br />
SW<br />
6 CTRL LED 5<br />
KB_BL<br />
CRITICAL<br />
U5850<br />
LT3491<br />
DFN<br />
2<br />
1<br />
CAP<br />
THRML<br />
PAD<br />
7<br />
KB_BL<br />
CRITICAL<br />
L5850<br />
10UH-0.58A-0.35OHM<br />
1 2<br />
1098AS-SM<br />
3<br />
4<br />
1 KB_BL<br />
R5855<br />
2<br />
10<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
KBDLED_SW<br />
MIN_LINE_WIDTH=0.3 MM<br />
MIN_NECK_WIDTH=0.25 MM<br />
SWITCH_NODE=TRUE<br />
KBDLED_CAP<br />
MIN_LINE_WIDTH=0.25 MM<br />
MIN_NECK_WIDTH=0.25 MM<br />
6A5<br />
KB_BL<br />
1 C5855<br />
1UF<br />
10%<br />
35V<br />
2<br />
X5R<br />
603<br />
KBDLED_ANODE<br />
MIN_LINE_WIDTH=0.25 MM<br />
MIN_NECK_WIDTH=0.25 MM<br />
SMC_KDBLED_PRESENT_L<br />
49A6 6A5<br />
APN 518S0691<br />
J5815 pin 1 is grounded<br />
KB_BL<br />
CRITICAL on keyboard backlight flex<br />
J5815<br />
FF18-4A-R11AD-B-3H<br />
F-RT-SM<br />
KBD BACKLIGHT CONNECTOR<br />
1<br />
2<br />
3<br />
4<br />
SYNC_MASTER=YUAN.MA<br />
APPLE INC.<br />
WELLSPRING 2<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
SYNC_DATE=05/09/2008<br />
OF<br />
49 81<br />
REV.<br />
4.7.0<br />
A<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
D<br />
C<br />
C<br />
Analog SMS<br />
R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC<br />
7C3<br />
=PP3V3_S3_SMS<br />
B<br />
40C8<br />
IN<br />
SMS_ONOFF_L<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
SMS_PWRDN<br />
MAKE_BASE=TRUE<br />
SMS_SELFTEST<br />
1<br />
R5922<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
NC<br />
NC<br />
NC<br />
NC<br />
1<br />
5<br />
2<br />
15<br />
4<br />
3<br />
6<br />
9<br />
LGA<br />
FS VOUTX<br />
PD CRITICAL<br />
VOUTY<br />
ST<br />
RES<br />
RES<br />
NC<br />
NC<br />
NC<br />
14<br />
VDD<br />
U5920<br />
AP344ALH<br />
GND<br />
7<br />
VOUTZ<br />
NC<br />
NC<br />
NC<br />
12<br />
10<br />
8<br />
11 NC<br />
13 NC<br />
16 NC<br />
SMS_X_AXIS<br />
SMS_Y_AXIS<br />
SMS_Z_AXIS<br />
1<br />
1<br />
2<br />
C5922<br />
0.1UF<br />
10%<br />
16V<br />
X5R<br />
402<br />
C5923<br />
0.01UF<br />
2 16V<br />
10%<br />
CERM<br />
402<br />
1<br />
2<br />
C5926<br />
10UF<br />
X5R<br />
4V<br />
20%<br />
603<br />
1<br />
C5924<br />
0.01UF<br />
10%<br />
16V<br />
2 CERM<br />
402<br />
1<br />
OUT<br />
OUT<br />
0.01UF<br />
10%<br />
16V<br />
2 CERM<br />
402<br />
40A8<br />
40A8<br />
OUT 40A8<br />
C5925<br />
Desired orientation when<br />
placed on board top-side:<br />
+Y<br />
Front of system<br />
+X<br />
+Z (up)<br />
Circle indicates pin 1 location when placed<br />
in correct orientation<br />
B<br />
A<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
A<br />
APPLE INC.<br />
R5921 1 4.7.0<br />
SMS<br />
SYNC_MASTER=YUNWU SYNC_DATE=06/26/2008<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
50<br />
OF<br />
REV.<br />
81<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
D<br />
42C7 42B5 7A3<br />
=PP3V3_S5_ROM<br />
C<br />
SPI_CLK_MUX<br />
R6150<br />
IN<br />
1 2<br />
42C5 42A8<br />
PLACEMENT_NOTE=PLACE CLOSE TO U6100 5%<br />
1/16W<br />
MF-LF<br />
IN<br />
SPI_<strong>MLB</strong>_CS_L 402<br />
42B5<br />
0<br />
NO STUFF<br />
R6190 1<br />
10K<br />
1/16W<br />
5%<br />
MF-LF<br />
4022<br />
R6100 1<br />
3.3K 5% 1/16W<br />
MF-LF<br />
402 2<br />
76A3<br />
1<br />
R6101<br />
3.3K<br />
5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
SPI_CLK<br />
SPI_WP_L<br />
SPI_HOLD_L<br />
C6100 1<br />
0.1UF<br />
20%<br />
10V<br />
CERM 2<br />
402<br />
CRITICAL<br />
VCC<br />
8<br />
U6100<br />
32MBIT<br />
SOP<br />
6 SCLK<br />
SI/SIO0 5 76A3<br />
MX25L3205DM2I-12G<br />
OMIT<br />
1 CE*<br />
3<br />
SO/SIO1 2 76A3<br />
WP*/ACC<br />
7 HOLD*<br />
GND<br />
4<br />
SPI_MOSI<br />
SPI_MISO_R<br />
NO STUFF<br />
1<br />
R6191<br />
10K 5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
R6152<br />
0<br />
SPI_MOSI_MUX<br />
1 2<br />
IN 42A8 42C5<br />
5% PLACEMENT_NOTE=PLACE CLOSE TO U6100<br />
1/16W<br />
R6105 MF-LF<br />
0<br />
402<br />
1 2<br />
SPI_MISO_MUX<br />
OUT 42A8 42B5<br />
5%<br />
1/16W PLACEMENT_NOTE=PLACE CLOSE TO U6100<br />
MF-LF<br />
402<br />
C<br />
B<br />
MCP79 SPI Frequency Select<br />
Frequency<br />
31 MHz<br />
SPI_MOSI<br />
0<br />
SPI_CLK<br />
0<br />
B<br />
42 MHz<br />
25 MHz<br />
1 MHz<br />
0<br />
1<br />
1<br />
1<br />
0<br />
1<br />
25MHz is selected with R5190 and R5191<br />
Any of the 4 frequencies can be selected<br />
with R6190, R6191, R5190 and R5191<br />
A<br />
SYNC_MASTER=CHANGZHANG<br />
SPI ROM<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=05/02/2008<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
51 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
C<br />
GPIO0 = ANALOG SW CONTROL<br />
GPIO1 = HP AMP CONTROL<br />
GPIO3 = SPKR AMP SHDN CONTROL<br />
7B6<br />
IN<br />
56D2 54C7 54C4 52D2 52A5<br />
52D2 52A5 6C2<br />
IN<br />
56A7<br />
54C5<br />
55C7<br />
57D8<br />
76B3 20D2<br />
76B3 20D2<br />
76A3 20D7<br />
76A3 20D2<br />
76A3 20D2<br />
OUT<br />
AUD_GPIO_0<br />
OUT<br />
AUD_GPIO_1<br />
TP_AUD_GPIO_2<br />
NC AUD_GPIO_3<br />
56D3<br />
OUT<br />
IN<br />
IN<br />
IN<br />
OUT<br />
IN<br />
IN<br />
NC<br />
OUT<br />
L6201<br />
FERR-220-OHM<br />
=PP1V8_S0_AUDIO 1 2<br />
VOLTAGE=1.8V<br />
MIN_LINE_WIDTH=0.10MM<br />
0402<br />
MIN_NECK_WIDTH=0.10MM<br />
GND_AUDIO_HP_AMP<br />
PP4V5_AUDIO_ANALOG<br />
AUD_SENSE_A<br />
HDA_BIT_CLK<br />
HDA_SYNC<br />
HDA_SDIN0<br />
HDA_SDOUT<br />
HDA_RST_L<br />
TP_AUD_SPDIF_IN<br />
AUD_SPDIF_OUT<br />
U6201 CONSUMES 33MA MAX. FROM 1.8V RAIL<br />
C6210<br />
R6212<br />
39<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
PP1V8_S0_AUDIO_DIG<br />
AUDIO CODEC<br />
APPLE P/N 353S2355<br />
1 1<br />
4.7UF<br />
C6211<br />
0.1UF<br />
20%<br />
10%<br />
4V<br />
X5R-1 2 2<br />
16V<br />
X5R<br />
402<br />
402<br />
C6216<br />
1<br />
C6215<br />
1<br />
1<br />
1<br />
0.1UF C6214<br />
C6219<br />
1UF<br />
10%<br />
10% 0.1UF<br />
10UF<br />
C6218<br />
1 1<br />
10V<br />
16V<br />
X5R 2<br />
10%<br />
20%<br />
C6217 X5R 2<br />
16V<br />
402<br />
X5R 2<br />
16V<br />
0.1UF 10UF 402-1<br />
2<br />
TANT-POLY<br />
10%<br />
20%<br />
402<br />
CRITICAL 2012-LLP<br />
16V<br />
X5R 2 2 16V<br />
TANT-POLY<br />
C6221<br />
1 1<br />
C6220<br />
402<br />
2012-LLP<br />
10UF<br />
10UF<br />
VD VA_REF VA_HP VA<br />
20%<br />
20%<br />
1<br />
VBIAS_DAC<br />
6.3V<br />
VBIAS_DAC<br />
X5R<br />
2 2<br />
6.3V<br />
29<br />
R6210<br />
X5R<br />
603-1<br />
603-1<br />
HPOUT_L 38 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM<br />
2.67K<br />
CS4206_FP<br />
44 VHP_FILT+<br />
1%<br />
CRITICAL<br />
HPOUT_R 40 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM<br />
1/16W<br />
CS4206_FN<br />
41 VHP_FILT- U6201<br />
MF-LF<br />
402<br />
CS4206ACNZC<br />
2<br />
HPREF 39 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM<br />
QFN<br />
R6211<br />
10 SYNC<br />
39<br />
1 2 AUD_SDI_R<br />
8 SDI<br />
MICIN_L+ 18<br />
2 GPIO0/DMIC_SDA1 LINEOUT_L1+ 35<br />
12 GPIO1/DMIC_SDA2 LINEOUT_L1- 34<br />
/SPDIF_OUT2<br />
14 GPIO2<br />
LINEOUT_R1+ 36<br />
15 GPIO3<br />
LINEOUT_R1- 37<br />
13 SENSE_A<br />
LINEOUT_L2+ 31<br />
CS4206_FLYP<br />
LINEOUT_L2- 30<br />
CS4206_FLYC<br />
LINEOUT_R2+ 32<br />
45 FLYP<br />
LINEOUT_R2-<br />
C6222<br />
1 1<br />
33<br />
C6223<br />
43 FLYC<br />
2.2UF<br />
2.2UF<br />
20%<br />
20%<br />
42 FLYN<br />
6.3V<br />
6.3V<br />
CRITICAL<br />
CERM 2 2 CERM<br />
MICBIAS 16<br />
402-LF<br />
402-LF<br />
3 VL_HD<br />
CS4206_FLYN<br />
VCOM 28 CS4206_VCOM<br />
1 VL_IF<br />
6 BITCLK<br />
LINEIN_L+ 21<br />
LINEIN_C- 22<br />
LINEIN_R+ 23<br />
5%<br />
1/16W<br />
5 SDO<br />
MICIN_L- 17<br />
MF-LF<br />
MICIN_R+ 19<br />
402<br />
11 RESET*<br />
MICIN_R- 20<br />
AUD_SPDIF_OUT_CHIP<br />
9<br />
47 SPDIF_IN<br />
48 SPDIF_OUT<br />
24<br />
46<br />
25<br />
DGND THRM_PAD AGND<br />
VREF+_ADC<br />
DMIC_SCL<br />
27<br />
4<br />
CS4206_VREF_ADC<br />
TP_AUD_DMIC_CLK<br />
NC<br />
NC<br />
C6213<br />
=PP5V_S3_AUDIO<br />
=PP3V3_S0_AUDIO<br />
PP4V5_AUDIO_ANALOG<br />
AUD_HP_PORT_L<br />
AUD_HP_PORT_R<br />
AUD_HP_PORT_REF<br />
TP_AUD_LO1_P_L<br />
TP_AUD_LO1_N_L<br />
AUD_LO1_P_R<br />
AUD_LO1_N_R<br />
AUD_LO2_P_L<br />
AUD_LO2_N_L<br />
AUD_LO2_P_R<br />
AUD_LO2_N_R<br />
AUD_CODEC_MICBIAS<br />
AUD_LI_P_L<br />
AUD_LI_REF<br />
AUD_LI_P_R<br />
AUD_MIC_INP_L<br />
AUD_MIC_INN_L<br />
AUD_MIC_INP_R<br />
AUD_MIC_INN_R<br />
7C3 52A8 54D5 56B6<br />
7C5 52A8 56D8 57B8 57D3<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
NC<br />
NC<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
6C2 52A5 52D7<br />
1<br />
10UF<br />
20% CRITICAL<br />
2 X5R<br />
6.3V<br />
603-1<br />
GND_AUDIO_HP_AMP 52A5 52D7 54C4 54C7 56D2<br />
GND_AUDIO_CODEC 52A5 52B7 53B6 56A7 57A8 57B4 57B8 57C3 57C8 57D1<br />
54C7<br />
54B7<br />
56D3<br />
55B7<br />
55B7<br />
55B7<br />
55A7<br />
55C7<br />
55C7<br />
57C4<br />
53C3<br />
53B3<br />
53B3<br />
57C3<br />
57C3<br />
57B4<br />
57B4<br />
FR SPKR AMP. SIG. SOURCE<br />
LFT. SPKR AMP. SIG. SOURCE<br />
RT. SPKR AMP. SIG. SOURCE<br />
EXT MIC CODEC INPUT<br />
BI MIC CODEC INPUT<br />
D<br />
C<br />
7<br />
49<br />
26<br />
B<br />
57D1 57C8 57C3 57B8 57B4 57A8 56A7 53B6 52D2 52A5<br />
GND_AUDIO_CODEC<br />
MIN_LINE_WIDTH=0.5MM<br />
MIN_NECK_WIDTH=0.2MM<br />
VOLTAGE=0V<br />
C6224 1<br />
1UF<br />
20%<br />
16V<br />
TANT 2<br />
0603-SM<br />
1<br />
C6225<br />
10UF<br />
20%<br />
2 16V<br />
TANT-POLY<br />
2012-LLP<br />
1<br />
NOSTUFF<br />
R6213<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
B<br />
A<br />
56B6 54D5 52D2 7C3<br />
57D3 57B8 56D8 52D2 7C5<br />
IN<br />
IN<br />
=PP5V_S3_AUDIO<br />
=PP3V3_S0_AUDIO<br />
L6200<br />
0402<br />
4.5V POWER SUPPLY FOR CODEC<br />
MIN_LINE_WIDTH=0.15MM<br />
FERR-220-OHM MIN_NECK_WIDTH=0.10MM<br />
VOLTAGE=5V<br />
1<br />
2 4V5_REG_IN<br />
R6200<br />
2.21K<br />
1 2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
C6200<br />
1UF<br />
10%<br />
2<br />
10V<br />
X5R<br />
402<br />
4V5_REG_EN<br />
XW6200<br />
SM<br />
NOSTUFF<br />
R6201<br />
0<br />
APPLE P/N 353S2456<br />
10%<br />
10V<br />
2 X5R<br />
402<br />
TPS71745<br />
6 SON<br />
IN<br />
1<br />
OUT<br />
CRITICAL<br />
4 EN NR/FB 3 4V5_NR<br />
1UF<br />
U6200<br />
GND<br />
2<br />
NC 5<br />
1<br />
1 C6201<br />
C6202<br />
1<br />
C6203<br />
1UF<br />
0.1UF<br />
10%<br />
16V<br />
X7R-CERM 2<br />
402<br />
MIN_LINE_WIDTH=0.15MM<br />
MIN_NECK_WIDTH=0.10MM<br />
VOLTAGE=4.5V<br />
PP4V5_AUDIO_ANALOG<br />
2<br />
10%<br />
10V<br />
X5R<br />
402<br />
OUT<br />
GND_AUDIO_CODEC<br />
6C2 52D2 52D7<br />
52B7 52D2 53B6 56A7 57A8 57B4 57B8 57C3 57C8 57D1<br />
NOTES ON CODEC I/O<br />
DIFF FSINPUT= 2.45VRMS<br />
SE FSINPUT= 1.22VRMS<br />
DAC1 FSOUTPUT= 1.34VRMS<br />
DAC2/3 FSOUTPUTDIFF= 2.67VRMS<br />
DAC2/3 FSOUTPUTSE= 1.34VRMS<br />
AUDIO: CODEC/REGULATOR<br />
NOTICE OF PROPRIETARY PROPERTY<br />
A<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
XW6201<br />
SM<br />
1 2<br />
MIN_LINE_WIDTH=0.3MM<br />
MIN_NECK_WIDTH=0.2MM<br />
VOLTAGE=0V<br />
GND_AUDIO_HP_AMP<br />
52D2 52D7 54C4 54C7 56D2<br />
APPLE INC.<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
52<br />
81<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
D<br />
LINE INPUT VOLTAGE DIVIDER<br />
CODEC RIN = 20K OHMS<br />
NET RIN = 10.36K OHMS (INCLUDING PULL-DOWNS AT ANALOG SWITCH COM PINS)<br />
FC_HP = 3.6 HZ<br />
FC_LP = 43KHZ<br />
VIN = 2VRMS, CODEC VIN = 1.14 VRMS<br />
C<br />
56B7<br />
IN<br />
AUD_LI_L<br />
MIN_LINE_WIDTH=.1MM<br />
MIN_NECK_WIDTH=.1MM<br />
R6301<br />
7.87K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
AUD_LI_L_DIV<br />
MIN_LINE_WIDTH=.1MM<br />
MIN_NECK_WIDTH=.1MM<br />
NOSTUFF<br />
C6303<br />
820PF<br />
10%<br />
50V<br />
CERM<br />
402<br />
R6302<br />
21.5K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
CRITICAL<br />
C6301<br />
2.2UF<br />
20%<br />
10V<br />
X5R-CERM<br />
402<br />
CRITICAL<br />
C6302<br />
2.2UF<br />
AUD_LI_P_L<br />
MIN_LINE_WIDTH=.1MM<br />
MIN_NECK_WIDTH=.1MM<br />
OUT<br />
52C2<br />
C<br />
20%<br />
10V<br />
X5R-CERM<br />
402<br />
56D2<br />
IN<br />
AUD_LI_GND<br />
10 1%<br />
1/16W<br />
MF-LF<br />
2402<br />
MIN_LINE_WIDTH=.1MM<br />
MIN_NECK_WIDTH=.1MM<br />
1<br />
R6300<br />
CRITICAL<br />
C6312<br />
2.2UF<br />
AUD_LI_REF<br />
MIN_LINE_WIDTH=.1MM<br />
MIN_NECK_WIDTH=.1MM<br />
OUT<br />
52C2<br />
B<br />
57D1 57C8 57C3 57B8 57B4 57A8 56A7 52D2 52B7 52A5<br />
IN<br />
GND_AUDIO_CODEC<br />
NOSTUFF<br />
C6313<br />
820PF<br />
10%<br />
50V<br />
CERM<br />
402<br />
R6312<br />
21.5K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
20%<br />
10V<br />
X5R-CERM<br />
402<br />
B<br />
56A7<br />
IN<br />
AUD_LI_R<br />
MIN_LINE_WIDTH=.1MM<br />
MIN_NECK_WIDTH=.1MM<br />
R6311<br />
7.87K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
AUD_LI_R_DIV<br />
MIN_LINE_WIDTH=.1MM<br />
MIN_NECK_WIDTH=.1MM<br />
CRITICAL<br />
C6311<br />
2.2UF<br />
20%<br />
10V<br />
X5R-CERM<br />
402<br />
AUD_LI_P_R<br />
MIN_LINE_WIDTH=.1MM<br />
MIN_NECK_WIDTH=.1MM<br />
OUT<br />
52C2<br />
A<br />
AUDIO: LINE INPUT FILTER<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
53 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
FOR PROTO2, STUFF R6521 AND NO STUFF R6520 AND R6522 UNTIL<br />
RE-TASKABLE IO SW SUPPORT AVAILABLE (FORCES IO INTO OUTPUT MODE).<br />
D<br />
C<br />
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER<br />
52D2<br />
NC<br />
IN<br />
AUD_HP_PORT_L<br />
AUD_HP_ZOBEL_L<br />
CRITICAL<br />
C6500<br />
1<br />
0.1UF<br />
10%<br />
16V<br />
X7R-CERM 2<br />
402<br />
R6500<br />
1<br />
39<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R6501<br />
0<br />
1<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
NO STUFF<br />
CRITICAL<br />
1<br />
C6501<br />
0.0022UF<br />
10%<br />
50V<br />
CERM<br />
402<br />
2<br />
AUD_HP_L OUT 54B4<br />
52C7 IN<br />
56B6 52D2 52A8 7C3<br />
FERR-120-OHM-1.5A<br />
=PP5V_S3_AUDIO<br />
0402-LF<br />
AUD_LO_AMP_INL_M<br />
54B3<br />
54B3<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
56D2 54C7 52D7 52D2 52A5<br />
L6520<br />
AUD_LO_AMP_INR_M<br />
R6520<br />
0<br />
AUD_GPIO_1 1 2 AUD_GPIO_1_R<br />
GND_AUDIO_HP_AMP<br />
MIN_LINE_WIDTH=0.3MM<br />
MIN_NECK_WIDTH=0.2MM<br />
AUD_PP5V_F<br />
C6520<br />
0.1UF<br />
10%<br />
16V<br />
X7R-CERM<br />
402<br />
C6521<br />
10UF<br />
20%<br />
6.3V<br />
X5R<br />
603<br />
R6522<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
NO STUFF<br />
R6521<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
6 INL<br />
8 INR<br />
5 SHDN*<br />
THRM<br />
PAD<br />
13<br />
HP/LO AMP<br />
APN: 353S1637<br />
SGND<br />
7<br />
12<br />
VDD<br />
CRITICAL<br />
U6500<br />
MAX9724A<br />
TQFN<br />
PGND<br />
2<br />
SVSS<br />
9<br />
OUTL<br />
OUTR<br />
C1P 1<br />
C1N 3<br />
PVSS<br />
4<br />
11<br />
10<br />
CRITICAL<br />
C6522<br />
1UF<br />
10%<br />
10V<br />
X5R<br />
402<br />
MAX9724_C1P<br />
MAX9724_C1N<br />
MAX9724_SVSS<br />
MIN_NECK_WIDTH=0.15MM<br />
MIN_LINE_WIDTH=0.2MM<br />
MIN_NECK_WIDTH=0.15MM<br />
MIN_LINE_WIDTH=0.2MM<br />
CRITICAL<br />
C6523<br />
1UF<br />
10%<br />
10V<br />
X5R<br />
402<br />
CRITICAL<br />
C6524<br />
1UF<br />
10%<br />
10V<br />
X5R<br />
402<br />
AUD_LO_AMP_OUTL<br />
AUD_LO_AMP_OUTR<br />
OUT<br />
OUT<br />
54B1 56B7<br />
54B1 56B7<br />
D<br />
C<br />
56D2 54C4 52D7 52D2 52A5<br />
IN<br />
GND_AUDIO_HP_AMP<br />
NC<br />
52D2<br />
AUD_HP_ZOBEL_R<br />
IN<br />
R6510<br />
39<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
CRITICAL<br />
C6510<br />
1<br />
0.1UF<br />
10%<br />
16V<br />
X7R-CERM 2<br />
402<br />
AUD_HP_PORT_R<br />
1<br />
R6511<br />
0<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
NO STUFF<br />
CRITICAL<br />
1<br />
C6511<br />
0.0022UF<br />
10%<br />
50V<br />
CERM<br />
402<br />
2<br />
AUD_HP_R<br />
OUT<br />
54B4<br />
MAX9724 GAIN/FILTER COMPONENTS<br />
AV_PB = -1V/V, FC_LPF = 35.2KHZ<br />
CRITICAL<br />
C6530<br />
330PF<br />
5%<br />
50V<br />
COG<br />
402<br />
R6531<br />
13.7K<br />
B<br />
54C6<br />
IN<br />
AUD_HP_L<br />
R6530<br />
13.7K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
AUD_LO_AMP_INL_M<br />
54C4<br />
AUD_LO_AMP_OUTL<br />
OUT<br />
54D1 56B7<br />
B<br />
54B6<br />
IN<br />
AUD_HP_R<br />
R6532<br />
13.7K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
AUD_LO_AMP_INR_M<br />
54C4<br />
R6533<br />
13.7K<br />
AUD_LO_AMP_OUTR<br />
OUT<br />
54C1 56B7<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
CRITICAL<br />
C6531<br />
330PF<br />
A<br />
5%<br />
50V<br />
COG<br />
402<br />
SYNC_MASTER=AUDIO<br />
AUDIO: HEADPHONE FILTER<br />
NOTICE OF PROPRIETARY PROPERTY<br />
SYNC_DATE=02/03/2009<br />
A<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
54 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
SATELLITE & SUB TWEETER AMPLIFIER<br />
APN:353S2524<br />
D<br />
SATELLITE<br />
SUB<br />
GAIN<br />
169 HZ < FC < 282 HZ<br />
80 HZ < FC < 132 HZ<br />
6DB<br />
D<br />
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM<br />
55C7 55B7 7C3<br />
=PP5V_S3_AUDIO_AMP<br />
C<br />
55B7 55A7<br />
52C2 IN<br />
52C2 IN<br />
52C7 IN<br />
AUD_LO2_P_R<br />
AUD_LO2_N_R<br />
AUD_GPIO_3<br />
SPKRAMP_SHDN<br />
L6610<br />
FERR-1000-OHM<br />
1 2 SPKRAMP_INR_P<br />
0402<br />
L6611<br />
FERR-1000-OHM<br />
1 2<br />
0402<br />
SPKRAMP_INR_N<br />
CRITICAL<br />
C6611<br />
0.047UF<br />
2<br />
1<br />
10%<br />
16V<br />
X7R<br />
402<br />
CRITICAL<br />
C6610<br />
0.047UF<br />
1 2<br />
10%<br />
16V<br />
X7R<br />
402<br />
R6610<br />
0<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
C6607<br />
1<br />
1UF<br />
10%<br />
10V<br />
X5R 2<br />
402<br />
MAX9705_R_P<br />
MAX9705_R_N<br />
R6611<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
3<br />
5<br />
IN+<br />
1 10<br />
VDD PVDD<br />
U6610<br />
MAX9705A<br />
TDFN<br />
OUT+ 8<br />
IN- OUT-<br />
CRITICAL<br />
SYNC<br />
SHDN*<br />
THRML<br />
GND PGND PAD<br />
4 7 11<br />
9<br />
6<br />
CRITICAL<br />
1<br />
C6601<br />
47UF<br />
20%<br />
2 6.3V<br />
TANT1<br />
2012-LLP<br />
MIN_LINE_WIDTH=0.30 mm<br />
MIN_NECK_WIDTH=0.20 MM<br />
SPKRAMP_R_P_OUT<br />
6C7 56B2<br />
MIN_LINE_WIDTH=0.30 mm<br />
MIN_NECK_WIDTH=0.20 MM<br />
SPKRAMP_R_N_OUT<br />
6C7 56A2<br />
C<br />
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM<br />
55D7 55B7 7C3 =PP5V_S3_AUDIO_AMP<br />
52C2<br />
52C2<br />
55C7 55A7<br />
IN<br />
IN<br />
AUD_LO1_P_R<br />
AUD_LO1_N_R<br />
SPKRAMP_SHDN<br />
L6620<br />
FERR-1000-OHM<br />
1 2<br />
0402<br />
SPKRAMP_INSUB_P<br />
L6621<br />
FERR-1000-OHM<br />
1 2<br />
0402<br />
CRITICAL<br />
C6620<br />
0.1UF<br />
10%<br />
16V<br />
X5R<br />
402<br />
SPKRAMP_INSUB_N<br />
CRITICAL<br />
C6621<br />
0.1UF<br />
1 2<br />
10%<br />
16V<br />
X5R<br />
402<br />
C6608<br />
1UF<br />
10% 10V<br />
X5R<br />
402<br />
MAX9705_SUB_P<br />
MAX9705_SUB_N<br />
1<br />
2<br />
VDD<br />
GND PGND<br />
PVDD<br />
U6620<br />
MAX9705A<br />
TDFN<br />
IN+ OUT+<br />
IN- OUT-<br />
CRITICAL<br />
SYNC<br />
SHDN*<br />
THRML<br />
PAD<br />
1<br />
CRITICAL<br />
C6603<br />
100UF<br />
20%<br />
2 6.3V<br />
TANT<br />
CASE-AL1<br />
MIN_LINE_WIDTH=0.30 mm<br />
MIN_NECK_WIDTH=0.20 MM<br />
SPKRAMP_SUB_P_OUT 6C7 56B2<br />
MIN_LINE_WIDTH=0.30 mm<br />
MIN_NECK_WIDTH=0.20 MM<br />
SPKRAMP_SUB_N_OUT<br />
6C7 56B2<br />
B<br />
B<br />
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM<br />
55D7 55C7 7C3 =PP5V_S3_AUDIO_AMP<br />
55C7 55B7<br />
52C2 IN<br />
52C2 IN<br />
AUD_LO2_P_L<br />
AUD_LO2_N_L<br />
SPKRAMP_SHDN<br />
L6630<br />
FERR-1000-OHM<br />
1 2<br />
0402<br />
L6631<br />
SPKRAMP_INL_P<br />
FERR-1000-OHM<br />
1 2 SPKRAMP_INL_N<br />
0402<br />
CRITICAL<br />
C6630<br />
0.047UF<br />
1 2<br />
10%<br />
16V<br />
X7R<br />
402<br />
CRITICAL<br />
C6631<br />
0.047UF<br />
1 2<br />
10%<br />
16V<br />
X7R<br />
402<br />
C6609<br />
1<br />
1UF<br />
10%<br />
10V<br />
X5R<br />
402<br />
MAX9705_L_P<br />
MAX9705_L_N<br />
IN+<br />
IN-<br />
VDD<br />
GND PGND<br />
PVDD<br />
2 U6630<br />
MAX9705A<br />
TDFN<br />
OUT+<br />
OUT-<br />
CRITICAL SYNC<br />
SHDN*<br />
THRML<br />
PAD<br />
CRITICAL<br />
1<br />
C6605<br />
47UF<br />
20%<br />
2 6.3V<br />
TANT1<br />
2012-LLP<br />
MIN_LINE_WIDTH=0.30 mm<br />
MIN_NECK_WIDTH=0.20 MM<br />
SPKRAMP_L_P_OUT<br />
MIN_LINE_WIDTH=0.30 mm<br />
MIN_NECK_WIDTH=0.20 MM<br />
SPKRAMP_L_N_OUT<br />
6D7 56B2<br />
6D7 56B2<br />
A<br />
AUDI0: SPEAKER AMP<br />
SYNC_MASTER=AUDIO<br />
SYNC_DATE=12/18/2008<br />
NOTICE OF PROPRIETARY PROPERTY<br />
A<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
55 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
AUDIO JACK: LI/LO/HP CONNECTOR, SPDIF TX<br />
D<br />
C<br />
57D3 57B8 52D2 52A8 7C5<br />
=PP3V3_S0_AUDIO<br />
APN:514-0671<br />
J6700<br />
SPDIF-TXRX-<strong>K24</strong><br />
F-RT-TH<br />
CRITICAL<br />
MIC<br />
DETECT<br />
6<br />
5<br />
SWITCH 2<br />
LEFT 1<br />
RIGHT 3<br />
GND 4<br />
AUDIO<br />
A - VIN<br />
B - VCC<br />
C - GND<br />
OPERATING VOLTAGE 3.3<br />
POF<br />
SHELL<br />
SHIELD<br />
PINS<br />
7<br />
8<br />
9<br />
10<br />
11<br />
12<br />
13<br />
GND_CHASSIS_AUDIO_JACK<br />
1 C6700<br />
1UF<br />
10%<br />
6.3V<br />
2 CERM<br />
402<br />
CHASSIS GND STITCHES<br />
XW6710<br />
SM<br />
AUD_CONNJ1_MIC<br />
MIN_LINE_WIDTH=0.4MM<br />
MIN_NECK_WIDTH=0.2MM<br />
AUD_CONNJ1_SLEEVE<br />
AUD_CONNJ1_SLEEVEDET<br />
AUD_CONNJ1_TIPDET<br />
AUD_CONNJ1_TIP<br />
AUD_CONNJ1_RING<br />
CRITICAL<br />
DZ6701<br />
6.8V-100PF<br />
402<br />
2<br />
1<br />
2<br />
1<br />
CRITICAL<br />
DZ6705<br />
6.8V-100PF<br />
402<br />
CRITICAL<br />
DZ6704<br />
6.8V-100PF<br />
402<br />
2<br />
1<br />
2<br />
1<br />
CRITICAL<br />
DZ6703<br />
6.8V-100PF<br />
402<br />
CRITICAL<br />
DZ6700<br />
6.8V-100PF<br />
402<br />
2<br />
1<br />
NOSTUFF<br />
R6723<br />
0<br />
L6701<br />
FERR-1000-OHM<br />
1<br />
0402<br />
L6702<br />
FERR-1000-OHM<br />
2<br />
1 2<br />
IN<br />
HS_MIC_HI OUT 57C1<br />
HS_MIC_LO OUT 57C1<br />
0402<br />
L6706 CRITICAL<br />
FERR-220-OHM<br />
AUD_HP_PORT_REF<br />
0402<br />
CRITICAL<br />
L6703<br />
FERR-120-OHM-1.5A<br />
C6701<br />
1<br />
100PF<br />
5%<br />
50V<br />
2 CERM<br />
402<br />
1<br />
0402-LF<br />
CRITICAL<br />
L6704<br />
2<br />
FERR-220-OHM<br />
1<br />
2<br />
0402<br />
CRITICAL<br />
L6705<br />
FERR-220-OHM<br />
1<br />
2<br />
0402<br />
R6700<br />
10K<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
R6701<br />
4.7<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
AUD_SPDIF_OUT<br />
OUT<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
52B7<br />
MIN_LINE_WIDTH=0.4MM<br />
MIN_NECK_WIDTH=0.2MM<br />
AUD_CONN_GND<br />
AUD_CONN_L<br />
AUD_CONN_R<br />
AUD_J1_SLEEVEDET_R<br />
AUD_J1_TIPDET_R<br />
52D2<br />
56B3<br />
56A3<br />
57C6 57C8<br />
57A7 57C8<br />
XW6700<br />
SM<br />
XW6701<br />
SM<br />
GND_AUDIO_HP_AMP<br />
AUD_LI_GND<br />
AUD_CONN_GND<br />
52A5 52D2 52D7 54C4 54C7<br />
53B6<br />
56A7 56D256A7<br />
56D2<br />
MIC CONNECTOR<br />
APN:518S0520<br />
57B1 6D7<br />
57B1 6D7<br />
57B1 6D7<br />
BI_MIC_LO<br />
BI_MIC_SHIELD<br />
BI_MIC_HI<br />
CRITICAL<br />
J6701<br />
78171-0003<br />
M-RT-SM<br />
4<br />
1<br />
2<br />
3<br />
5<br />
D<br />
C<br />
XW6711<br />
SM<br />
R6760<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
7D1<br />
=PP3V42_G3H_AUDIO<br />
NOSTUFF<br />
R6725<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
NOSTUFF<br />
R6722<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
SPEAKER CONNECTOR<br />
APN:518S0519<br />
55B2 6D7<br />
55A2 6D7<br />
IN<br />
IN<br />
SPKRAMP_L_P_OUT<br />
SPKRAMP_L_N_OUT<br />
CRITICAL<br />
J6702<br />
78171-0002<br />
M-RT-SM<br />
3<br />
1<br />
2<br />
B<br />
A<br />
54D1 54B1<br />
54C1 54B1<br />
53C6<br />
53B6<br />
52C7<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
IN<br />
AUD_LO_AMP_OUTL<br />
AUD_LO_AMP_OUTR<br />
AUD_LI_L<br />
AUD_LI_R<br />
AUD_GPIO_0<br />
R6716<br />
R6717<br />
R6715<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
GND STUFFING OPTIONS FOR CMOS SWITCH<br />
GND_AUDIO_CODEC<br />
56D2<br />
57D1 57C8 57C3 57B8 57B4 57A8 53B6 52D2 52B7 52A5<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
R6718<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
R6719<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
AUD_CONN_GND<br />
54D5 52D2 52A8 7C3<br />
R6720<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
=PP5V_S3_AUDIO<br />
AUD_LO_AMP_OUTL_SWITCH<br />
AUD_LO_AMP_OUTR_SWITCH<br />
AUD_LI_L_SWITCH<br />
AUD_LI_R_SWITCH<br />
AUD_SWITCH_CTRL<br />
AUD_SWITCH_GND<br />
R6714<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
R6724<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
R6721<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
C6710<br />
1UF<br />
10%<br />
10V<br />
X5R<br />
402<br />
PP_MAX14504_VCC<br />
C6711<br />
0.0033UF<br />
10%<br />
50V<br />
CERM<br />
402<br />
NOSTUFF<br />
R6726<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
VCC<br />
C4 NC1<br />
MAX14504<br />
WLP COM1 B4<br />
C1 NC2 CRITICAL<br />
A4 NO1<br />
A1 NO2<br />
C2 CB<br />
SWITCH_CP A2 NEG<br />
A3<br />
U6700<br />
B3<br />
GND<br />
C3<br />
APN: 353S2536<br />
COM2 B1<br />
EN* B2<br />
R6713<br />
24K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
ANALOG AUDIO IO SWITCH<br />
NOSTUFF<br />
R6727<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
MIN_LINE_WIDTH=0.2MM<br />
MIN_NECK_WIDTH=0.15MM<br />
MIN_LINE_WIDTH=0.2MM<br />
MIN_NECK_WIDTH=0.15MM<br />
R6712<br />
24K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
AUD_CONN_L<br />
AUD_CONN_R<br />
GPIO0 = 0 AND GPIO1 = 1 --> HP PATH SELECTED<br />
GPIO0 = 1 AND GPIO1 = 0 --> LI PATH SELECTED<br />
BI<br />
BI<br />
56C3<br />
56C3<br />
55C2 6C7<br />
55B2 6C7<br />
55C2 6C7<br />
IN<br />
IN<br />
IN<br />
SPKRAMP_SUB_P_OUT<br />
SPKRAMP_SUB_N_OUT<br />
SPKRAMP_R_P_OUT<br />
SPKRAMP_R_N_OUT<br />
55C2 6C7 IN<br />
C6760 - C6763 ARE FOR FILTERING POTENTIAL FSB NOISE COUPLED ON SPKR LINES<br />
APPLE INC.<br />
1<br />
1<br />
C6760<br />
33PF<br />
2 50V 5%<br />
CERM<br />
402<br />
C6761<br />
33PF<br />
5%<br />
2<br />
50V<br />
CERM<br />
402<br />
1<br />
2<br />
1<br />
C6762<br />
33PF<br />
5%<br />
50V<br />
CERM<br />
402<br />
C6763<br />
33PF<br />
5%<br />
50V<br />
2 CERM<br />
402<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
APN:518S0521<br />
SHT<br />
4<br />
CRITICAL<br />
J6703<br />
78171-0004<br />
M-RT-SM<br />
5<br />
AUDIO: JACK<br />
SYNC_MASTER=AUDIO SYNC_DATE=03/20/2009<br />
1<br />
2<br />
3<br />
4<br />
6<br />
051-7898<br />
56<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
B<br />
A<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
CODEC OUTPUT SIGNAL PATHS<br />
D<br />
C<br />
FUNCTION<br />
HP/LINE OUT<br />
LINE IN<br />
SATELLITES<br />
SUB<br />
SPDIF OUT<br />
VOLUME<br />
0X02 (2)<br />
0X05 (5)<br />
0X04 (4)<br />
0X03 (3)<br />
N/A<br />
CODEC INPUT SIGNAL PATHS<br />
CONVERTER<br />
0X02 (2)<br />
0X05 (5)<br />
0X04 (4)<br />
0X03 (03)<br />
0X08 (8)<br />
FUNCTION<br />
CONVERTER<br />
BUILT-IN MIC 0X06 (6)<br />
HEADSET MIC<br />
0X06 (6)<br />
52C7 OUT AUD_SENSE_A<br />
57C8 57B8 PP3V3_S0_AUDIO_F<br />
57A7 56C3 IN<br />
AUD_J1_TIPDET_R<br />
57B8 57B4 57A8 56A7 53B6 52D2 52B7 52A5 GND_AUDIO_CODEC<br />
57D1 57C3<br />
57C8 57B8 PP3V3_S0_AUDIO_F<br />
R6801<br />
300K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
R6802<br />
47K<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
AUD_J1_DET_RC<br />
1<br />
2<br />
R6803<br />
220K<br />
1 2<br />
D 3<br />
Q6800<br />
SSM6N15FEAPE<br />
SOT563<br />
C6801<br />
0.1UF<br />
20% 10V<br />
CERM 402<br />
G<br />
PIN COMPLEX<br />
0X09 (9,A)<br />
0X0C (12)<br />
0X0B (11)<br />
0X0A (10)<br />
0X10 (16)<br />
PIN COMPLEX<br />
0X0D (13,B,RIGHT)<br />
0X0D (13,V22,B,LEFT)<br />
APN:376S0613<br />
5<br />
S<br />
AUD_J1_SLEEVEDET_INV<br />
AUD_OUTJACK_INSERT_L<br />
4<br />
MUTE CONTROL<br />
GPIO_0 AND GPIO_1<br />
GPIO_0 AND GPIO_1<br />
GPIO_3<br />
GPIO_3<br />
N/A<br />
VREF<br />
MIC_BIAS (80%)<br />
MIKEY<br />
PORT A DETECT (HEADPHONES)<br />
Q6801<br />
SSM6N15FEAPE<br />
SOT563<br />
5<br />
G<br />
D<br />
S<br />
R6806<br />
39.2K<br />
1<br />
DET ASSIGNMENT<br />
0X09 (A)<br />
0X09 (A)AND UI ELEMENT<br />
N/A<br />
N/A<br />
0X0D (B)<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
AUD_PORTA_DET_L<br />
3<br />
4<br />
DET ASSIGNMENT<br />
N/A<br />
MIKEY<br />
PORT B DETECT(SPDIF DELEGATE)<br />
NC<br />
Q6801<br />
SSM6N15FEAPE<br />
SOT563<br />
2<br />
G<br />
D<br />
S<br />
1<br />
R6805<br />
20.0K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
AUD_PORTB_DET_L<br />
6<br />
1<br />
NC<br />
57B8 56D8 52D2 52A8 7C5 =PP3V3_S0_AUDIO<br />
43B6<br />
43B6<br />
20C3 20A4<br />
18D7<br />
PULLUPS ON MCP PAGE<br />
IN<br />
BI<br />
OUT<br />
IN<br />
57C8 57C3 57B8 57B4 57A8 56A7 53B6 52D2 52B7 52A5<br />
57D1<br />
=I2C_MIKEY_SCL<br />
=I2C_MIKEY_SDA<br />
AUD_I2C_INT_L<br />
AUD_IPHS_SWITCH_EN<br />
GND_AUDIO_CODEC<br />
52C2 OUT AUD_MIC_INP_L<br />
52C2 OUT<br />
AUD_MIC_INN_L<br />
57C8 57C3 57B8 57B4 57A8 56A7 53B6 52D2 52B7 52A5 GND_AUDIO_CODEC<br />
57D1<br />
PORT B LEFT(HEADSET MIC)<br />
HP=80HZ, LP=8.82KHZ<br />
MIKEY<br />
L6880 MIN_LINE_WIDTH=0.10MM<br />
FERR-1000-OHM MIN_NECK_WIDTH=0.10MM<br />
VOLTAGE=3.3V<br />
1<br />
2 PP3V3_S0_HS_RX<br />
DRC MIKEY<br />
0402<br />
MIKEY<br />
CRITICAL<br />
C6886<br />
0.1UF<br />
1 2<br />
10%<br />
25V<br />
X5R<br />
402<br />
CRITICAL<br />
MIKEY<br />
C6880<br />
1UF<br />
10%<br />
6.3V<br />
CERM<br />
402<br />
MIKEY<br />
R6880 1<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
MIKEY<br />
CRITICAL<br />
C6883<br />
0.1UF<br />
1<br />
2<br />
10%<br />
25V<br />
X5R<br />
402<br />
2<br />
XW6880<br />
SM<br />
1 2<br />
6<br />
5<br />
7<br />
SCL<br />
SDA<br />
INT*<br />
MIKEY<br />
R6883<br />
100K<br />
1<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
3<br />
MIKEY<br />
AVDD<br />
U6880<br />
CD3275<br />
DRC<br />
8 ENABLE<br />
GND<br />
4<br />
9<br />
MICBIAS<br />
DETECT<br />
BYPASS<br />
THM<br />
11<br />
APN:353S2256<br />
1<br />
2<br />
10<br />
HS_MIC_BIAS<br />
HS_SW_DET<br />
HS_RX_BP<br />
MIKEY<br />
C6881 1<br />
0.01UF<br />
16V<br />
MIKEY<br />
10%<br />
402 CERM<br />
2<br />
1<br />
R6881<br />
1K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
MIKEY<br />
R6884<br />
2.2K<br />
HS_MIC_HI_RC<br />
1<br />
2<br />
5%<br />
1/16W<br />
1 MIKEY MF-LF<br />
402<br />
C6884<br />
0.0082UF<br />
10% 25V<br />
2 X7R 402<br />
CRITICAL<br />
MIKEY<br />
1<br />
R6882<br />
2.2K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
1<br />
2<br />
MIKEY<br />
C6885<br />
27PF<br />
50V<br />
2<br />
5%<br />
CERM 402<br />
CRITICAL<br />
MIKEY<br />
CRITICAL<br />
C6882<br />
2.2UF<br />
20%<br />
6.3V<br />
TANT<br />
402<br />
GND_AUDIO_CODEC 52A5 52B7 52D2 53B6 56A7 57A8<br />
57B4 57B8 57C3 57C8<br />
HS_MIC_HI<br />
HS_MIC_LO<br />
IN<br />
IN<br />
56D3<br />
56D3<br />
D<br />
C<br />
B<br />
A<br />
57C6 56C3<br />
IN<br />
57D3 56D8 52D2 52A8 7C5<br />
AUD_J1_SLEEVEDET_R<br />
57C3 57B4 57A8 56A7 53B6 52D2 52B7 52A5 GND_AUDIO_CODEC<br />
57D1 57C8<br />
IN<br />
R6804<br />
220K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
MIN_LINE_WIDTH=0.10MM<br />
MIN_NECK_WIDTH=0.10MM<br />
57C8 PP3V3_S0_AUDIO_F<br />
VOLTAGE=3.3V<br />
=PP3V3_S0_AUDIO<br />
PLACE L6800/C6800 CLOSE TO JACK TRANS. AREA<br />
57C8 56C3 AUD_J1_TIPDET_R<br />
57D1 57C8 57C3 57B8 57B4 56A7 53B6 52D2 52B7 52A5 GND_AUDIO_CODEC<br />
1<br />
2<br />
1<br />
2<br />
C6802<br />
0.01UF<br />
10%<br />
16V<br />
CERM<br />
402<br />
L6862<br />
FERR-1000-OHM<br />
1<br />
0402<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
Q6800<br />
SSM6N15FEAPE<br />
SOT563<br />
2<br />
C6861<br />
1<br />
0.1UF<br />
10V 20%<br />
402 CERM 2<br />
2<br />
G<br />
R6860<br />
15K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
D<br />
S<br />
6<br />
1<br />
EXTRACTION NOTIFICATION CKT<br />
SSM6N15FEAPE<br />
TIPDET_FILT<br />
Q6802<br />
SOT563<br />
2 G<br />
C6860<br />
0.1UF<br />
20%<br />
10V<br />
CERM<br />
402<br />
D 6<br />
S 1<br />
57C8 56C3 AUD_J1_SLEEVEDET_R<br />
R6864<br />
220K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
Q6802<br />
SSM6N15FEAPE<br />
SOT563<br />
AUD_J1_TIPDET_INV<br />
5 G<br />
D 3<br />
S 4<br />
R6865<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
AUD_PERPH_DET_R<br />
R6861<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
AUD_IP_PERIPHERAL_DET OUT 16B6<br />
52C2<br />
IN<br />
AUD_CODEC_MICBIAS<br />
57C8 57C3 57B8 57B4 57A8 56A7 53B6 52D2 52B7 52A5 GND_AUDIO_CODEC<br />
57D1<br />
52C2 OUT AUD_MIC_INP_R<br />
52C2 OUT AUD_MIC_INN_R<br />
57C8 57C3 57B8 57B4 57A8 56A7 53B6 52D2 52B7 52A5 GND_AUDIO_CODEC<br />
57D1<br />
XW6851<br />
SM<br />
1<br />
2<br />
CRITICAL<br />
C6851<br />
0.1UF<br />
1<br />
10%<br />
25V<br />
X5R<br />
402<br />
2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
CRITICAL<br />
C6850<br />
0.1UF<br />
1 2<br />
10%<br />
25V<br />
X5R<br />
402<br />
R6853<br />
2.4K<br />
1 2<br />
1%<br />
1/16W<br />
MF<br />
402-1<br />
PORT B RIGHT(BUILT-IN MIC)<br />
R6850<br />
100<br />
1 2 MIC_BIAS_FILT<br />
1 CRITICAL<br />
C6852<br />
2.2UF<br />
20%<br />
2 6.3V<br />
TANT<br />
1<br />
402<br />
R6852<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
BI_MIC_HI_F<br />
BI_MIC_LO_F<br />
HP=80HZ<br />
R6851<br />
2.4K<br />
1<br />
2<br />
1%<br />
1/16W<br />
MF<br />
402-1<br />
CRITICAL 1<br />
C6853<br />
0.001UF<br />
50V 10%<br />
402 CERM<br />
2<br />
1<br />
2<br />
CRITICAL<br />
C6854<br />
27PF<br />
5% 50V<br />
CERM 402<br />
L6850<br />
FERR-1000-OHM<br />
1 2<br />
L6851<br />
FERR-1000-OHM<br />
1<br />
0402<br />
0402<br />
2<br />
BI_MIC_HI<br />
BI_MIC_LO<br />
BI_MIC_SHIELD<br />
SYNC_MASTER=AUDIO<br />
IN<br />
IN<br />
IN<br />
6D7 56C2<br />
6D7 56C2<br />
6D7 56C2<br />
AUDIO: JACK TRANSLATORS<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
SYNC_DATE=03/20/2009<br />
B<br />
A<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
57 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
MagSafe DC Power Jack<br />
D<br />
CRITICAL<br />
J6900<br />
78048-0573<br />
M-RT-SM<br />
518S0656<br />
1<br />
2<br />
3<br />
4<br />
5 6B3 ADAPTER_SENSE<br />
R6928<br />
0<br />
1<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
6C3 PP18V5_DCIN_FUSE<br />
MIN_LINE_WIDTH=1mm<br />
MIN_NECK_WIDTH=0.20mm<br />
VOLTAGE=18.5V<br />
1<br />
C6905<br />
0.01UF<br />
20%<br />
50V<br />
2<br />
CERM<br />
603<br />
CRITICAL<br />
F6905<br />
6AMP-24V<br />
1 2<br />
1206-1<br />
40B8<br />
BI<br />
R6929<br />
2.0K<br />
402<br />
MF-LF<br />
1/16W<br />
5%<br />
SYS_ONEWIRE<br />
1 2<br />
ONEWIRE_PU<br />
1<br />
VCC<br />
U6900<br />
MAX9940<br />
SC70-5<br />
4 INT<br />
EXT 5<br />
SMC_BC_ACOK_VCC<br />
4<br />
Y<br />
SOT665<br />
TC7SZ08AFEAPE<br />
5<br />
2<br />
A<br />
U6901<br />
B<br />
3<br />
=PP18V5_DCIN_CONN<br />
=PP3V42_G3H_ONEWIRE<br />
7D1<br />
1<br />
1<br />
C6908<br />
0.1UF<br />
2 10V<br />
CERM<br />
402<br />
SMC_BC_ACOK<br />
20% PLACEMENT_NOTE=PLACE NEAR U6901<br />
40C5 41B2 41D5<br />
7D2 58C8<br />
D<br />
GND<br />
NC<br />
2<br />
3<br />
NC<br />
1-Wire OverVoltage Protection<br />
ADAPTER_SENSE_R<br />
BIL CONNECTOR<br />
C<br />
58C2 7D1<br />
=PP3V42_G3H_BATT<br />
1 2<br />
R6960<br />
10K<br />
1/16W<br />
402<br />
MF-LF<br />
5%<br />
516S0523<br />
CRITICAL<br />
J6955<br />
CPB6312-0101F<br />
F-ST-SM<br />
14 13<br />
C<br />
58D1 7D2 =PP18V5_DCIN_CONN<br />
59A3 58A7 6A7 BATT_POS_F<br />
MIN_LINE_WIDTH=0.6 MM<br />
MIN_NECK_WIDTH=0.3 mm<br />
VOLTAGE=12.6V<br />
R6905<br />
47<br />
1 2<br />
5%<br />
1/8W<br />
MF-LF<br />
805<br />
PPDCIN_S5_P3V42G3H<br />
MIN_LINE_WIDTH=0.3 mm<br />
MIN_NECK_WIDTH=0.3 mm<br />
VOLTAGE=18.5V<br />
CRITICAL<br />
D6905<br />
HN2D01JEAPE<br />
SOT665<br />
1 5<br />
3<br />
4<br />
2<br />
NC<br />
NC<br />
3.425V "G3Hot" Supply<br />
Supply needs to guarantee 3.31V delivered to SMC VRef generator<br />
PPVIN_G3H_P3V42G3H<br />
MIN_LINE_WIDTH=0.4 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
P3V42G3H_BOOST<br />
VOLTAGE=18.5V<br />
DIDT=TRUE<br />
TO SMC<br />
C6954 1 2<br />
0.001UF<br />
10%<br />
50V<br />
CERM<br />
402<br />
SMC_BIL_BUTTON_L<br />
58A6 43C3 BI<br />
58A6 43C3 BI<br />
=SMBUS_BATT_SDA<br />
=SMBUS_BATT_SCL<br />
C6953<br />
1<br />
47PF 5%<br />
50V<br />
CERM<br />
402<br />
2<br />
C6952<br />
47PF<br />
5%<br />
50V<br />
CERM<br />
402<br />
1<br />
2<br />
NC<br />
2 1<br />
4 3<br />
6 5<br />
8<br />
10<br />
12<br />
7<br />
9<br />
11<br />
16 15<br />
58C4 7D1<br />
NC<br />
=PP3V42_G3H_BATT<br />
6A7 SMC_LID_R<br />
C6951<br />
1<br />
0.1UF<br />
10%<br />
25V<br />
X5R<br />
2<br />
402<br />
1<br />
2<br />
1<br />
1/16W<br />
C6955<br />
0.001UF<br />
10%<br />
50V<br />
CERM<br />
402<br />
R6961<br />
100<br />
5%<br />
MF-LF<br />
2<br />
402<br />
SMC_LID<br />
40B5 41C2 48A5<br />
B<br />
C6990<br />
10UF<br />
10%<br />
25V<br />
X5R<br />
805<br />
1<br />
2<br />
NC<br />
VIN<br />
BOOST<br />
U6990<br />
LT3470A<br />
8 SHDN* DFN SW 4<br />
BIAS 2<br />
7 NC<br />
CRITICAL<br />
FB 1<br />
GND<br />
THRM<br />
PAD<br />
6<br />
3<br />
5<br />
9<br />
C6994 1<br />
0.22uF<br />
20%<br />
6.3V<br />
2<br />
X5R<br />
402<br />
P3V42G3H_SW<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.25 mm<br />
SWITCH_NODE=TRUE DIDT=TRUE<br />
P3V42G3H_FB<br />
2<br />
5%<br />
50V<br />
CERM<br />
402<br />
1<br />
1<br />
C6995<br />
22pF<br />
CRITICAL<br />
L6995<br />
33UH<br />
CDPH4D19FHF-SM<br />
2<br />
<br />
1<br />
R6995<br />
348K<br />
1%<br />
1/16W<br />
MF-LF<br />
402 2<br />
<br />
1<br />
R6996<br />
200K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
=PP3V42_G3H_REG<br />
Vout = 3.425V<br />
250MA MAX OUTPUT<br />
(Switcher limit)<br />
CRITICAL<br />
1<br />
C6999<br />
22UF<br />
2 6.3V<br />
20%<br />
CERM<br />
805<br />
7D2<br />
B<br />
A<br />
518-0359<br />
P1<br />
P2<br />
P3<br />
P4<br />
P5<br />
P6<br />
P7<br />
P8<br />
P9<br />
SHLD_PIN<br />
SHLD_PIN<br />
SHLD_PIN<br />
SHLD_PIN<br />
CRITICAL<br />
J6950<br />
BAT-<strong>K24</strong><br />
M-RT-TH<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10<br />
11<br />
12<br />
13<br />
BATTERY CONNECTOR<br />
=SMBUS_BATT_SCL<br />
6A7 SYS_DETECT_L<br />
=SMBUS_BATT_SDA<br />
CRITICAL<br />
RCLAMP2402B<br />
SC-75<br />
59A3 58B8 6A7 BATT_POS_F<br />
43C3 58C3<br />
1D6950<br />
3<br />
2<br />
R6950<br />
1<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
43C3 58C3<br />
C6950<br />
1<br />
0.1UF<br />
10%<br />
25V<br />
X5R 2<br />
402<br />
Vout = 1.25V * (1 + Ra / Rb)<br />
SYNC_MASTER=YUNWU<br />
DC-In & Battery Connectors<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=12/11/2008<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
58<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
8 7 6 5 4 3 2 1
D<br />
C<br />
B<br />
7C1<br />
=PP18V5_G3H_CHGR<br />
1 2<br />
CHGR_DCIN<br />
59C5<br />
C7010 1<br />
0.1UF<br />
10%<br />
25V<br />
X5R 2<br />
402<br />
59C4 59B6<br />
8 7 6 5 4 3 2 1<br />
D7010<br />
1SS418<br />
SOD-723-HF<br />
CRITICAL<br />
R7010 1<br />
30.1K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R7011<br />
GND_CHGR_SGND<br />
1<br />
9.31K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
C7063 1<br />
(CHGR_ACIN)<br />
C7044<br />
0.01UF<br />
2 CERM<br />
16V 10%<br />
402<br />
AMON PULLDOWN LOGIC<br />
1<br />
0.1UF<br />
10%<br />
25V<br />
X5R<br />
402<br />
PBUS SUPPLY / BATTERY CHARGER<br />
2<br />
0.033UF<br />
R70981<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402 2<br />
S<br />
G<br />
D<br />
VCC<br />
3 GND<br />
CHGR_LOWCURRENT_REF<br />
59A8 1 2 CHGR_VDD 1 2 CHGR_VDDP<br />
10<br />
5%<br />
4.7 R7040 1<br />
1/16W<br />
C7041<br />
C7040<br />
XW7020<br />
5%<br />
MF-LF<br />
SM<br />
1UF<br />
1/16W<br />
1UF<br />
1 402 59D5 59A8 7D1 =PP3V42_G3H_CHGR<br />
2 1 2<br />
10%<br />
MF-LF<br />
10%<br />
10V<br />
X5R<br />
402<br />
2<br />
10V<br />
C7047 1<br />
X5R<br />
1 CRITICAL<br />
402-1<br />
1 CHGR_CSIP_XW7020<br />
402-1 C7024<br />
R7020<br />
1UF<br />
0.047UF R7021<br />
10%<br />
10%<br />
0.02<br />
10V<br />
0.5%<br />
X5R 2<br />
10V 10<br />
CERM 2 5%<br />
1W<br />
402-1<br />
402 1/16W XW7021<br />
VDD VDDP<br />
2 0612-1 MF<br />
MF-LF<br />
SM<br />
402<br />
1 2<br />
1 2<br />
12 VHST<br />
AGATE 1 CHGR_AGATE<br />
CHGR_CSIN_XW7021<br />
43B3 =SMBUS_CHGR_SCL 11 SCL<br />
CSIP 28 CHGR_CSIP<br />
10<br />
CRITICAL<br />
SDA<br />
CSIN<br />
1 C7061<br />
0.1UF 1 C7062<br />
43B3 =SMBUS_CHGR_SDA<br />
27 CHGR_CSIN<br />
U7000<br />
0.1UF<br />
10%<br />
10%<br />
BGATE 16<br />
25V<br />
25V<br />
NC 4<br />
QFN 59A3 CHGR_BGATE<br />
VREF<br />
2 X5R<br />
DCIN<br />
402 2 X5R<br />
5<br />
2 CHGR_DCIN<br />
402<br />
59D8<br />
CHGR_ACIN<br />
3 ACIN<br />
GND_CHGR_SGND 59B6 59B8<br />
BOOT 25 CHGR_BOOT<br />
5<br />
DIDT=TRUE<br />
CHGR_ICOMP ICOMP<br />
UGATE 24 CHGR_UGATE<br />
4<br />
MIN_LINE_WIDTH=0.5 MM<br />
CHGR_VCOMP 7 VCOMP<br />
PHASE 23 CHGR_PHASE<br />
MIN_NECK_WIDTH=0.2 MM<br />
DIDT=TRUE<br />
CHGR_VNEG 8 VNEG<br />
C7025<br />
LGATE 21 CHGR_LGATE<br />
1<br />
CHGR_CSOP 18 CSOP<br />
0.1UF<br />
TRKL* 13 NC<br />
10%<br />
CHGR_CSON 17 CSON<br />
25V<br />
AMON 9<br />
59D4<br />
CHGR_AMON<br />
X5R<br />
45B3<br />
1<br />
402 2<br />
1 2 3<br />
59B8<br />
R7045<br />
BMON<br />
56.2K<br />
C7043<br />
15 CHGR_BMON 45A6<br />
1% 0.1UF<br />
ACOK 14 =CHGR_ACOK 41D4<br />
1/16W<br />
MF-LF<br />
1 2<br />
MIN_LINE_WIDTH=0.5 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
402<br />
2<br />
DIDT=TRUE<br />
16V<br />
10%<br />
5<br />
CHGR_VCOMP_R<br />
X5R<br />
C7045<br />
1<br />
402<br />
0.001UF<br />
10%<br />
4<br />
50V<br />
CERM 2<br />
MIN_LINE_WIDTH=0.5 MM<br />
402<br />
MIN_NECK_WIDTH=0.2 MM<br />
DIDT=TRUE<br />
1 2<br />
R7046 1<br />
3.01K 1%<br />
1/16W<br />
MF-LF<br />
402 2<br />
CHGR_VNEG_R<br />
C7046 1 2<br />
470PF<br />
10%<br />
50V<br />
CERM<br />
402<br />
1 2 3<br />
CRITICAL<br />
Q7000<br />
HAT1127H<br />
LFPAK-SM<br />
4<br />
5<br />
CHGR_SGATE<br />
PPVDCIN_G3H_PRE2<br />
(CHGR_CSOP)<br />
(CHGR_CSON)<br />
19<br />
THRM_PAD<br />
29<br />
R7001<br />
62K<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
ISL6258A<br />
AGND<br />
6<br />
26<br />
20<br />
PGND<br />
22<br />
XW7000<br />
SM<br />
(CHGR_CSO_R_N)<br />
R7060<br />
1<br />
57.6K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R7061 1<br />
1.82K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
C7026<br />
0.001UF<br />
10%<br />
2<br />
50V<br />
X7R<br />
402<br />
1<br />
R7023<br />
5<br />
2<br />
1<br />
2<br />
4<br />
C7060<br />
0.1UF 10%<br />
25V<br />
X5R<br />
402<br />
CRITICAL<br />
U7060<br />
TL331<br />
SOT23-5<br />
CRITICAL<br />
Q7021<br />
RJK0305DPB<br />
LFPAK-HF<br />
1 2 3<br />
Q7020<br />
LFPAK-HF<br />
1<br />
2<br />
CRITICAL<br />
D<br />
R7062 1<br />
62K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
RJK0305DPB<br />
C7042 1<br />
10%<br />
16V<br />
X5R<br />
CRITICAL<br />
402 2<br />
L7000<br />
59C4 59B8<br />
GND_CHGR_SGND<br />
MIN_LINE_WIDTH=0.6 MM<br />
MIN_NECK_WIDTH=0.3 MM<br />
=PP3V42_G3H_CHGR<br />
59C6 59A8 7D1<br />
59C5<br />
45B3<br />
59B8<br />
CHGR_AMON<br />
CHGR_LOWCURRENT_GATE<br />
1 2<br />
4.7UH-9.5A<br />
IHLP4040DZ-SM<br />
R7031<br />
10<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
5<br />
CRITICAL<br />
Q7001<br />
HAT1127H<br />
LFPAK-SM<br />
G<br />
S<br />
R7099<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
MIN_NECK_WIDTH=0.3 MM<br />
MIN_LINE_WIDTH=0.6 MM<br />
PP18V5_S5_CHGR_SW_R<br />
CRITICAL CRITICAL<br />
1<br />
1<br />
C7020 C7021<br />
22UF 22UF 1UF<br />
20%<br />
20%<br />
10%<br />
25V<br />
25V<br />
2<br />
25V<br />
POLY-TANT<br />
2<br />
POLY-TANT X5R<br />
CASE-D2-SM CASE-D2-SM 603-1<br />
R7047<br />
10<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
4<br />
3<br />
1 2<br />
100K<br />
CHGR_LOWCURRENT_GATE_R 1 2<br />
MIN_LINE_WIDTH=0.6 MM<br />
MIN_NECK_WIDTH=0.25 MM<br />
PPVBAT_G3H_CHGR_REG<br />
CRITICAL<br />
1<br />
C7008<br />
33UF<br />
2 20%<br />
16V<br />
POLY-TANT<br />
CASED2E-SM<br />
80D3 45A8<br />
80D3 45A8<br />
PPVDCIN_G3H_PRE<br />
MIN_LINE_WIDTH=0.6 MM<br />
MIN_NECK_WIDTH=0.3 MM<br />
CHGR_CSO_R_P<br />
CHGR_CSO_R_N<br />
C7022<br />
1<br />
2<br />
CRITICAL<br />
R7008<br />
0.01<br />
0.5%<br />
1W<br />
MF<br />
0612-1<br />
1 2<br />
3 4<br />
C7023<br />
1UF<br />
10%<br />
25V<br />
X5R<br />
603-1<br />
CRITICAL<br />
1<br />
1<br />
0.001UF<br />
20%<br />
50V<br />
2 CERM<br />
402<br />
2<br />
F7000<br />
7AMP<br />
1206<br />
C7027<br />
C7028<br />
1<br />
C7011 1<br />
1UF 0.001UF<br />
10%<br />
20%<br />
25V<br />
50V<br />
2 X5R<br />
603-1 2<br />
CERM<br />
402<br />
=PPBUS_G3H<br />
PPVBAT_G3H_CHGR_OUT<br />
TO SYSTEM<br />
PWM FREQ. = 400 kHz<br />
MAX CURRENT = 7A<br />
(??? limited)<br />
7C2<br />
59A5<br />
D<br />
C<br />
B<br />
59D4 59C5 45B3<br />
CHGR_AMON<br />
A<br />
59C6 CHGR_VDD<br />
59D5 59C6 7D1<br />
Q7070<br />
SSM6N15FEAPE<br />
R7073<br />
1<br />
1K<br />
5%<br />
1/16W<br />
MF-LF<br />
402 2<br />
=PP3V42_G3H_CHGR<br />
R7074<br />
1<br />
1M 5%<br />
1/16W<br />
MF-LF<br />
402 2<br />
SOT563<br />
5 G<br />
Q7070<br />
SSM6N15FEAPE D 6<br />
SOT563<br />
2 G S 1<br />
CHGR_VDD_L<br />
D 3<br />
S 4<br />
NOSTUFF<br />
1<br />
R7075<br />
1M 5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
BATTERY CHARGE LIMITING FETS<br />
59C1<br />
PPVBAT_G3H_CHGR_OUT<br />
1 C7050 1 C7051<br />
0.01uF<br />
10%<br />
0.1UF 10%<br />
2<br />
16V<br />
CERM 2<br />
16V<br />
X5R<br />
402<br />
402<br />
3<br />
2<br />
1<br />
Q7050<br />
SI7137DP<br />
S<br />
G<br />
4<br />
SO-8<br />
D<br />
5<br />
CHGR_BGATE<br />
CRITICAL<br />
BATT_POS_F<br />
59C5<br />
6A7 58A7 58B8<br />
PBUS Supply/Battery Charger<br />
SYNC_MASTER=RAYMOND<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=01/31/2008<br />
A<br />
CHGR_VDD_R<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
59<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
81<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
5V_S3/3.3V_S5 POWER SUPPLY<br />
D<br />
VOUT = (2 * RA / RB) + 2<br />
VOUT = (2 * RC / RD) + 2<br />
ROUTING NOTE:<br />
Place XW7203 by Pin1 OF L7260.<br />
XW7203<br />
SM<br />
2 1<br />
5V_S3_VFB_XW7203<br />
<br />
R7267<br />
15.0K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1 2<br />
<br />
R7268<br />
10K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1 2<br />
<br />
R7269<br />
10K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1 2<br />
R7270<br />
6.49K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1 2<br />
3V3S5_VFB_R7270<br />
XW7204<br />
SM<br />
2 1<br />
ROUTING NOTE:<br />
Place XW7204 by Pin 2 of L7220.<br />
C<br />
ROUTING NOTE:<br />
Place XW7202 by C7292.<br />
60C7 7C1<br />
=PPVIN_S3_5VS3<br />
XW7202<br />
SM<br />
2 1<br />
66D8 40D5 6C3<br />
1<br />
SMC_PM_G2_EN<br />
C7272<br />
1UF<br />
10%<br />
2 25V<br />
X5R<br />
603-1<br />
GND_5V3V3S5_SGND<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
60B5<br />
R7273<br />
1<br />
2<br />
XW7205<br />
SM<br />
2 1<br />
ROUTING NOTE:<br />
Place XW7205 by C7252.<br />
C<br />
B<br />
MAX CURRENT = 8A<br />
PWM FREQ. = 300 KHZ<br />
=PP5V_S3_REG<br />
7C4<br />
VOLTAGE=5V<br />
C7293<br />
1<br />
0.001UF<br />
20%<br />
50V<br />
2 CERM<br />
402<br />
1<br />
C7290<br />
1<br />
10UF<br />
20%<br />
2 6.3V<br />
X5R<br />
603<br />
C7282<br />
0.001UF<br />
20%<br />
50V<br />
2 CERM<br />
402<br />
1<br />
C7291<br />
220UF<br />
20%<br />
2 6.3V<br />
ELEC<br />
D1A-SM<br />
60C6 7C1<br />
CRITICAL<br />
=PPVIN_S3_5VS3<br />
CRITICAL<br />
1C7280<br />
39UF-0.027OHM<br />
20%<br />
2 16V<br />
POLY<br />
B1A-SM<br />
L7260<br />
1<br />
C7281<br />
10%<br />
2 25V<br />
X5R<br />
603-1<br />
CRITICAL<br />
4.7UH-13A-15MOHM<br />
PCMB104E4R7-SM<br />
1<br />
1UF<br />
CRITICAL<br />
Q7260<br />
SI7110DN<br />
PWRPK-1212-8-HF<br />
2<br />
CRITICAL<br />
Q7261<br />
SI7108DN<br />
PWRPK-1212-8-HF<br />
5<br />
D<br />
S<br />
3 2 1<br />
5<br />
D<br />
S<br />
3 2 1<br />
G 4<br />
G 4<br />
5VS3_3V3S5_VREF<br />
20%<br />
2 6.3V<br />
C7271<br />
X5R<br />
603<br />
C7260 10%<br />
VIN VREF<br />
0.1UF<br />
10%<br />
2 10V<br />
14<br />
SKIPSEL<br />
VREG3<br />
8<br />
CERM 10%<br />
16V<br />
402<br />
16V<br />
X5R<br />
4<br />
TONSEL<br />
VREG5<br />
17<br />
X5R<br />
402<br />
5V3V3S5_REG5<br />
402<br />
2 1 MIN_LINE_WIDTH=0.6 MM<br />
CRITICAL<br />
5V_S3_VBST<br />
22<br />
VBST1<br />
VBST2<br />
9 3V3S5_VBST<br />
DIDT=TRUE 2 1<br />
MIN_NECK_WIDTH=0.2 MM DIDT=TRUE<br />
U7200<br />
5V_S3_DRVH<br />
21<br />
DRVH1<br />
DRVH2<br />
10 3V3S5_DRVH<br />
MIN_LINE_WIDTH=0.6 MM<br />
MIN_LINE_WIDTH=0.6<br />
QFN<br />
MM DIDT=TRUE<br />
MIN_NECK_WIDTH=0.2 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
DIDT=TRUE<br />
5V_S3_LL<br />
20<br />
LL1<br />
LL2<br />
11 3V3S5_LL<br />
MIN_LINE_WIDTH=0.6 MM<br />
MIN_LINE_WIDTH=0.6 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
5V_S3_DRVL<br />
19<br />
DRVL1<br />
DRVL2<br />
12<br />
MIN_NECK_WIDT=0.2 DIDT=TRUE<br />
3V3S5DRVL<br />
DIDT=TRUE<br />
DIDT=TRUE<br />
5V_S3_VO1<br />
24<br />
VO1<br />
VO2<br />
7 3V3S5VO2<br />
DIDT=TRUE<br />
5V_S3_VFB<br />
5V_S3_ENTRIP<br />
1 R7271<br />
86.6K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
16<br />
2<br />
VFB1<br />
VFB2<br />
5 3V3S5_VFB<br />
1<br />
ENTRIP1<br />
GND<br />
15<br />
TPS51125<br />
3<br />
ENTRIP2<br />
6<br />
VCLK<br />
18<br />
NC<br />
PGOOD<br />
23<br />
EN0<br />
13 5V3V3_REG_EN<br />
THRM_PAD<br />
25<br />
5V3V3S5_REG3<br />
3V3S5_ENTRIP<br />
C7273<br />
1<br />
10UF<br />
20%<br />
2 6.3V<br />
X5R<br />
603<br />
1<br />
C7270<br />
10UF<br />
1<br />
2<br />
C7220<br />
0.1UF<br />
R7272<br />
75K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
7C1<br />
1<br />
8<br />
=PPVIN_S5_3V3S5<br />
9 4 3 2<br />
Q1<br />
Q2<br />
7 6 5<br />
10<br />
SW<br />
C7241<br />
1<br />
1<br />
1<br />
1UF<br />
39UF-0.027OHM<br />
10%<br />
20%<br />
20%<br />
2 25V<br />
X5R<br />
2 16V<br />
2<br />
50V<br />
POLY<br />
CERM<br />
603-1 B1A-SM<br />
402<br />
Q7220<br />
FDMS9600S<br />
MLP<br />
CRITICAL<br />
L7220<br />
1 2<br />
CRITICAL<br />
4.7UH-5.5A<br />
IHLP2525CZ<br />
CRITICAL<br />
C7240<br />
1<br />
C7242<br />
0.001UF<br />
CRITICAL<br />
C7251<br />
150UF<br />
20%<br />
2 6.3V<br />
POLY<br />
B1A-SM<br />
PWM FREQ. = 375 KHZ<br />
MAX CURRENT = 4A<br />
1<br />
C7250<br />
10UF<br />
20%<br />
2 6.3V<br />
X5R<br />
603<br />
=PP3V3_S5_REG<br />
1<br />
C7253<br />
0.001UF<br />
20%<br />
50V<br />
2 CERM<br />
402<br />
VOLTAGE=3.3V<br />
7B4<br />
B<br />
A<br />
=P5VS3_EN_L<br />
66C6 IN<br />
2 G<br />
D 6<br />
S 1<br />
Q7221<br />
SSM6N15FEAPE<br />
SOT563<br />
66D6<br />
60C4<br />
=P3V3S5_EN_L 5 G<br />
IN<br />
GND_5V3V3S5_SGND<br />
D 3<br />
S 4<br />
Q7221<br />
SSM6N15FEAPE<br />
SOT563<br />
1<br />
0.22UF<br />
051-7898<br />
1 2<br />
XW7201<br />
SM<br />
ROUTING NOTE:<br />
P5V3V3_PGOOD<br />
Place XW7201 between Pin 15 and Pin 25 of U7200.<br />
66A5<br />
5V/3.3V SUPPLY<br />
SYNC_MASTER=RAYMOND<br />
SYNC_DATE=02/08/2008<br />
NOTICE OF PROPRIETARY PROPERTY<br />
A<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
REV.<br />
4.7.0<br />
OF<br />
60 81<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
25D3 7C4 =PPVTT_S3_DDR_BUF<br />
1.5V/0.75V(DDR3) POWER SUPPLY<br />
VOUT = 0.75V * (1 + RA / RB)<br />
<br />
1 2<br />
C7340<br />
0.033UF<br />
10%<br />
16V<br />
X5R<br />
402<br />
1 2<br />
R7322<br />
20K<br />
0.1%<br />
1/16W<br />
MF<br />
402<br />
1V5S3_VDDQSET<br />
C7303<br />
R7321 100PF<br />
20K<br />
0.1%<br />
1/16W<br />
MF<br />
402<br />
1 2<br />
NO STUFF<br />
1 2<br />
5%<br />
50V<br />
CERM<br />
402<br />
1 C7301<br />
10UF<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
603<br />
D<br />
C<br />
=PP0V75_S0_REG<br />
7C8<br />
67A3 24C1<br />
66C6<br />
=DDRVTT_EN<br />
=DDRREG_EN<br />
1<br />
XW7303<br />
22UF<br />
1 2<br />
C7300<br />
1UF<br />
10%<br />
10V<br />
X5R<br />
402-1<br />
2<br />
1<br />
SM<br />
CRITICAL<br />
C7307<br />
20%<br />
2 6.3V<br />
X5R-CERM-1<br />
603<br />
1<br />
R7310<br />
10.7K<br />
1%<br />
1/16W<br />
2 402 MF-LF<br />
1V5S3_CS<br />
10<br />
11<br />
16<br />
ROUTING NOTE:<br />
Place XW7303 by C7308.<br />
CRITICAL<br />
1 C7308<br />
22UF<br />
20%<br />
2 6.3V<br />
X5R-CERM-1<br />
603<br />
1V5S3_V5FILT<br />
1V5S3_VTTSNS<br />
6<br />
VDDQSET VTTREF VLDOIN VTT V5FILT VBST V5IN VDDQSNS VTTSNS<br />
S3<br />
S5<br />
COMP<br />
CS<br />
9<br />
5<br />
THRM_PAD<br />
25<br />
23<br />
CRITICAL<br />
U7300<br />
SYM (1 OF 2)<br />
TPS51116<br />
ROUTING NOTE:<br />
CONNECT CS_GND TO<br />
Q7321 PIN1,2.3<br />
USING KEVIN CONNECTION.<br />
CS_GND<br />
17<br />
24<br />
14<br />
1 2<br />
R7307<br />
4.7<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
QFN<br />
GND<br />
3<br />
22<br />
15<br />
PGND<br />
18<br />
=PP5V_S3_1V5S30V75S0<br />
1 C7302<br />
10UF<br />
20%<br />
2 6.3V<br />
X5R<br />
603<br />
8<br />
VTTGND<br />
1<br />
2<br />
1V5S3_VBST<br />
DIDT=TRUE<br />
PGOOD<br />
DRVH<br />
LL<br />
DRVL<br />
MODE<br />
NC0<br />
NC1<br />
13<br />
211V5S3_DRVH<br />
201V5S3_LL<br />
191V5S3_DRVL<br />
4<br />
7 NC<br />
12NC<br />
1<br />
7C3<br />
5%<br />
0 1/16W<br />
MF-LF<br />
402<br />
2<br />
R7300<br />
DIDT=TRUE<br />
1<br />
2<br />
C7309<br />
0.1uF<br />
10%<br />
16V<br />
X5R<br />
402<br />
MIN_LINE_WIDTH=1 mm<br />
MIN_NECK_WIDTH=0.25 mm<br />
DIDT=TRUE<br />
1V5S3_VDDQSNS<br />
1V8S3_VBST_RC<br />
DIDT=TRUE<br />
MIN_LINE_WIDTH=1 mm<br />
MIN_NECK_WIDTH=0.25 mm<br />
DIDT=TRUE<br />
MIN_LINE_WIDTH=1 mm<br />
MIN_NECK_WIDTH=0.25 mm<br />
4<br />
4<br />
G<br />
G<br />
D<br />
5<br />
S<br />
1 2 3<br />
5<br />
D<br />
S<br />
1 2 3<br />
CRITICAL<br />
Q7320<br />
SI7110DN<br />
PWRPK-1212-8-HF<br />
CRITICAL<br />
L7320<br />
1.0UH-13A-5.6M-OHM<br />
SM-IHLP-1<br />
1 2<br />
CRITICAL<br />
Q7321<br />
XW7301<br />
SM<br />
1 2<br />
1<br />
C7342<br />
330UF<br />
20%<br />
SI7108DN 2 2.5V<br />
TANT<br />
PWRPK-1212-8-HF CASE-B2-SM<br />
1<br />
2<br />
ROUTING NOTE:<br />
Place XW7301 by L7320.<br />
1<br />
=PPVIN_S5_1V5S30V75S0<br />
CRITICAL CRITICAL<br />
C7330<br />
1<br />
C7331 C7332 C7333<br />
39UF-0.027OHM 39UF-0.027OHM<br />
16V<br />
20% 2 16V<br />
20%<br />
POLY<br />
POLY<br />
B1A-SM<br />
B1A-SM<br />
VOLTAGE=1.5V<br />
MIN_LINE_WIDTH=1.5 mm<br />
MIN_NECK_WIDTH=0.25 mm<br />
CRITICAL<br />
C7341<br />
10UF<br />
2 6.3V 20%<br />
X5R<br />
603<br />
7C1<br />
1<br />
1<br />
1UF<br />
0.001UF<br />
10%<br />
20%<br />
2 25V<br />
X5R<br />
2 50V<br />
CERM<br />
603-1 402<br />
MAX CURRENT = 12A<br />
PWM FREQ. = 400 KHZ<br />
PUT ONE BULK CAP NEXT TO THE LOAD<br />
=PP1V5_S3_REG<br />
1<br />
CRITICAL<br />
C7343<br />
330UF<br />
20%<br />
2 2.5V<br />
TANT<br />
CASE-B2-SM<br />
1<br />
C7344<br />
0.001UF<br />
20%<br />
2 50V<br />
CERM<br />
402<br />
7D4<br />
C<br />
B<br />
ROUTING NOTE:<br />
PUT 6 VIAS UNDER THE THERMAL PAD<br />
GND_1V5S3_SGND<br />
GND_1V5S3_CSGND<br />
SM<br />
1 2<br />
XW7300<br />
SM<br />
1<br />
2<br />
XW7302<br />
ROUTING NOTE:<br />
Place XW7300 between<br />
Pin 3 and Pin 25<br />
of U7300.<br />
ROUTING NOTE:<br />
Place XW7302 by Q7321.<br />
DDRREG_PGOOD<br />
R7399<br />
100K<br />
66A2<br />
5% 1/16W<br />
MF-LF<br />
402<br />
1 2 =PP3V3_S3_PDCISENS 7D3<br />
B<br />
STATE<br />
S0<br />
S3<br />
S5/G3HOT<br />
PM_SLP_S4_L PM_SLP_S3_L PP1V5_S3<br />
HIGH<br />
HIGH<br />
1.5V<br />
HIGH<br />
LOW<br />
1.5V<br />
LOW LOW<br />
0.0V<br />
PP0V75_S0<br />
0.75V<br />
0.0V<br />
0.0V<br />
A<br />
1.5V/0.75V DDR3 SUPPLY<br />
SYNC_MASTER=RAYMOND<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=01/31/2008<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
61<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
C<br />
B<br />
A<br />
7D5<br />
62D4 62C3 7B1<br />
73B3 20C7<br />
IN<br />
7C5<br />
=PP5V_S0_CPU_IMVP<br />
=PPVIN_S5_CPU_IMVP<br />
PM_DPRSLPVR<br />
=PP3V3_S0_IMVP<br />
1<br />
2<br />
C7405<br />
0.015uF<br />
10%<br />
16V<br />
X7R<br />
402<br />
R7409<br />
1<br />
1K 1%<br />
1/16W<br />
MF-LF<br />
2 402<br />
C7414<br />
470PF<br />
10%<br />
50V<br />
CERM<br />
402<br />
R7414<br />
1<br />
97.6K<br />
1%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
1<br />
2<br />
1 2<br />
1 2<br />
R7412<br />
10<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
R7421 10 5%<br />
1/16W<br />
MF-LF<br />
402<br />
147K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1 2<br />
C7406<br />
0.001UF<br />
10%<br />
50V<br />
CERM<br />
402<br />
1<br />
R7411<br />
255<br />
1%<br />
1/16W<br />
MF-LF<br />
2 402<br />
1<br />
2<br />
1UF<br />
10%<br />
6.3V<br />
CERM<br />
402<br />
(IMVP6_FB)<br />
C7426<br />
1 2<br />
R7420<br />
10 5%<br />
1/16W<br />
MF-LF<br />
402<br />
(IMVP6_COMP)<br />
MIN_LINE_WIDTH<br />
(IMVP6_VW)<br />
NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.<br />
1<br />
2<br />
C7413<br />
220PF 5%<br />
25V<br />
CERM<br />
402<br />
1 2<br />
NO STUFF<br />
R7413<br />
1K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
2<br />
C7496<br />
0.01UF<br />
10%<br />
16V<br />
CERM<br />
402<br />
C7430<br />
1<br />
2<br />
C7407<br />
0.001UF<br />
10%<br />
50V<br />
CERM<br />
402<br />
MIN_NECK_WIDTH<br />
PP5V_S0_IMVP6_VDD<br />
MIN_LINE_WIDTH=0.25 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=5V<br />
PPVIN_S5_IMVP6_VIN<br />
MIN_LINE_WIDTH=0.25 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
R7447<br />
1<br />
0.1uF 1<br />
10%<br />
16V<br />
2.0K<br />
X5R<br />
5%<br />
402<br />
1/16W<br />
2<br />
MF-LF<br />
402<br />
62B7 62A4 GND_IMVP6_SGND<br />
2<br />
20 22 31<br />
NO STUFF NO STUFF<br />
VIN VDD PVCC<br />
R7427<br />
4.02K<br />
R7426<br />
43<br />
VID6<br />
BOOT1<br />
36<br />
73A3 10B6<br />
1% 470K<br />
CPU_VID<br />
1/16W 402 CRITICAL<br />
42 CRITICAL 26<br />
73A3 10B6 CPU_VID<br />
VID5<br />
BOOT2<br />
MF-LF<br />
402<br />
41 U7400<br />
73A3 10B6<br />
VID4<br />
1 2 1 2<br />
CPU_VID<br />
QFN<br />
40<br />
35<br />
10B6<br />
VID3<br />
UGATE1<br />
1<br />
CPU_VID<br />
73A3<br />
R7445<br />
39<br />
10B6 CPU_VID<br />
VID2<br />
NO STUFF<br />
499<br />
73A3<br />
34<br />
PHASE1<br />
C7410<br />
ERT-J0EV474J<br />
38<br />
1%<br />
73A3 10B6 CPU_VID<br />
VID1<br />
1/16W<br />
0.01uF<br />
37<br />
32<br />
MF-LF 73A3 10B6 CPU_VID<br />
VID0<br />
LGATE1<br />
10% IMVP6_NTC_R<br />
2402<br />
16V<br />
33<br />
CERM<br />
PGND1<br />
73B3 13A3 9B2<br />
402<br />
IN<br />
CPU_DPRSTP_L<br />
46<br />
DPRSTP*<br />
73B3 IMVP_DPRSLPVR<br />
45<br />
24<br />
1 2<br />
DPRSLPVR<br />
ISEN1<br />
2<br />
9B2<br />
R7406<br />
IN<br />
CPU_PSI_L<br />
PSI*<br />
NO STUFF<br />
45B3 IMVP6_IMON<br />
3<br />
OUT<br />
IMON<br />
UGATE2<br />
27<br />
0<br />
5%<br />
PHASE2<br />
28<br />
1/16W<br />
48<br />
3V3<br />
MF-LF<br />
CPU_PROCHOT_L 402<br />
(NC) 47<br />
30<br />
CLK_EN*<br />
LGATE2<br />
73C3 41D4 13B6 9C5<br />
1 2<br />
FROM SMC 40D8<br />
44<br />
IN IMVP_VR_ON<br />
VR_ON<br />
29<br />
1<br />
PGND2<br />
24A8 VR_PWRGOOD_DELAY<br />
1 2<br />
OUT<br />
PGOOD<br />
IMVP6_VR_TT 5<br />
VR_TT*<br />
R7408<br />
6<br />
ISEN2<br />
23<br />
IMVP6_NTC NTC<br />
R7410<br />
1<br />
6.81K 1%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
7<br />
SOFT<br />
4<br />
RBIAS<br />
13<br />
VDIFF<br />
12<br />
FB2<br />
11<br />
FB<br />
10<br />
COMP<br />
9<br />
VW<br />
25<br />
NC<br />
OMIT<br />
XW7400<br />
SM<br />
GND<br />
19<br />
VSUM<br />
OCSET<br />
8<br />
18<br />
VO<br />
DROOP<br />
16<br />
17<br />
DFB<br />
14<br />
VSEN<br />
15<br />
RTN<br />
TPAD<br />
DPRSLPVR<br />
IMVP6_LGATE1<br />
(GND)<br />
IMVP6_LGATE2<br />
(GND)<br />
5<br />
1<br />
C7409<br />
1<br />
C7417 1 C7418 1<br />
0.001UF<br />
CRITICAL 33UF 33UF 1UF<br />
20%<br />
DPRSTP* PSI* OPERATION MODE<br />
20%<br />
20%<br />
10%<br />
50VPWM FREQ. = 300 KHZ<br />
2 16V<br />
POLY-TANT<br />
2 16V<br />
25V<br />
Q7400<br />
POLY-TANT<br />
CASED2E-SM CASED2E-SM<br />
2 X5R 2<br />
CERM<br />
402<br />
DIDT=TRUE<br />
4<br />
603-1<br />
0 1 1 2-PHASE CCM RJK0305DPB<br />
MAX CURRENT = 44A<br />
1<br />
1<br />
MIN_LINE_WIDTH MIN_NECK_WIDTH<br />
0.25 MM<br />
0.25 MM<br />
0.25 MM 0.25 MM<br />
0.25 MM 0.25 MM<br />
0.25 MM<br />
0.25 MM<br />
0.25 MM<br />
0.25 MM<br />
1<br />
0<br />
0<br />
1<br />
1-PHASE DCM<br />
0 0 1-PHASE DCM<br />
(IMVP6_VO)<br />
IMVP6 CPU VCORE REGULATOR<br />
62C6<br />
62C6<br />
62C6<br />
62C6<br />
62C6<br />
IMVP6_COMP_RC<br />
IMVP6_VDIFF_RC<br />
IMVP6_PHASE1 1.5 MM 0.25 MM<br />
IMVP6_BOOT1<br />
0.25 MM<br />
0.25 MM<br />
IMVP6_UGATE1 1.5 MM 0.25 MM<br />
IMVP6_LGATE1<br />
1.5 MM<br />
0.25 MM<br />
IMVP6_ISEN1<br />
0.25 MM<br />
0.25 MM<br />
MIN_LINE_WIDTH=0.25 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
PP3V3_S0_IMVP6_3V3<br />
62A4<br />
62C8<br />
62A4<br />
62A4<br />
62A4<br />
62A4<br />
62A4<br />
62A4<br />
62A4<br />
IMVP6_SOFT<br />
IMVP6_RBIAS<br />
IMVP6_VDIFF<br />
IMVP6_FB2<br />
IMVP6_FB<br />
IMVP6_COMP<br />
IMVP6_VW<br />
GND_IMVP6_SGND<br />
VOLTAGE=0V<br />
62C6<br />
62C6<br />
62C6<br />
62C6<br />
62C6<br />
ISL9504BCRZ<br />
21<br />
2<br />
1<br />
49<br />
1 2<br />
NO STUFF<br />
C7432<br />
0.01UF<br />
10%<br />
16V<br />
CERM<br />
402<br />
1 2<br />
1<br />
2<br />
C7433<br />
0.018UF<br />
10%<br />
16V<br />
X7R<br />
402<br />
1 2<br />
C7421<br />
0.22uF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
402<br />
IMVP6_PHASE2<br />
IMVP6_BOOT2<br />
IMVP6_UGATE2<br />
IMVP6_LGATE2<br />
IMVP6_ISEN2<br />
62A4<br />
C7435<br />
10UF<br />
20%<br />
6.3V<br />
X5R<br />
603<br />
1<br />
2<br />
C7431<br />
0.068UF<br />
10%<br />
10V<br />
CERM<br />
402 62A4<br />
1<br />
R7423<br />
0 5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
0<br />
DIDT=TRUE<br />
IMVP6_BOOT1<br />
IMVP6_BOOT2<br />
DIDT=TRUE<br />
IMVP6_UGATE1<br />
IMVP6_PHASE1<br />
IMVP6_VSUM<br />
IMVP6_OCSET<br />
IMVP6_VO<br />
IMVP6_DROOP<br />
IMVP6_RTN<br />
IMVP6_ISEN1<br />
IMVP6_UGATE2<br />
IMVP6_PHASE2<br />
IMVP6_ISEN2<br />
IMVP6_DFB<br />
IMVP6_VSEN<br />
62A8<br />
62A6<br />
1<br />
2<br />
C7427<br />
0.1UF<br />
10%<br />
16V<br />
X5R<br />
402<br />
R7418 R7417<br />
1<br />
1K<br />
1%<br />
1/16W<br />
MF-LF<br />
2 402<br />
1<br />
2<br />
1<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1 2IMVP6_BOOT2_RC<br />
DIDT=TRUE<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
62A8<br />
62A8<br />
62A8<br />
62A8<br />
62A6<br />
62A6<br />
62A6<br />
62A6<br />
62A4<br />
1<br />
5.36K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
0.12UF<br />
10%<br />
10.0V<br />
CERM-X5R<br />
402 2<br />
2<br />
C7428<br />
1-PHASE CCM<br />
C7415<br />
1 0.1UF<br />
10%<br />
16V<br />
2 X5R<br />
402<br />
C7429<br />
1<br />
180pF<br />
5%<br />
2 50V<br />
CERM<br />
402<br />
R7415<br />
1<br />
0.22UF<br />
10% 11K<br />
6.3V 1%<br />
CERM-X5R 1/16W<br />
402<br />
MF-LF<br />
2 402<br />
8 7 6 5 4 3 2 1<br />
R7416<br />
1<br />
13.7K<br />
1%<br />
1/16W<br />
MF-LF<br />
2 402<br />
2<br />
ERT-J1VR103J<br />
NO STUFF<br />
1 C7400<br />
0.0022UF<br />
10%<br />
50V<br />
2 CERM<br />
402<br />
1<br />
2<br />
NO STUFF<br />
C7402<br />
0.0022UF<br />
10%<br />
50V<br />
CERM<br />
402<br />
(IMVP6_VO)<br />
R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED<br />
R7422<br />
R7425<br />
C7434<br />
1<br />
0 5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
CPU_VCCSENSE_P<br />
CPU_VCCSENSE_N<br />
2<br />
R7424<br />
62A4<br />
62A4<br />
62A4<br />
62A4<br />
IMVP6_BOOT1_RC<br />
DIDT=TRUE<br />
10B5 73A3<br />
10A5 73A3<br />
NO STUFF<br />
C7416<br />
0.001UF<br />
10%<br />
50V<br />
CERM<br />
402<br />
R7430<br />
1<br />
2<br />
1<br />
3.92K<br />
1%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
IMVP6_VO_R<br />
1<br />
62C6<br />
62C6<br />
62C8 62B7<br />
62C6<br />
62C6<br />
62B6<br />
62C7<br />
62C7<br />
62B7<br />
62B7<br />
62B7<br />
62B7<br />
62B7<br />
62B6<br />
62B5<br />
CRITICAL<br />
R7431<br />
10KOHM-5%<br />
0603-LF<br />
62D8 62C3 7B1<br />
=PPVIN_S5_CPU_IMVP<br />
DIDT=TRUE<br />
DIDT=TRUE<br />
4<br />
DIDT=TRUE<br />
DIDT=TRUE<br />
4<br />
5<br />
1 2 3<br />
4<br />
DIDT=TRUE<br />
5<br />
123<br />
123<br />
CRITICAL<br />
Q7401<br />
LFPAK-HF<br />
RJK0328DPB<br />
LFPAK-HF<br />
MIN_LINE_WIDTH MIN_NECK_WIDTH<br />
IMVP6_OCSET<br />
0.25 MM<br />
0.20 MM<br />
IMVP6_VSUM<br />
0.25 MM 0.20 MM<br />
GND_IMVP6_SGND<br />
0.50 MM<br />
0.20 MM<br />
IMVP6_VO<br />
0.25 MM<br />
0.20 MM<br />
IMVP6_DROOP<br />
0.25 MM<br />
0.20 MM<br />
IMVP6_DFB<br />
0.25 MM<br />
0.20 MM<br />
IMVP6_SOFT 0.25 MM 0.20 MM<br />
IMVP6_RBIAS 0.25 MM 0.20 MM<br />
IMVP6_VDIFF 0.25 MM 0.20 MM<br />
IMVP6_FB2<br />
0.25 MM<br />
0.20 MM<br />
IMVP6_FB 0.25 MM 0.20 MM<br />
IMVP6_COMP 0.25 MM 0.20 MM<br />
0.25 MM 0.25 MM<br />
IMVP6_VW<br />
IMVP6_RTN<br />
5<br />
62D8 62D4 7B1<br />
1 2 3<br />
CRITICAL<br />
Q7403<br />
CRITICAL<br />
(IMVP6_PHASE1)<br />
(IMVP6_ISEN1)<br />
=PPVIN_S5_CPU_IMVP<br />
CRITICAL CRITICAL<br />
CRITICAL<br />
Q7402<br />
RJK0328DPB<br />
LFPAK-HF<br />
C7401<br />
33UF<br />
20%<br />
16V<br />
POLY-TANT<br />
CASED2E-SM<br />
0.25 MM<br />
0.25 MM<br />
IMVP6_VSEN 0.25 MM 0.25 MM<br />
C7408<br />
33UF<br />
20%<br />
16V<br />
POLY-TANT<br />
2<br />
CASED2E-SM<br />
RJK0305DPB<br />
LFPAK-HF<br />
(IMVP6_PHASE2)<br />
1<br />
2<br />
(IMVP6_ISEN2)<br />
(IMVP6_VSUM)<br />
CRITICAL<br />
1<br />
C7411<br />
1UF<br />
10%<br />
25V<br />
X5R<br />
603-1<br />
1 2<br />
R7400<br />
10K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
1 2<br />
CRITICAL<br />
L7401<br />
0.36UH-30A-0.80MOHM<br />
MPC1055-SM<br />
MPC1055LR36<br />
DCR=0.8MOHM<br />
1 2<br />
R7405<br />
10K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
R7443<br />
1<br />
3.65K<br />
1%<br />
1/16W<br />
MF-LF<br />
2 402<br />
1<br />
0.001UF<br />
20%<br />
50V<br />
2 CERM<br />
402<br />
1 2<br />
CRITICAL<br />
L7400<br />
0.36UH-30A-0.80MOHM<br />
MPC1055-SM<br />
MPC1055LR36<br />
DCR=0.8MOHM<br />
C7422<br />
APPLE INC.<br />
C7403<br />
0.22uF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
402<br />
1<br />
3.65K<br />
1%<br />
1/16W<br />
MF-LF<br />
2 402<br />
1 2<br />
1 2<br />
C7404<br />
0.22uF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
402<br />
C7419<br />
LOAD LINE SLOPE = -2.1 MV/A<br />
1 2<br />
NO R7451 STUFF<br />
10K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
R7401<br />
1 2<br />
1 5%<br />
1/16W<br />
MF-LF<br />
402<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
R7404<br />
1 2<br />
R7407<br />
1 5%<br />
1/16W<br />
MF-LF<br />
402<br />
NO STUFF<br />
1 2<br />
R7452<br />
10K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
SYNC_MASTER=RAYMOND<br />
DRAWING NUMBER<br />
NONE<br />
=PPVCORE_S0_CPU_REG<br />
SHT<br />
OF<br />
C7420<br />
1<br />
0.001UF<br />
20%<br />
50V<br />
2<br />
CERM<br />
402<br />
C7423<br />
1<br />
0.001UF<br />
20%<br />
50V<br />
CERM<br />
2 402<br />
IMVP6 CPU VCore Regulator<br />
SYNC_DATE=01/31/2008<br />
051-7898<br />
62<br />
REV.<br />
81<br />
7D8<br />
4.7.0<br />
D<br />
C<br />
B<br />
A
8 7 6 5 4 3 2 1<br />
MCP VCORE POWER SUPPLY<br />
D<br />
C<br />
B<br />
45D8<br />
MCPCORES0_IMON<br />
20C3 20A3<br />
20C3 20A3<br />
20C3 20A3<br />
IN<br />
IN<br />
IN<br />
MCP_VID<br />
MCP_VID<br />
MCP_VID<br />
PLACEMENT_NOTE=PLACE R7582 ON THE BOTTOM SIDE<br />
PLACEMENT_NOTE=PLACE R7583 ON THE BOTTOM SIDE<br />
XW7562<br />
SM<br />
63C7 63C1 7C8 =PPMCPCORE_S0_REG 1 2<br />
PLACE XW NEAR THE MCP,<br />
OMIT<br />
CONNECT SENSE LINES TO CLOSEST<br />
MCPCORE AND GND BALL<br />
OF MCP<br />
SM<br />
1 2<br />
OMIT<br />
XW7563<br />
R7593<br />
1<br />
0<br />
5%<br />
2<br />
1/16W<br />
MF-LF<br />
402<br />
R7590<br />
1<br />
0<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
R7592<br />
1<br />
0<br />
2<br />
5% 1/16W<br />
MF-LF<br />
402<br />
R7591<br />
0<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1 NOSTUFF 1<br />
R7580<br />
NOSTUFF R7581<br />
20.0K 20.0K<br />
PLACEMENT_NOTE=PLACE R7580 ON THE BOTTOM SIDE 1%<br />
1%<br />
PLACEMENT_NOTE=PLACE R7581 ON THE BOTTOM SIDE<br />
1/16W 1/16W<br />
MF-LF MF-LF<br />
2402<br />
2402<br />
63C1 63B8 7C8<br />
=PPMCPCORE_S0_REG<br />
R7566<br />
20<br />
MCPCORES0_RSEN_P 1 2<br />
1/16W<br />
1%<br />
MF-LF<br />
402<br />
R7568<br />
20<br />
MCPCORES0_RSEN_N 1 2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
R7582<br />
1<br />
20.0K<br />
1%<br />
1/16W<br />
MF-LF<br />
2402<br />
R7583<br />
1<br />
20.0K<br />
1%<br />
1/16W<br />
2 402 MF-LF<br />
R7563<br />
1<br />
100<br />
1%<br />
1/16W<br />
MF-LF<br />
2402<br />
(MCPCORES0_VSEN)<br />
C7570<br />
1<br />
0.001UF<br />
10%<br />
2<br />
50V<br />
X7R<br />
402<br />
(MCPCORES0_RTN)<br />
1<br />
R7571<br />
100<br />
1%<br />
1/16W<br />
MF-LF<br />
2402<br />
VOLTAGE=5V<br />
MIN_LINE_WIDTH=0.6 mm<br />
MIN_NECK_WIDTH=0.2 MM<br />
20<br />
R7560<br />
16<br />
15<br />
ISL6263D<br />
22<br />
33<br />
7C1<br />
=PPVIN_S0_MCPCORE<br />
5V_S0_MCPREG_VIN<br />
1 2.2 CRITICAL CRITICAL<br />
2 =PP5V_S0_MCPREG<br />
7D5<br />
C7563 1 1<br />
C7560 5%<br />
1 1<br />
C7571 C7561<br />
1/10W<br />
0.001UF 68UF 68UF 1UF<br />
MF-LF<br />
10%<br />
20%<br />
20%<br />
10%<br />
603<br />
50V 25V<br />
C7550 1<br />
X7R 2 2 16V<br />
1 C7562<br />
2 16V<br />
2<br />
POLY-TANT POLY-TANT X5R<br />
402<br />
CASE-D2E-SM CASE-D2E-SM 603-1<br />
1UF<br />
1UF<br />
5<br />
10%<br />
10%<br />
16V<br />
1 X5R 2<br />
2<br />
16V<br />
X5R<br />
R7561<br />
D<br />
1K<br />
402<br />
402<br />
VDD PVCC<br />
Q7560<br />
5%<br />
(MCPCORES0_UGATE)<br />
4 G<br />
1/16W<br />
MIN_LINE_WIDTH=0.5 MM<br />
FDMC8676<br />
MF-LF<br />
MIN_NECK_WIDTH=0.2 MM<br />
POWER33-SM<br />
2402<br />
GATE_NODE=TRUE<br />
U7500<br />
DIDT=TRUE<br />
MCPCORES0_RBIAS<br />
CRITICAL<br />
1 RBIAS QFN VIN 14<br />
S<br />
R7565 C7564<br />
MCPCORES0_SOFT 2 SOFT<br />
0<br />
0.22UF<br />
UGATE 18 MCPCORES0_UGATE1<br />
2 MCPCORES0_BOOT_R 1 2 1 2 3<br />
0.25 MM<br />
CRITICAL<br />
5% 0.2 MM<br />
MCPCORES0_IMON_R 28 IMON<br />
BOOT 17 MCPCORES0_BOOT 1/10W<br />
CERM-X7R<br />
DIDT=TRUE<br />
MF-LF<br />
10V<br />
L7560<br />
DIDT=TRUE 0.2 MM<br />
603<br />
603<br />
0.82UH-16A<br />
66A5<br />
31<br />
OUT<br />
MCPCORES0_PGOOD<br />
PGOOD<br />
PHASE 19<br />
5%<br />
25<br />
(MCPCORES0_PHASE)<br />
PPMCPCORE_S0_R<br />
MCP_VID0_R<br />
MCPCORES0_PHASE<br />
0.25 MM<br />
VID0<br />
MIN_LINE_WIDTH=0.5 MM<br />
SWITCHNODE<br />
26 VID1<br />
1 NO R7589<br />
STUFF<br />
MIN_LINE_WIDTH=0.5 MM<br />
MIN_NECK_WIDTH=0.2 MM<br />
SPM6550T-COMBO MIN_NECK_WIDTH=0.2 MM<br />
MCP_VID1_R<br />
SWITCH_NODE=TRUE<br />
VOLTAGE=1V<br />
DIDT=TRUE<br />
MCP_VID2_R 27 VID2<br />
1<br />
5<br />
5%<br />
MCPCORES0_OS0 23 OFFSET0<br />
1/10W<br />
24 OFFSET1<br />
D<br />
MF-LF<br />
MCPCORES0_OS1<br />
CRITICAL<br />
(MCPCORES0_LGATE)<br />
2 603<br />
66C1<br />
29<br />
IN<br />
=MCPCORES0_EN<br />
VR_ON<br />
Q7565 MCPCORE_SNUBBER<br />
MCPCORES0_FDE 30 AF_EN<br />
LGATE 21 MCPCORES0_LGATE<br />
4 G FDMC8678S<br />
32<br />
MICROFET3X3<br />
FDE<br />
MIN_LINE_WIDTH=0.5 MM<br />
1<br />
8<br />
MIN_NECK_WIDTH=0.2 MM<br />
MCPCORES0_VSEN<br />
VSEN<br />
S<br />
NO STUFF<br />
GATE_NODE=TRUE<br />
MCPCORES0_RTN<br />
9<br />
DIDT=TRUE<br />
C7589<br />
RTN<br />
1 2 3<br />
2 0.001UF<br />
50V<br />
MCPCORES0_VW<br />
4 VW<br />
X7R<br />
10% 402<br />
VO 12 MCPCORES0_VO<br />
(MCPCORES0_VO)<br />
MCPCORES0_COMP<br />
5 COMP<br />
OCSET 3<br />
R7569<br />
11.3K<br />
MCPCORES0_OCSET 1 2<br />
MCPCORES0_FB<br />
6 FB<br />
ISP 13 MCPCORES0_ISP<br />
1%<br />
1/16W<br />
ISN 11 MCPCORES0_ISN<br />
MF-LF<br />
MCPCORES0_VDIFF 7 VDIFF<br />
402<br />
1R7573<br />
ICOMP 10 MCPCORES0_ICOMP<br />
10K C7573 1<br />
1%<br />
PGND VSS THRM_PAD<br />
1/16W 47PF<br />
MF-LF 5%<br />
2402<br />
50V<br />
CERM 2<br />
402<br />
1<br />
C7576 1 R7572<br />
R7500<br />
0.1UF 150K<br />
100<br />
10%<br />
1%<br />
1 2 MCPCORES0_ISP_R<br />
16V 1/16W<br />
X7R-CERM 2 MF-LF<br />
1%<br />
402 2<br />
402<br />
1/16W<br />
XW7561<br />
MF-LF<br />
SM<br />
402<br />
GND_MCPCORES0_AGND1<br />
2<br />
VOLTAGE=0V<br />
(MCPCORES0_ISN)<br />
MIN_LINE_WIDTH=0.6 mm<br />
MIN_NECK_WIDTH=0.2 MM<br />
(MCPCORES0_ICOMP)<br />
R7575<br />
1<br />
47.0K<br />
1%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
1 C7575<br />
47PF<br />
5%<br />
2<br />
50V<br />
CERM<br />
402<br />
R7525<br />
2<br />
4<br />
0.001<br />
1%<br />
1W<br />
MF-1<br />
0612<br />
1<br />
3<br />
C7566<br />
1<br />
10UF<br />
20%<br />
4V<br />
X5R 2<br />
603<br />
C7567<br />
1<br />
10UF<br />
20%<br />
2<br />
4V<br />
X5R<br />
603<br />
MAX CURRENT: 13A<br />
(Q7560 Limit)<br />
=PPMCPCORE_S0_REG<br />
f = 300 kHz<br />
CRITICAL<br />
1<br />
C7565<br />
270UF<br />
20%<br />
2 2V TANT<br />
CASE-B4-SM<br />
C7569<br />
1<br />
0.001UF<br />
10%<br />
2<br />
50V<br />
X7R<br />
402<br />
7C8 63B8 63C7<br />
CRITICAL<br />
1<br />
C7568<br />
270UF 20%<br />
2 2V TANT<br />
CASE-B4-SM<br />
D<br />
C<br />
B<br />
(MCPCORES0_VW)<br />
A<br />
0.001UF<br />
C7580<br />
10%<br />
68PF<br />
50V<br />
X7R 2 1<br />
1 2<br />
402 R7576<br />
6.98K<br />
5%<br />
1%<br />
50V<br />
1/16W<br />
CERM<br />
R7577<br />
C7581 MF-LF<br />
402-1<br />
133K<br />
560PF 2402<br />
1 2 MCPCORES0_COMP_C 1 2<br />
(MCPCORES0_COMP)<br />
1%<br />
1/16W<br />
10%<br />
MF-LF<br />
50V<br />
402<br />
CERM<br />
402 (MCPCORES0_FB)<br />
R7578<br />
100<br />
1 2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
C7579 1<br />
560PF<br />
MCPCORES0_VDIF_C 1 2<br />
R7579<br />
C7582<br />
10%<br />
50V<br />
2.21K CERM<br />
1 2 402<br />
(MCPCORES0_VDIFF)<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
VID MCP TARGET<br />
000 +1.05V<br />
001 +1.00V<br />
010 +0.95V<br />
011 +0.90V<br />
100 +0.85V<br />
101 +0.80V<br />
110 +0.75V<br />
111 +0.70V<br />
SYNC_MASTER=K19_<strong>MLB</strong><br />
MCP CORE REGULATOR<br />
NOTICE OF PROPRIETARY PROPERTY<br />
SYNC_DATE=12/10/2008<br />
A<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
63<br />
81<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
CPUVTT POWER SUPPLY<br />
D<br />
7C1<br />
=PPVIN_S0_CPUVTTS0<br />
CRITICAL<br />
1<br />
C7630<br />
33UF<br />
20%<br />
16V 2<br />
POLY-TANT<br />
CASED2E-SM<br />
1<br />
2<br />
C7695<br />
1UF<br />
10%<br />
25V<br />
X5R<br />
603-1<br />
C7696<br />
1<br />
0.001UF<br />
20%<br />
50V<br />
CERM<br />
2 402<br />
C<br />
B<br />
7D5<br />
=PP5V_S0_CPUVTTS0<br />
R7601<br />
301 1 2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
PP5V_S0_CPUVTTS0_V5FILT<br />
MIN_LINE_WIDTH=0.6 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=5V<br />
66C1<br />
66A5<br />
IN<br />
OUT<br />
=CPUVTTS0_EN<br />
CPUVTTS0_PGOOD<br />
(=PPCPUVTT_S0_REG)<br />
CPUVTTS0_VFB<br />
CPUVTTS0_TRIP<br />
1<br />
R7604<br />
8.87K<br />
1%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
1<br />
C7601<br />
1UF<br />
10%<br />
10V<br />
X5R<br />
2<br />
402-1<br />
3<br />
5<br />
11<br />
PGOOD<br />
VOUT<br />
VFB<br />
TRIP<br />
4<br />
V5FILT<br />
V5DRV<br />
CRITICAL<br />
U7600<br />
TPS51117RGY_QFN14<br />
SYM QFN (2 OF 2)<br />
1 EN_PSV<br />
TON 2<br />
6<br />
VBST<br />
DRVH<br />
LL<br />
DRVL<br />
GND THRM_PAD PGND<br />
7<br />
15<br />
XW7600<br />
SM<br />
1<br />
2<br />
10<br />
8<br />
ROUTING NOTE:<br />
14<br />
13<br />
12<br />
9<br />
1<br />
C7604<br />
4.7UF<br />
10%<br />
6.3V<br />
2<br />
X5R-CERM<br />
603<br />
CPUVTTS0_TON<br />
CPUVTTS0_VBST<br />
CPUVTTS0_DRVH<br />
GATE_NODE=TRUE<br />
CPUVTTS0_LL<br />
SWITCH_NODE=TRUE<br />
CPUVTTS0_DRVL<br />
GATE_NODE=TRUE<br />
(GND)<br />
Place XW7600 between Pin 7 and Pin 15 of U7600.<br />
GND_CPUVTTS0_SGND<br />
MIN_LINE_WIDTH=0.6 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=0V<br />
(CPUVTTS0_VFB)<br />
MIN_LINE_WIDTH=0.6MM<br />
MIN_NECK_WIDTH=0.2MM<br />
MIN_LINE_WIDTH=0.6MM<br />
MIN_NECK_WIDTH=0.2MM<br />
MIN_LINE_WIDTH=0.6MM<br />
MIN_NECK_WIDTH=0.2MM<br />
MIN_LINE_WIDTH=0.6MM<br />
MIN_NECK_WIDTH=0.2MM<br />
C7603<br />
0.1UF<br />
10%<br />
50V<br />
DIDT=TRUE X7R<br />
603-1<br />
DIDT=TRUE<br />
DIDT=TRUE<br />
DIDT=TRUE<br />
R7603<br />
1<br />
200K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
2<br />
Q7620<br />
FDMS9600S<br />
MLP<br />
CRITICAL 1<br />
8<br />
9 4 3 2<br />
Q1<br />
Q2<br />
7 6 5<br />
10<br />
SW<br />
1<br />
R7670<br />
8.45K<br />
1%<br />
1/16W<br />
2<br />
MF-LF<br />
402<br />
<br />
1<br />
R7671<br />
20.0K<br />
1%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
<br />
L7620<br />
2.2UH-8.0A<br />
CRITICAL<br />
CPUVTTS0_VSNS<br />
1 2<br />
PCMB065T-SM<br />
Vout = 0.75V * (1 + Ra / Rb)<br />
2<br />
XW7665<br />
SM<br />
1<br />
NO STUFF<br />
C7670<br />
1<br />
100PF<br />
50V<br />
5%<br />
CERM 2<br />
402<br />
PLACEMENT_NOTE=Place XW7665 next to L7620<br />
1<br />
2<br />
C7665<br />
10UF<br />
20%<br />
6.3V<br />
X5R<br />
603<br />
CRITICAL<br />
C7660 1<br />
2<br />
330UF<br />
20%<br />
2.5V<br />
TANT<br />
CASE-B2-SM<br />
SM<br />
2<br />
1<br />
1<br />
2<br />
=PPCPUVTT_S0_REG<br />
VOUT = 1.062V<br />
8A max output<br />
F = 320 KHZ<br />
C7661<br />
0.001UF<br />
20%<br />
50V<br />
CERM<br />
402<br />
XW7601<br />
ROUTING NOTE:<br />
Place XW7601 by C7660.<br />
7D8<br />
C<br />
B<br />
CPUVTTS0_VOUT<br />
(=PPCPUVTT_S0_REG)<br />
A<br />
CPU VTT(1.05V) SUPPLY<br />
SYNC_MASTER=RAYMOND<br />
SYNC_DATE=02/08/2008<br />
NOTICE OF PROPRIETARY PROPERTY<br />
A<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
64 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
1.8V S0 SWITCHER<br />
D<br />
7B5<br />
=PP3V3_S0_P1V8S0<br />
1<br />
C7760<br />
10uF<br />
20%<br />
6.3V<br />
X5R 2<br />
603<br />
66C1<br />
=P1V8S0_EN<br />
4<br />
3<br />
1 CRITICAL<br />
VI<br />
U7760<br />
TPS62202<br />
SOT23-5<br />
FB<br />
EN SW<br />
GND<br />
2<br />
5<br />
P1V8S0_SW<br />
DIDT=TRUE<br />
CRITICAL<br />
L7760<br />
10UH-0.55A-330MOHM<br />
PCAA031B-SM<br />
1 2<br />
C7762<br />
1<br />
10uF<br />
20%<br />
6.3V<br />
X5R 2<br />
603<br />
MAX CURRENT = 200MA<br />
=PP1V8_S0_REG<br />
7B8<br />
C<br />
1.05V S0 PLL LDO<br />
C<br />
B<br />
A<br />
7A3<br />
66B1<br />
MCP 1.05V S5 (AUXC) SUPPLY<br />
=PP3V3_S5_P1V05S5<br />
66D6<br />
IN<br />
P1V05_S5_PGOOD<br />
=P1V05_S5_EN<br />
1<br />
VIN<br />
U7750<br />
1<br />
2<br />
CRITICAL<br />
C7750<br />
22UF<br />
20%<br />
6.3V<br />
CERM<br />
805<br />
CRITICAL<br />
L7770<br />
ISL8009B<br />
2.2UH-3.25A<br />
DFN<br />
IHLP1616BZ-SM<br />
2<br />
EN CRITICAL LX<br />
8 1V05S5_SW 1 DIDT=TRUE<br />
2<br />
3<br />
POR<br />
VFB<br />
6 1V05S5_FB<br />
C7776 1<br />
4<br />
SKIP<br />
RSI<br />
5<br />
47PF<br />
5%<br />
50V<br />
GND THRM_PAD<br />
CERM 2<br />
402<br />
7 9<br />
7B5<br />
2<br />
<br />
1<br />
IN0 OUT0<br />
9<br />
2<br />
IN1LDO_YES<br />
OUT1<br />
10<br />
P1V05S0_LDO_SS 7<br />
SS<br />
PG<br />
3<br />
NOSTUFF<br />
C7743<br />
1<br />
GND THRML_PAD<br />
0.0022UF<br />
10%<br />
50V<br />
CERM 2<br />
402<br />
=PP1V05_S5_REG 7B4<br />
1 <br />
Vout = 1.05V<br />
1<br />
2<br />
=PP3V3_S0_MCP_PLL_VLDO<br />
7B6<br />
806K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
C7741<br />
1<br />
1UF<br />
LDO_YES 10%<br />
6.3V<br />
CERM 2<br />
402<br />
R7780<br />
255K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
R7781<br />
LDO_YES<br />
100<br />
1 2 PP3V3_S0_MCP_PLL_VLDO_BIAS<br />
5%<br />
MIN_LINE_WIDTH=0.2 MM<br />
1/16W<br />
MIN_NECK_WIDTH=0.2 mm<br />
VOLTAGE=3.3V<br />
MF-LF<br />
402<br />
LDO_YES<br />
=PP1V5_S0_MCP_PLL_VLDO<br />
1<br />
2<br />
CRITICAL<br />
C7771<br />
47UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0805<br />
R7743<br />
C7740 1<br />
1UF<br />
10%<br />
2<br />
6.3V<br />
CERM<br />
402<br />
EN<br />
MAX CURRENT = 0.8A<br />
FREQ = 1.6MHZ<br />
5<br />
6<br />
CRITICAL<br />
BIAS<br />
4<br />
TPS74701<br />
SON<br />
U7740<br />
11<br />
FB<br />
8<br />
P1V05S0_LDO_FB<br />
TP_P1V05S0_LDO_PGOOD<br />
1.37K<br />
4.42K<br />
Vout = 1.05V<br />
MAX CURRENT = 0.5A<br />
<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
R7746<br />
<br />
1%<br />
PP1V05_S0_MCP_PLL_UF_LDO<br />
MIN_LINE_WIDTH=0.6 mm<br />
MIN_NECK_WIDTH=0.2 mm<br />
LDO_YES<br />
VOLTAGE=1.05V<br />
1/16W<br />
MF-LF<br />
402<br />
R7747<br />
LDO_YES<br />
C7742<br />
4.7UF<br />
20%<br />
2<br />
4V<br />
X5R 402<br />
LDO_YES<br />
VOUT = 0.8V * (1 + RA / RB)<br />
1<br />
7C7<br />
=PP1V05_S0_MCP_PLL_UF_R<br />
LDO_NO<br />
R7745<br />
1<br />
0<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
R7744<br />
0<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
LDO_YES<br />
=PP1V05_S0_MCP_PLL_UF<br />
MISC POWER SUPPLIES<br />
SYNC_MASTER=RAYMOND<br />
7B8 22C4<br />
SYNC_DATE=01/23/2008<br />
NOTICE OF PROPRIETARY PROPERTY<br />
B<br />
A<br />
VOUT = 0.8V * (1 + RA / RB)<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
65<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
81<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
66C8 66B3 7D1<br />
60C5 40D5 6C3<br />
IN<br />
=PP3V42_G3H_PWRCTL<br />
SMC_PM_G2_EN<br />
1<br />
R7800<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
3.3V 1.05V S5 ENABLE<br />
R7802<br />
100K<br />
2 1<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
Q7800<br />
SSM3K15FV<br />
SOD-VESM-HF<br />
1 G<br />
D 3<br />
S 2<br />
1 C7802<br />
2<br />
NO STUFF<br />
0.068UF<br />
10%<br />
10V<br />
CERM<br />
402<br />
PM_G2_P3V3S5_EN_L<br />
MAKE_BASE=TRUE<br />
R7801<br />
5.1K<br />
2 1 PM_G2_P1V05S5_EN<br />
MAKE_BASE=TRUE<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1 C7801<br />
0.47UF<br />
10%<br />
6.3V<br />
2 CERM-X5R<br />
402<br />
=P3V3S5_EN_L<br />
=P1V05_S5_EN<br />
OUT 60A5<br />
OUT 65A8<br />
Power Control Signals<br />
State<br />
SMC_PM_G2_ENABLE<br />
PM_SLP_S4_L<br />
PM_SLP_S3_L<br />
Run (S0) 1<br />
1 1<br />
Sleep (S3)<br />
1<br />
1<br />
0<br />
Soft-Off (S5)<br />
1 0<br />
0<br />
Battery Off (G3Hot)<br />
0 0<br />
0<br />
R7859<br />
(PM_SLP_S3_L)<br />
100<br />
70D8 40C5 35A5 32B7 20C3 6C3 IN<br />
PM_SLP_S3_L<br />
2 1<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
3.3V_S0, 1.8V_S0 ENABLE<br />
MCPDDR, CPUVTT,MCPCORES0 ENABLE<br />
1.5V S0 AND 1.05V S0 ENABLE<br />
PM_SLP_S3_L_BUF<br />
MAKE_BASE=TRUE<br />
=P5VS0_EN<br />
OUT<br />
67A8<br />
D<br />
66D8 66B3 7D1<br />
=PP3V42_G3H_PWRCTL<br />
R7813<br />
68K<br />
2 1<br />
S3 ENABLE<br />
R7879<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
2<br />
2 R7880<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1 22K<br />
2<br />
1<br />
R7881<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
33K<br />
2<br />
1<br />
R7882<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
0<br />
2<br />
1<br />
R7883<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
10K<br />
2<br />
1<br />
R7884<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
5.1K<br />
=PBUSVSENS_EN<br />
OUT<br />
44B7<br />
C<br />
41A2 40C5 20C3 6C3<br />
IN<br />
PM_SLP_S4_L<br />
MAKE_BASE=TRUE<br />
R7810 1<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
(PM_S4_STATE_L)<br />
1 G<br />
D<br />
S 2<br />
3 Q7813<br />
SSM3K15FV<br />
SOD-VESM-HF<br />
1 NO STUFF<br />
C7813<br />
2<br />
0.068UF<br />
10%<br />
10V<br />
CERM<br />
402<br />
PM_SLP_S3_L_INVERT<br />
MAKE_BASE=TRUE<br />
=P5VS3_EN_L<br />
OUT 60A7<br />
MCPCORES0_EN<br />
MAKE_BASE=TRUE<br />
CPUVTTS0_EN<br />
MAKE_BASE=TRUE<br />
MCPDDR_EN<br />
MAKE_BASE=TRUE<br />
P1V8S0_EN<br />
MAKE_BASE=TRUE<br />
P3V3S0_EN<br />
MAKE_BASE=TRUE<br />
=P3V3S0_EN<br />
=P1V8S0_EN<br />
=MCPDDR_EN<br />
=CPUVTTS0_EN<br />
=MCPCORES0_EN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
67B8<br />
65C7<br />
67C4<br />
64B7<br />
63C6<br />
C<br />
R7811<br />
5.1K<br />
1<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
C7810<br />
0.47UF<br />
1 2<br />
10%<br />
6.3V<br />
CERM-X5R<br />
402<br />
1<br />
C7880<br />
0.47UF<br />
10%<br />
6.3V<br />
2<br />
CERM-X5R<br />
402<br />
1<br />
C7881<br />
0.47UF<br />
10%<br />
6.3V<br />
2<br />
CERM-X5R<br />
402<br />
NO STUFF<br />
1<br />
C7882<br />
0.47UF<br />
10%<br />
6.3V<br />
2<br />
CERM-X5R<br />
402<br />
1<br />
C7883<br />
0.47UF<br />
10%<br />
6.3V<br />
2<br />
CERM-X5R<br />
402<br />
1 C7884<br />
0.47UF<br />
10%<br />
6.3V<br />
2 CERM-X5R<br />
402<br />
DDRREG_EN<br />
MAKE_BASE=TRUE<br />
=DDRREG_EN<br />
=USB_PWR_EN<br />
OUT<br />
OUT<br />
61C8<br />
38B7<br />
1<br />
R7812<br />
0<br />
2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
NO STUFF<br />
C7812<br />
0.47UF<br />
1 2<br />
10%<br />
6.3V<br />
CERM-X5R<br />
402<br />
66D8 66C8 7D1<br />
=PP3V42_G3H_PWRCTL<br />
VOLTAGE MONITOR<br />
P3V3S3_EN<br />
MAKE_BASE=TRUE<br />
=P3V3S3_EN<br />
OUT<br />
67C8<br />
7A3<br />
=PP3V3_S5_PWRCTL<br />
B<br />
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT<br />
PP3V3_VMON_VDD<br />
=PP5V_S0_VMON<br />
7D5<br />
1<br />
R7870<br />
10K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
OTHER S0 RAILS PGOOD<br />
CT<br />
C7841 1<br />
0.001UF<br />
20%<br />
50V<br />
CERM 2<br />
402<br />
6<br />
VDD<br />
U7840<br />
5 SENSE<br />
RESET* 1<br />
TPS3808G33DBVRG4<br />
4 CT<br />
SOT23-6<br />
MR* 3<br />
GND<br />
2<br />
C7840 1<br />
0.1uF<br />
20%<br />
10V<br />
2 CERM<br />
402<br />
1 R7840<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
RSMRST_PWRGD<br />
P1V05_S5_PGOOD<br />
TPS3808 MR* HAS INTERNAL PULLUP<br />
40D8<br />
65A8<br />
B<br />
A<br />
7C5 =PP3V3_S0_VMON<br />
=PP1V5_S0_VMON<br />
7B6<br />
7D7<br />
=PP1V05_S0_VMON<br />
353S2310<br />
GND<br />
VDD<br />
U7870<br />
ISL88042IRTEZ<br />
TDFN<br />
3<br />
5<br />
V2MON<br />
V3MON<br />
MR*<br />
6 V4MON RST*<br />
4<br />
2<br />
7<br />
THRM_PAD<br />
9<br />
1<br />
8<br />
NC<br />
C7870 1<br />
0.1uF<br />
20%<br />
10V<br />
2 CERM<br />
402<br />
1<br />
R7871<br />
20.0K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
S0PGOOD_PWROK<br />
7C5 =PP3V3_S0_PWRCTL<br />
60A2 IN<br />
P5V3V3_PGOOD<br />
63C6 IN<br />
MCPCORES0_PGOOD<br />
R7820<br />
1<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
TP_DDRREG_PGOOD<br />
MAKE_BASE=TRUE<br />
Unused PGOOD signal<br />
DDRREG_PGOOD<br />
61B3<br />
POWER SEQUENCING<br />
SYNC_MASTER=YUAN.MA<br />
SYNC_DATE=12/11/2008<br />
NOTICE OF PROPRIETARY PROPERTY<br />
A<br />
V2MON THRESHOLD IS 2.866V<br />
V3MON THRESHOLD IS 0.6V<br />
V4MON THRESHOLD IS 0.6V<br />
64B7<br />
IN<br />
CPUVTTS0_PGOOD<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
(S0PGOOD_PWROK)<br />
ALL_SYS_PWRGD<br />
MAKE_BASE=TRUE<br />
OUT<br />
24B8 40D8<br />
APPLE INC.<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
66<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
3.3V S3 FET<br />
1.5V S0 FET<br />
(1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)<br />
D<br />
7A3 =PP3V3_S5_P3V3S3FET<br />
66B6 =P3V3S3_EN<br />
IN<br />
R7912 1<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
Q7903<br />
SSM3K15FV<br />
SOD-VESM-HF<br />
1 G<br />
P3V3S3_EN_L<br />
D 3<br />
S 2<br />
R7910<br />
47K<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
C7911 1<br />
0.033UF<br />
10%<br />
16V<br />
2<br />
X5R<br />
402<br />
P3V3S3_SS<br />
4<br />
CRITICAL<br />
Q7910<br />
FDC638P_G<br />
3<br />
SM<br />
C7910<br />
0.01UF<br />
1 2<br />
10%<br />
16V<br />
CERM<br />
402<br />
6<br />
5<br />
2<br />
1<br />
=PP3V3_S3_FET<br />
7D4<br />
3.3V S3 FET<br />
MOSFET<br />
FDC638P<br />
CHANNEL<br />
P-TYPE<br />
RDS(ON)<br />
48 mOhm @4.5V<br />
LOADING<br />
0.182 A (EDP)<br />
7C3<br />
=PP5V_S3_MCPDDRFET<br />
R7903 1<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
D 3<br />
Q7971<br />
SSM6N15FEAPE<br />
SOT563<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
7D3<br />
R7901<br />
10K<br />
1 2<br />
MCPDDR_EN_L<br />
=PP1V5_S3_P1V5S0FET<br />
MCPDDR_SS<br />
R7971<br />
47K<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
C7902 1<br />
0.1UF<br />
2<br />
D 6<br />
Q7971<br />
SSM6N15FEAPE<br />
SOT563<br />
2<br />
20%<br />
10V<br />
CERM<br />
402<br />
G<br />
S<br />
MCPDDR_EN_L_RC<br />
1<br />
4 G<br />
SENSE<br />
7<br />
9 CRITICAL<br />
Q7901<br />
D ROME<br />
DFN<br />
NC<br />
8<br />
KELVIN 6 P1V5_S0_KELVIN OUT<br />
S<br />
GND<br />
1 2 3 5<br />
P1V5_S0_SENSE OUT<br />
=PP1V5_S0_FET<br />
7C8<br />
1<br />
C7903<br />
0.068UF<br />
1.5V S0 FET<br />
10%<br />
10V<br />
2<br />
CERM<br />
MOSFET<br />
Rome SenseFET<br />
402<br />
CHANNEL<br />
N-TYPE<br />
RDS(ON)<br />
6.3 mOHM @4.5V VGS<br />
45C8 45D8<br />
D<br />
LOADING<br />
5A (EDP)<br />
3.3V S0 FET<br />
66C1<br />
IN<br />
=MCPDDR_EN<br />
5<br />
G<br />
S<br />
4<br />
C<br />
7A3<br />
=PP3V3_S5_P3V3S0FET<br />
R7932 1<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
P3V3S0_EN_L<br />
R7930<br />
47K<br />
1 2<br />
C7931 1<br />
16V<br />
2<br />
X5R<br />
0.033UF<br />
10%<br />
402<br />
P3V3S0_SS<br />
4<br />
CRITICAL<br />
Q7930<br />
FDC606P_G<br />
SOT-6<br />
S<br />
3 G<br />
D<br />
1 2 5 6<br />
C7930<br />
0.01UF<br />
1 2<br />
=PP3V3_S0_FET<br />
7D6<br />
3.3V S0 FET<br />
MOSFET<br />
FDC606P<br />
CHANNEL<br />
P-TYPE<br />
RDS(ON)<br />
26 MOHM @4.5V<br />
LOADING<br />
1.431 A (EDP)<br />
C<br />
Q7905<br />
SSM3K15FV<br />
SOD-VESM-HF<br />
D 3<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
10%<br />
16V<br />
CERM<br />
402<br />
MCP79 DDRVTT FET<br />
B<br />
66C1 IN<br />
=P3V3S0_EN<br />
7C3 =PP5V_S3_P5VS0FET<br />
1 G<br />
S 2<br />
R7942<br />
47K<br />
Q7945<br />
SSM3K15FV<br />
SOD-VESM-HF<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
2<br />
D 3<br />
P5V0S0_EN_L<br />
5.0V S0 FET<br />
R7940<br />
47K<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
C7941<br />
0.033UF<br />
10%<br />
16V<br />
X5R<br />
402<br />
1<br />
2<br />
P5V0S0_SS<br />
3<br />
1 2<br />
CRITICAL<br />
Q7940<br />
TPCP8102<br />
23V1K-SM<br />
S<br />
G<br />
4<br />
D<br />
C7940<br />
0.01UF<br />
1<br />
8<br />
7<br />
6<br />
5<br />
10%<br />
16V<br />
CERM<br />
402<br />
376S0778<br />
2<br />
=PP5V_S0_FET<br />
7D6<br />
5.0V S0 FET<br />
MOSFET<br />
TPCP8102<br />
CHANNEL<br />
P-TYPE<br />
RDS(ON)<br />
13.5 MOHM @4.5V<br />
LOADING<br />
1.7 A (EDP)<br />
7C7<br />
7C3<br />
MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT<br />
NVIDIA RECOMMENDS UNPOWERING DURING SLEEP.<br />
IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE<br />
MUST GUARANTEE MEM_CKE SIGNALS ARE LOW<br />
BEFORE RAIL IS TURNED OFF, AND REMAINS LOW<br />
UNTIL AFTER RAIL TURNS BACK ON OR DIMMS<br />
WILL EXIT SELF-REFRESH PREMATURELY.<br />
MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP<br />
ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS<br />
LOW THROUGH VTT TERMINATION RESISTORS.<br />
=PPVTT_S0_VTTCLAMP<br />
=PP5V_S3_VTTCLAMP<br />
R7976 1<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R7975<br />
10<br />
2 1<br />
5%<br />
1/10W<br />
MF-LF<br />
603<br />
VTTCLAMP_EN<br />
VTTCLAMP_L<br />
D 6<br />
Q7975<br />
SSM6N15FEAPE<br />
SOT563<br />
2<br />
G<br />
S<br />
1<br />
90mA max load @ 0.9V<br />
81mW max power<br />
CKT FROM T18<br />
B<br />
A<br />
66C1<br />
IN<br />
=P5VS0_EN<br />
1 G<br />
S 2<br />
61C8 24C1<br />
IN<br />
=DDRVTT_EN<br />
D 3<br />
Q7975<br />
SSM6N15FEAPE<br />
SOT563<br />
5<br />
G<br />
S<br />
4<br />
NO STUFF<br />
0.001UF<br />
20%<br />
50V<br />
CERM<br />
402<br />
C7976 1 2<br />
SYNC_MASTER=YUAN.MA<br />
POWER FETS<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
SYNC_DATE=12/11/2008<br />
A<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
67 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 . 1
SYM_VER-1<br />
8 7 6 5 4 3 2 1<br />
D<br />
D<br />
C<br />
B<br />
CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP<br />
17B6<br />
7A3<br />
LVDS_IG_PANEL_PWR<br />
1<br />
R9014<br />
1K<br />
5%<br />
1/16W<br />
2 402 MF-LF<br />
=PP3V3_S5_LCD<br />
1 C9009<br />
0.1UF<br />
10%<br />
2<br />
16V<br />
X5R<br />
402<br />
CRITICAL<br />
U9000<br />
FPF1009<br />
1<br />
MFET-2X2<br />
ON<br />
2 VIN_1 VOUT_1 4<br />
3 VIN_2 VOUT_2 5<br />
GND THRM<br />
PAD<br />
6 7<br />
C9011<br />
1<br />
0.1UF<br />
10%<br />
2 16V<br />
X5R 402<br />
1 C9012<br />
10UF<br />
20%<br />
2 6.3V<br />
X5R<br />
603<br />
PP3V3_LCDVDD_SW<br />
VOLTAGE=3.3V<br />
MIN_LINE_WIDTH=0.30 MM<br />
MIN_NECK_WIDTH=0.20 MM<br />
17B3 6C7<br />
17A3 6C7<br />
7C5<br />
=PP3V3_S0_LCD<br />
LVDS_IG_DDC_CLK<br />
LVDS_IG_DDC_DATA<br />
1<br />
R9008<br />
100K<br />
5%<br />
1/16W<br />
2 402 MF-LF<br />
L9004<br />
FERR-120-OHM-1.5A<br />
1<br />
1<br />
R9009<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
2<br />
0402-LF<br />
CRITICAL<br />
L9008<br />
120-OHM-0.3A-EMI<br />
1<br />
0402-LF<br />
(LVDS DDC POWER)<br />
2<br />
C9015<br />
0.001UF<br />
10%<br />
50V<br />
X7R<br />
402<br />
6C7 PP3V3_S0_LCD_F<br />
MIN_LINE_WIDTH=0.25 MM VOLTAGE=3.3V<br />
MIN_NECK_WIDTH=0.20 MM<br />
75B3 17B3<br />
75B3 17B3<br />
LVDS_IG_A_CLK_N<br />
LVDS_IG_A_CLK_P<br />
4<br />
CRITICAL<br />
L9080<br />
1<br />
2<br />
90-OHM-200MA<br />
AMC2012-SM<br />
1<br />
3 2<br />
C9010<br />
0.001UF<br />
10%<br />
50V<br />
X7R<br />
402<br />
1<br />
2<br />
LCD<br />
CONNECTOR<br />
LVDS CONNECTOR:518S0650<br />
6C7 6C3 PP3V3_LCDVDD_SW_F<br />
MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3VMIN_LINE_WIDTH=0.30 MM<br />
71B1 6C7<br />
71B1 6C7<br />
71B1 6C7<br />
71B1 6B7<br />
71B1 6B7<br />
71A1 6B7<br />
75B3 6C7<br />
75B3 6C7<br />
LED_RETURN_1<br />
LED_RETURN_2<br />
LED_RETURN_3<br />
LED_RETURN_4<br />
LED_RETURN_5<br />
LED_RETURN_6<br />
6B7<br />
LVDS_IG_A_CLK_F_N<br />
LVDS_IG_A_CLK_F_P<br />
71C1 6C7 6C3<br />
TP_BKL_SYNC<br />
17B3 6C7<br />
75B3<br />
17B3 6C7<br />
75B3<br />
17B3 6C7<br />
75B3<br />
75B3 17B3 6C7<br />
75B3 17B3 6C7<br />
75B3 17B3 6C7<br />
LVDS_IG_A_DATA_N<br />
LVDS_IG_A_DATA_P<br />
LVDS_IG_A_DATA_N<br />
LVDS_IG_A_DATA_P<br />
LVDS_IG_A_DATA_N<br />
LVDS_IG_A_DATA_P<br />
PPVOUT_S0_LCDBKLT<br />
NC<br />
NC<br />
NC<br />
CRITICAL<br />
J9000<br />
20474-030E-11<br />
F-RT-SM<br />
31<br />
32<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10<br />
11<br />
12<br />
13<br />
14<br />
15<br />
16<br />
17<br />
18<br />
19<br />
20<br />
21<br />
22<br />
23<br />
24<br />
25<br />
26<br />
27<br />
28<br />
29<br />
30<br />
33<br />
34<br />
LVDS I/F<br />
LED BKLT I/F<br />
C<br />
B<br />
A<br />
LVDS CONNECTOR<br />
SYNC_MASTER=NMARTIN SYNC_DATE=04/04/2008<br />
NOTICE OF PROPRIETARY PROPERTY<br />
A<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
68 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
17B6 =MCP_HDMI_TXC_P<br />
17B6 =MCP_HDMI_TXC_N<br />
17B6 =MCP_HDMI_TXD_P<br />
17B6 =MCP_HDMI_TXD_N<br />
17B6 =MCP_HDMI_TXD_P<br />
17B6 =MCP_HDMI_TXD_N<br />
17B6 =MCP_HDMI_TXD_P<br />
17B6 =MCP_HDMI_TXD_N<br />
17B6 =MCP_HDMI_HPD<br />
17A3 =MCP_HDMI_DDC_CLK<br />
17A3 =MCP_HDMI_DDC_DATA<br />
DP_ML_P<br />
DP_ML_N<br />
DP_ML_P<br />
DP_ML_N<br />
DP_ML_P<br />
DP_ML_N<br />
DP_ML_P<br />
DP_ML_N<br />
DP_HPD<br />
DP_IG_DDC_CLK<br />
DP_IG_DDC_DATA<br />
70C8 75C3<br />
MAKE_BASE=TRUE<br />
70C8 75C3<br />
MAKE_BASE=TRUE<br />
70C1 75C3<br />
MAKE_BASE=TRUE<br />
70C1 75C3<br />
MAKE_BASE=TRUE<br />
70C1 75C3<br />
MAKE_BASE=TRUE<br />
70C1 75C3<br />
MAKE_BASE=TRUE<br />
70C1 75C3<br />
MAKE_BASE=TRUE<br />
70C1 75C3<br />
MAKE_BASE=TRUE<br />
70A8<br />
MAKE_BASE=TRUE<br />
69C8<br />
MAKE_BASE=TRUE<br />
69C8<br />
MAKE_BASE=TRUE<br />
D<br />
DP_AUX_CH_C_N<br />
BI<br />
70C8 75B3<br />
C<br />
69D1<br />
BI<br />
Display Port Interoperability spec says that sources<br />
or sinks which do both DP and DVI must depend on the<br />
external adapter for pull ups on DDC lines (since DP<br />
AUX CH has 100K pull up/down on the <strong>MLB</strong>)..<br />
69D1<br />
BI<br />
DP_IG_DDC_DATA<br />
DP_IG_DDC_CLK<br />
R9300<br />
1<br />
33<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
R9301<br />
33 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
C9301<br />
0.1UF<br />
1<br />
10%<br />
16V<br />
X5R<br />
402<br />
75B3<br />
2<br />
DP_AUX_CH_SW_P<br />
3 D<br />
Q9300<br />
C9300<br />
0.1UF<br />
1<br />
10%<br />
16V<br />
X5R<br />
402<br />
SSM6N15FEAPE<br />
SOT563<br />
75B3<br />
2<br />
DP_AUX_CH_SW_N<br />
Q9300<br />
SSM6N15FEAPE<br />
SOT563<br />
D 6<br />
DP_AUX_CH_C_P<br />
BI<br />
70C8 75B3<br />
C<br />
4 S<br />
G 5<br />
2 G<br />
S 1<br />
75B3 17B6<br />
BI<br />
DP_IG_AUX_CH_P<br />
75B3 17B6<br />
BI<br />
DP_IG_AUX_CH_N<br />
=PP5V_S0_DP_AUX_MUX<br />
7D5<br />
R9306<br />
1K<br />
1<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
R9302<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
2<br />
402<br />
DDC_CA_DET_LS5V_L<br />
B<br />
3 D<br />
Q9301<br />
SSM3K15FV<br />
SOD-VESM-HF<br />
B<br />
2 S<br />
G 1<br />
70B8<br />
IN<br />
DP_CA_DET<br />
DP_IG_CA_DET<br />
OUT<br />
17B6<br />
A<br />
DISPLAYPORT SUPPORT<br />
SYNC_MASTER=AMASON<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=04/18/2008<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
69 81<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
Port Power Switch<br />
D<br />
7A3<br />
=PP3V3_S5_DP_PORT_PWR<br />
CRITICAL<br />
U9480<br />
TPS2051B<br />
SOT23<br />
5 IN OUT 1<br />
PM_SLP_S3_L<br />
4<br />
66D5 40C5 35A5 32B7 20C3 6C3 IN<br />
EN OC* 3<br />
GND<br />
2<br />
TP_DPPWR_OC_L<br />
PP3V3_S0_DPILIM<br />
MIN_LINE_WIDTH=0.38 MM<br />
MIN_NECK_WIDTH=0.20 MM<br />
VOLTAGE=3.3V<br />
1<br />
2<br />
L9400<br />
FERR-120-OHM-3A<br />
1<br />
C9400<br />
4.7UF<br />
20%<br />
6.3V<br />
X5R-CERM<br />
402<br />
0603<br />
2<br />
PP3V3_S0_DPPWR<br />
MIN_LINE_WIDTH=0.38 MM<br />
MIN_NECK_WIDTH=0.20 MM<br />
VOLTAGE=3.3V<br />
DP_ESD<br />
CRITICAL<br />
D9410<br />
RCLAMP0524P<br />
SLP2510P8<br />
5 IO IO 4<br />
6 NC NC 7<br />
GND<br />
DP_ESD<br />
CRITICAL<br />
D9410<br />
RCLAMP0524P<br />
SLP2510P8<br />
2 IO<br />
9 NC<br />
GND<br />
IO 1<br />
NC 10<br />
D<br />
C9480<br />
22UF<br />
20%<br />
6.3V<br />
X5R-CERM-1<br />
603<br />
1<br />
2<br />
1<br />
2<br />
C9481<br />
4.7UF<br />
20%<br />
6.3V<br />
X5R-CERM<br />
402<br />
C9485 1<br />
22UF<br />
20%<br />
6.3V<br />
X5R-CERM-1<br />
2<br />
603<br />
1<br />
CRITICAL<br />
C9486<br />
22UF<br />
20%<br />
2<br />
6.3V<br />
X5R-CERM-1<br />
603<br />
3<br />
3<br />
R9420<br />
1<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
C<br />
B<br />
75C3 69D1<br />
75C3 69D1<br />
75B3 69C4<br />
75B3 69D4<br />
IN<br />
IN<br />
BI<br />
BI<br />
70B8 7C5<br />
69B7<br />
DP_ML_P C9414<br />
DP_ML_C_P<br />
1 2 75C3<br />
0.1uF<br />
16V<br />
10% X5R 402<br />
DP_ML_N C9415<br />
DP_ML_C_N<br />
1 2 75C3<br />
0.1uF<br />
16V X5R<br />
10% 402<br />
DP_AUX_CH_C_P<br />
OUT<br />
DP_AUX_CH_C_N<br />
=PP3V3_S0_DPCONN<br />
DP_CA_DET<br />
R9443<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
Q9440<br />
2N7002DW-X-G<br />
SOT-363<br />
Q9440 must have Drain to Gate leakage of 5MOhm<br />
1<br />
6<br />
1<br />
D<br />
S<br />
G<br />
2<br />
R9442<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
DP_CA_DET_L_Q<br />
Q9440<br />
2N7002DW-X-G<br />
SOT-363<br />
1<br />
2<br />
3<br />
4<br />
D<br />
S<br />
G<br />
12-OHM-100MA<br />
TCM1210-4SM<br />
4 SYM_VER-2 1<br />
5<br />
3<br />
FL9403<br />
2<br />
R9421<br />
1<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402 2<br />
DP_CA_DET_Q<br />
R9422<br />
1<br />
1M<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
75B3<br />
75B3<br />
DP_ESD<br />
CRITICAL<br />
D9411<br />
RCLAMP0524P<br />
SLP2510P8<br />
2 IO<br />
9 NC<br />
GND<br />
IO 1<br />
NC 10<br />
DP to DVI/HDMI<br />
Cable Adapter<br />
(CA) has 100k<br />
pull-up to DP_PWR.<br />
3<br />
HDMI_CEC<br />
1<br />
R9425<br />
1M<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
DP_ML_CONN_P<br />
DP_ML_CONN_N<br />
BOT ROW<br />
TOP ROW<br />
TH PINS<br />
SM PINS<br />
2<br />
HOT_PLUG_DETECT GND<br />
1<br />
4<br />
6<br />
CONFIG1<br />
CONFIG2<br />
ML_LANE0P<br />
ML_LANE0N<br />
3<br />
5<br />
8<br />
10<br />
GND<br />
ML_LANE3P<br />
GND<br />
ML_LANE1P<br />
7<br />
9 75B3<br />
12<br />
ML_LANE3N<br />
75B3<br />
ML_LANE1N<br />
11<br />
14<br />
16<br />
GND<br />
AUX_CHP<br />
GND<br />
ML_LANE2P<br />
13<br />
15<br />
18<br />
AUX_CHN ML_LANE2N<br />
17<br />
20 DP_PWR<br />
RETURN<br />
19<br />
D9400<br />
RCLAMP0504F<br />
1<br />
2<br />
3<br />
CRITICAL<br />
J9400<br />
DSPLYPRT-M97-1<br />
F-RT-THSM<br />
DP_ESD<br />
CRITICAL<br />
SC70-6-1<br />
SHIELD PINS<br />
6<br />
5<br />
4<br />
22 21<br />
514-0637<br />
75B3<br />
75B3<br />
DP_ML_CONN_P<br />
DP_ML_CONN_N<br />
DP_ML_CONN_P<br />
DP_ML_CONN_N<br />
12-OHM-100MA<br />
TCM1210-4SM<br />
1 SYM_VER-2 4<br />
2<br />
DP_ESD<br />
CRITICAL<br />
D9411<br />
RCLAMP0524P<br />
SLP2510P8<br />
5IO<br />
IO 4<br />
6 NC NC 7<br />
GND<br />
3<br />
FL9401<br />
75B3 DP_ML_CONN_P<br />
75B3 DP_ML_CONN_N<br />
3<br />
FL9402<br />
12-OHM-100MA<br />
TCM1210-4SM<br />
1 SYM_VER-2 4<br />
2<br />
3<br />
12-OHM-100MA<br />
TCM1210-4SM<br />
1 SYM_VER-2 4<br />
2<br />
FL9400<br />
3<br />
75C3 DP_ML_C_P<br />
75C3 DP_ML_C_N<br />
75C3 DP_ML_C_P<br />
75C3 DP_ML_C_N<br />
75C3 DP_ML_C_P<br />
75C3 DP_ML_C_N<br />
C9410 1<br />
0.1uF<br />
C9411 1<br />
0.1uF<br />
C9412 1<br />
0.1uF<br />
C9413 1<br />
0.1uF<br />
C9416 1<br />
0.1uF<br />
C9417 1<br />
0.1uF<br />
2 DP_ML_P<br />
10% 16V X5R 402<br />
2 DP_ML_N<br />
10% 16V X5R 402<br />
2 DP_ML_P<br />
10% 16V X5R 402<br />
2 DP_ML_N<br />
10% 16V X5R 402<br />
2 DP_ML_P<br />
10% 16V X5R 402<br />
2 DP_ML_N<br />
10% 16V X5R 402<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
69D1 75C3<br />
69D1 75C3<br />
69D1 75C3<br />
69D1 75C3<br />
69D1 75C3<br />
69D1 75C3<br />
C<br />
B<br />
70C8 7C5<br />
=PP3V3_S0_DPCONN<br />
69D1 OUT<br />
DP_HPD<br />
R9445<br />
10K<br />
1<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
R9444<br />
1<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
A<br />
R9446<br />
100K<br />
1<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
MCP79 requires pull<br />
down HPD input with Q9441<br />
2N7002DW-X-G<br />
100K if DP_HPD is used. SOT-363<br />
6<br />
D<br />
S<br />
1<br />
G<br />
2<br />
DP_HPD_L_Q<br />
Q9441<br />
2N7002DW-X-G<br />
SOT-363<br />
3<br />
4<br />
D<br />
S<br />
G<br />
5<br />
DP_HPD_Q<br />
1<br />
R9423<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
DP Source must pull<br />
down HPD input with<br />
greater than or equal<br />
to 100K (DPv1.1a).<br />
SYNC_MASTER=AMASON<br />
DisplayPort Connector<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=06/30/2008<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
70<br />
81<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
BKLT_VLDO_EN_L<br />
*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.<br />
*PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.<br />
* LVDS_IG_BKL_PWM SHOULD BE AWAY FROM BOOST CIRCUIT<br />
6<br />
NO STUFF<br />
Q9701<br />
NTUD3127CXXG<br />
SOT-963<br />
N-CHANNEL<br />
D<br />
3<br />
D<br />
S<br />
G<br />
2<br />
1<br />
BKLT_EN_R<br />
NO STUFF<br />
R9701<br />
0<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
BKLT_EN<br />
71B6<br />
D<br />
D<br />
G<br />
S<br />
P-CHANNEL<br />
5<br />
4<br />
NO STUFF<br />
R9735<br />
100K<br />
1 2<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
=PP5V_S0_BKL<br />
7D5<br />
MIN_LINE_WIDTH=0.4 MM<br />
C<br />
72C3 71B7<br />
PPBUS_S0_LCDBKLT_PWR<br />
BKLT_PROD<br />
R9700<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
2<br />
CRITICAL<br />
1<br />
C9712<br />
10UF<br />
10%<br />
25V<br />
2<br />
X5R<br />
805<br />
MIN_NECK_WIDTH=0.2 MM<br />
VOLTAGE=5V<br />
1<br />
C9713<br />
0.1UF<br />
10%<br />
25V<br />
2<br />
X5R<br />
402<br />
BKL_SWGND 71B5 71C2<br />
NO STUFF<br />
1<br />
R9702<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
PPVIN_BKL<br />
MIN_LINE_WIDTH=0.5 MM<br />
MIN_NECK_WIDTH=0.375 MM<br />
VOLTAGE=6V<br />
1<br />
R9703<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
CRITICAL<br />
L9701<br />
22UH-2.5A<br />
1<br />
2<br />
IHLP2525CZ-SM<br />
PPBUS_S0_LCDBKLT_PWR_SW<br />
MIN_LINE_WIDTH=0.5 MM<br />
MIN_NECK_WIDTH=0.375 MM<br />
VOLTAGE=50V<br />
SWITCH_NODE=TRUE<br />
CRITICAL<br />
D9701<br />
SOD-123<br />
1 2<br />
RB160M-40<br />
1<br />
C9796<br />
200PF<br />
5%<br />
2<br />
100V<br />
CERM<br />
1206<br />
1 C9799<br />
2.2UF<br />
10%<br />
2<br />
100V<br />
X7R<br />
1210<br />
PPVOUT_S0_LCDBKLT<br />
C9797<br />
1<br />
10%<br />
2<br />
100V<br />
X7R<br />
1210<br />
2.2UF<br />
MIN_LINE_WIDTH=0.5 MM<br />
MIN_NECK_WIDTH=0.375 MM<br />
VOLTAGE=50V<br />
BKL_SWGND 71B5 71C5<br />
6C3 6C7 68B2<br />
C<br />
B<br />
43B6 =I2C_BKL_1_SCL<br />
43B6 =I2C_BKL_1_SDA<br />
R9753<br />
R9757<br />
72C3 71C7 PPBUS_S0_LCDBKLT_PWR<br />
72B7 17B6 IN<br />
0<br />
0<br />
1<br />
1<br />
1<br />
301K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
LVDS_IG_BKL_PWM<br />
7B5 =PP3V3_S0_BKL_VDDIO<br />
2<br />
2<br />
R9731<br />
2<br />
5%<br />
5%<br />
1/16W<br />
1/16W<br />
1<br />
2<br />
C9723<br />
0.1UF<br />
10%<br />
25V<br />
X5R<br />
402<br />
NO STUFF<br />
MF-LF 402<br />
MF-LF<br />
R9704<br />
0<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
NO STUFF<br />
R9714<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
R9704 SHOULD BE 47K IF RC FILTER IS USED<br />
2<br />
1<br />
402<br />
R9715<br />
100K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
R9716<br />
100K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
NO STUFF<br />
1 C9704<br />
33PF<br />
5%<br />
50V<br />
2 CERM<br />
402<br />
1<br />
0.01UF<br />
2 16V 10%<br />
CERM<br />
402<br />
1<br />
0.1UF<br />
10%<br />
2 X5R<br />
VDDIO VLDO<br />
402<br />
NC<br />
6 ALSO<br />
IF_SEL=1 FOR SMBUS 5 ALSI<br />
IF_SEL=0 FOR I2C<br />
20<br />
ADR<br />
BKL_IF_SEL<br />
71D3<br />
C9714<br />
BKL_SCL<br />
BKL_SDA<br />
BKLT_EN<br />
10%<br />
2<br />
25V<br />
X5R<br />
603-1<br />
BKL_SWGND HIGH CURRENT<br />
NEED 2 VIAS<br />
1<br />
XW9700<br />
1<br />
C9710<br />
1UF<br />
LVDS_IG_BKL_PWM_RC<br />
TP_BKL_FAULT<br />
SM<br />
2<br />
BKL_VLDO<br />
71C5<br />
71C2<br />
C9711<br />
3<br />
IF_SEL<br />
10<br />
SCLK<br />
11 SDA<br />
2 PWM<br />
7 FAULT<br />
4 EN<br />
BKL_SWGND<br />
PLACEMENT_NOTE=SW9700 PLACE NEAR C9712 C9713<br />
8<br />
BKL_SGND<br />
GND_SW<br />
1<br />
U9701<br />
OMIT<br />
GND_S<br />
9<br />
22<br />
LLP<br />
LP8543SQX<br />
GND_L<br />
15<br />
23<br />
VIN<br />
OUT6 18<br />
THRM<br />
PAD<br />
PPVIN_BKL_R<br />
SW 24<br />
FB 21<br />
OUT1<br />
12<br />
OUT2<br />
13<br />
OUT3<br />
14<br />
OUT4 16<br />
CRITICAL<br />
OUT5 17 BKL_ISEN5<br />
OUT7 19<br />
NC<br />
25<br />
XW9710<br />
1<br />
SM<br />
BKL_ISEN1<br />
BKL_ISEN2<br />
BKL_ISEN3<br />
BKL_ISEN4<br />
BKL_ISEN6<br />
2<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.20 mm<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.20 mm<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.20 mm<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.20 mm<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.20 mm<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.20 mm<br />
R9717<br />
0<br />
1 2<br />
R9718<br />
0<br />
1<br />
R9719<br />
0<br />
1<br />
R9720<br />
0<br />
1<br />
R9721<br />
0<br />
1<br />
5% BKLT_PROD<br />
1/16W<br />
MF-LF<br />
402<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
R9722<br />
0<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
BKLT_PROD<br />
2<br />
2<br />
2<br />
BKLT_PROD<br />
BKLT_PROD<br />
BKLT_PROD<br />
BKLT_PROD<br />
LED_RETURN_1<br />
LED_RETURN_2<br />
LED_RETURN_3<br />
LED_RETURN_4<br />
LED_RETURN_5<br />
LED_RETURN_6<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.20 mm<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.20 mm<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.20 mm<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.20 mm<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.20 mm<br />
MIN_LINE_WIDTH=0.5 mm<br />
MIN_NECK_WIDTH=0.20 mm<br />
OUT 6C7 68B3<br />
OUT 6C7 68B3<br />
OUT 6C7 68B3<br />
OUT 6B7 68B3<br />
OUT 6B7 68B3<br />
OUT 6B7 68B3<br />
B<br />
A<br />
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION<br />
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION<br />
103S0198<br />
116S0005<br />
6 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM R9717,R9718,R9719,R9720,R9721,R9722<br />
1<br />
RES,1/16W,0.1 OHM,1%,0402,SM<br />
R9700<br />
BKLT_ENG<br />
BKLT_ENG<br />
353S2670<br />
1<br />
IC,LP8543,WHT LED BKLT CTRLR,QFN24,PROD<br />
U9701<br />
CRITICAL<br />
SYNC_MASTER=KIRAN<br />
LCD BACKLIGHT DRIVER<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
SYNC_DATE=12/05/2008<br />
A<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
71<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1<br />
D<br />
7C1<br />
IN<br />
=PPBUS_S0_LCDBKLT<br />
MIN_LINE_WIDTH=0.4 mm<br />
MIN_NECK_WIDTH=0.25 mm<br />
VOLTAGE=12.6V<br />
F9800<br />
2AMP-32V<br />
1 2<br />
0402-HF<br />
PPBUS_S0_LCDBKLT_FUSED<br />
MIN_LINE_WIDTH=0.4 mm<br />
MIN_NECK_WIDTH=0.25 mm<br />
VOLTAGE=12.6V<br />
1<br />
R9808<br />
301K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1 C9802<br />
0.1UF<br />
10%<br />
16V<br />
2 X5R<br />
402<br />
CRITICAL<br />
Q9806<br />
FDC638APZ_SBMS001<br />
SSOT6-HF<br />
4<br />
3<br />
1 2 5 6<br />
PPBUS S0 LCDBkLT FET<br />
MOSFET<br />
FDC638APZ<br />
CHANNEL<br />
P-TYPE<br />
RDS(ON)<br />
43 mOhm @4.5V<br />
LOADING<br />
0.4 A (EDP)<br />
D<br />
PPBUS_S0_LCDBKLT_EN_DIV<br />
PPBUS_S0_LCDBKLT_EN_L<br />
1<br />
R9809<br />
147K<br />
1%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
Q9807<br />
SSM6N15FEAPE<br />
SOT563<br />
D<br />
3<br />
72B7 17B6<br />
IN<br />
LVDS_IG_BKL_ON<br />
5<br />
G<br />
S<br />
4<br />
BKLT_EN_L<br />
PPBUS_S0_LCDBKLT_PWR<br />
MIN_LINE_WIDTH=0.4 mm<br />
MIN_NECK_WIDTH=0.25 mm<br />
VOLTAGE=12.6V<br />
OUT<br />
71B7 71C7<br />
C<br />
24C1<br />
IN<br />
BKLT_PLT_RST_L<br />
Q9807<br />
SSM6N15FEAPE<br />
SOT563<br />
2 G<br />
D 6<br />
S 1<br />
C<br />
B<br />
B<br />
LVDS_IG_BKL_ON<br />
LVDS_IG_BKL_PWM<br />
17B6 72C8<br />
17B6 71A7<br />
1<br />
R9840<br />
1K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
1<br />
R9841<br />
1K<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
A<br />
MCP HAS INTERNAL 10K PULL-UP FOR THESE SIGNALS<br />
SYNC_MASTER=YITE<br />
LCD Backlight Support<br />
NOTICE OF PROPRIETARY PROPERTY<br />
SYNC_DATE=06/30/2008<br />
A<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
72 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 . 1
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
8 7 6 5 4 3 2 1<br />
FSB (Front-Side Bus) Constraints<br />
CPU / FSB Net Properties<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
ELECTRICAL_CONSTRAINT_SET<br />
PHYSICAL<br />
NET_TYPE<br />
SPACING<br />
FSB_50S<br />
* =50_OHM_SE<br />
=50_OHM_SE<br />
=50_OHM_SE<br />
=50_OHM_SE<br />
=STANDARD<br />
=STANDARD<br />
FSB_DSTB_50S =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE<br />
* =1:1_DIFFPAIR =1:1_DIFFPAIR<br />
FSB_DATA_GROUP0 FSB_50S FSB_DATA FSB_D_L<br />
FSB_DATA_GROUP0 FSB_50S FSB_DATA FSB_DINV_L<br />
FSB_DSTB0<br />
FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P<br />
9C4 13D3<br />
9C4 13D6<br />
9C4 13D6<br />
D<br />
C<br />
SPACING_RULE_SET<br />
FSB_DATA<br />
FSB_ADSTB<br />
FSB_1X<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
LINE-TO-LINE SPACING<br />
FSB_DSTB *<br />
=3x_DIELECTRIC<br />
?<br />
FSB_ADDR * =STANDARD<br />
* =2x_DIELECTRIC<br />
?<br />
* =STANDARD<br />
?<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
SPACING_RULE_SET<br />
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.<br />
FSB 2X signals / groups shown in signal table on right.<br />
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.<br />
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.<br />
FSB 1X signals shown in signal table on right.<br />
Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.<br />
Design Guide recommends each strobe/signal group is routed on the same layer.<br />
Intel Design Guide recommends FSB signals be routed only on internal layers.<br />
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.<br />
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2<br />
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3<br />
CPU Signal Constraints<br />
*<br />
=2x_DIELECTRIC ?<br />
LINE-TO-LINE SPACING<br />
FSB 4X signals / groups shown in signal table on right.<br />
Signals within each 4x group should be matched within 5 ps of strobe.<br />
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.<br />
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.<br />
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.<br />
CPU_50S<br />
?<br />
FSB_DSTB<br />
FSB_ADDR<br />
FSB_1X<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
*<br />
=50_OHM_SE<br />
=50_OHM_SE<br />
LAYER<br />
FSB_DATA TOP,BOTTOM =4x_DIELECTRIC<br />
?<br />
FSB_ADSTB<br />
=50_OHM_SE<br />
TOP,BOTTOM<br />
TOP,BOTTOM<br />
TOP,BOTTOM<br />
TOP,BOTTOM<br />
=50_OHM_SE<br />
=5x_DIELECTRIC ?<br />
=3x_DIELECTRIC ?<br />
=4x_DIELECTRIC ?<br />
=3x_DIELECTRIC ?<br />
=STANDARD<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
CPU_27P4S * =27P4_OHM_SE =27P4_OHM_SE<br />
=27P4_OHM_SE<br />
=27P4_OHM_SE<br />
7 MIL 7 MIL<br />
=STANDARD<br />
FSB 2X<br />
FSB 1X Signals<br />
Signals<br />
FSB 4X Signal Groups<br />
FSB_DSTB0 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_N<br />
FSB_DATA_GROUP1<br />
FSB_50S<br />
FSB_DATA FSB_D_L<br />
FSB_DATA_GROUP1<br />
FSB_50S<br />
FSB_DATA FSB_DINV_L<br />
FSB_DSTB1 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P<br />
FSB_DSTB1<br />
FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_N<br />
FSB_DATA_GROUP2<br />
FSB_DATA_GROUP2<br />
FSB_DSTB2<br />
FSB_DSTB2<br />
FSB_DATA_GROUP3<br />
FSB_DATA_GROUP3<br />
FSB_DSTB3<br />
FSB_DSTB3<br />
FSB_ADDR_GROUP0<br />
FSB_ADDR_GROUP0<br />
FSB_ADSTB0<br />
FSB_50S<br />
FSB_50S<br />
FSB_DSTB_50S<br />
FSB_DSTB_50S<br />
FSB_50S<br />
FSB_50S<br />
FSB_DSTB_50S<br />
FSB_DSTB_50S<br />
FSB_50S<br />
FSB_50S<br />
FSB_50S<br />
FSB_DATA<br />
FSB_DATA<br />
FSB_DSTB<br />
FSB_DSTB<br />
FSB_DATA<br />
FSB_DATA<br />
FSB_DSTB<br />
FSB_DSTB<br />
FSB_ADDR<br />
FSB_ADDR<br />
FSB_ADSTB<br />
FSB_D_L<br />
FSB_DINV_L<br />
FSB_DSTB_L_P<br />
FSB_DSTB_L_N<br />
FSB_D_L<br />
FSB_DINV_L<br />
FSB_DSTB_L_P<br />
FSB_DSTB_L_N<br />
FSB_A_L<br />
FSB_REQ_L<br />
FSB_ADSTB_L<br />
FSB_ADDR_GROUP1 FSB_50S<br />
FSB_ADDR FSB_A_L<br />
FSB_ADSTB1<br />
FSB_50S<br />
FSB_ADSTB FSB_ADSTB_L<br />
FSB_1X FSB_50S<br />
FSB_1X FSB_ADS_L<br />
FSB_BREQ0_L<br />
FSB_50S<br />
FSB_1X<br />
FSB_BREQ0_L<br />
FSB_BREQ1_L<br />
FSB_50S<br />
FSB_1X<br />
FSB_BREQ1_L<br />
FSB_1X FSB_50S<br />
FSB_1X FSB_BNR_L<br />
FSB_1X FSB_50S<br />
FSB_1X FSB_BPRI_L<br />
FSB_1X<br />
FSB_50S<br />
FSB_1X<br />
FSB_DBSY_L<br />
FSB_1X<br />
FSB_50S<br />
FSB_1X<br />
FSB_DEFER_L<br />
FSB_1X<br />
FSB_50S<br />
FSB_1X<br />
FSB_DRDY_L<br />
FSB_1X<br />
FSB_50S<br />
FSB_1X<br />
FSB_HIT_L<br />
FSB_1X FSB_50S<br />
FSB_1X FSB_HITM_L<br />
FSB_1X FSB_50S<br />
FSB_1X FSB_LOCK_L<br />
FSB_CPURST_L<br />
FSB_50S<br />
FSB_1X<br />
FSB_CPURST_L<br />
FSB_1X<br />
FSB_50S<br />
FSB_1X<br />
FSB_RS_L<br />
FSB_1X<br />
FSB_50S<br />
FSB_1X<br />
FSB_TRDY_L<br />
9C4 13D6<br />
9B4 9C4 13C3 13D3<br />
9B4 13D6<br />
9B4 13D6<br />
9B4 13D6<br />
9C2 13B3 13C3<br />
9C2 13D6<br />
9C2 13D6<br />
9C2 13D6<br />
9B2 9C2 13B3<br />
9B2 13D6<br />
9B2 13D6<br />
9B2 13D6<br />
9D8 13C6 13D6<br />
9D8 13B6<br />
9D8 13B6<br />
9C8 9D8 13C6<br />
9C8 13B6<br />
9D6 13B6<br />
9D6 13B6<br />
13B6<br />
9D6 13B6<br />
9D6 13B3<br />
9D6 13B6<br />
9D6 13B3<br />
9D6 13B6<br />
9D6 13B6<br />
9D6 13B6<br />
9D6 13B6<br />
9D6 12C2 13A3<br />
9D6 13A6<br />
9D6 13B6<br />
D<br />
C<br />
B<br />
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.<br />
SPACING_RULE_SET<br />
CPU_AGTL<br />
CPU_8MIL<br />
PHYSICAL_RULE_SET<br />
SPACING_RULE_SET<br />
PHYSICAL_RULE_SET<br />
SPACING_RULE_SET<br />
LAYER<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
LAYER<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
LAYER<br />
LINE-TO-LINE SPACING<br />
* =STANDARD<br />
?<br />
* 8 MIL<br />
?<br />
CPU_COMP *<br />
25 MIL<br />
?<br />
CPU_GTLREF<br />
CPU_ITP<br />
CPU_VCCSENSE *<br />
LINE-TO-LINE SPACING<br />
LINE-TO-LINE SPACING<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
SPACING_RULE_SET<br />
Most CPU signals with impedance requirements are 55-ohm single-ended.<br />
Some signals require 27.4-ohm single-ended impedance.<br />
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2<br />
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4<br />
MCP FSB COMP Signal Constraints<br />
MCP_50S<br />
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4<br />
FSB Clock Constraints<br />
*<br />
*<br />
25 MIL<br />
=2:1_SPACING ?<br />
25 MIL ?<br />
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5<br />
?<br />
CPU_AGTL<br />
SPACING_RULE_SET<br />
LAYER<br />
LAYER<br />
LINE-TO-LINE SPACING<br />
TOP,BOTTOM =2x_DIELECTRIC<br />
?<br />
SR DG recommends at least 25 mils, >50 mils preferred<br />
* =50_OHM_SE<br />
=50_OHM_SE =50_OHM_SE<br />
=50_OHM_SE<br />
MCP_FSB_COMP * 8 MIL<br />
?<br />
CLK_FSB<br />
=STANDARD<br />
CLK_FSB_100D * =100_OHM_DIFF =100_OHM_DIFF<br />
=100_OHM_DIFF<br />
=100_OHM_DIFF<br />
=100_OHM_DIFF<br />
CLK_FSB *<br />
=3x_DIELECTRIC<br />
?<br />
LINE-TO-LINE SPACING<br />
TOP,BOTTOM =4x_DIELECTRIC<br />
?<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
=STANDARD<br />
=100_OHM_DIFF<br />
CPU_ASYNC<br />
CPU_BSEL<br />
CPU_FERR_L<br />
CPU_ASYNC<br />
CPU_INIT_L<br />
CPU_ASYNC_R<br />
CPU_ASYNC_R<br />
CPU_PROCHOT_L<br />
CPU_PWRGD<br />
CPU_ASYNC<br />
CPU_ASYNC<br />
PM_THRMTRIP_L<br />
FSB_CPUSLP_L<br />
CPU_FROM_SB<br />
CPU_DPRSTP_L<br />
CPU_ASYNC<br />
MCP_CPU_COMP<br />
MCP_CPU_COMP<br />
MCP_CPU_COMP<br />
MCP_CPU_COMP<br />
CPU_50S<br />
CPU_50S<br />
CPU_50S<br />
CPU_50S<br />
CPU_50S<br />
CPU_50S<br />
CPU_50S<br />
CPU_50S<br />
CPU_50S<br />
CPU_50S<br />
CPU_50S<br />
CPU_50S<br />
CPU_50S<br />
CPU_50S<br />
CPU_50S<br />
CPU_50S<br />
MCP_50S<br />
MCP_50S<br />
MCP_50S<br />
MCP_50S<br />
CPU_AGTL<br />
CPU_AGTL<br />
CPU_8MIL<br />
CPU_AGTL<br />
CPU_AGTL<br />
CPU_AGTL<br />
CPU_AGTL<br />
CPU_AGTL<br />
CPU_AGTL<br />
CPU_AGTL<br />
CPU_AGTL<br />
CPU_8MIL<br />
CPU_AGTL<br />
CPU_AGTL<br />
CPU_AGTL<br />
CPU_AGTL<br />
MCP_FSB_COMP<br />
MCP_FSB_COMP<br />
MCP_FSB_COMP<br />
MCP_FSB_COMP<br />
CPU_A20M_L<br />
CPU_BSEL<br />
CPU_FERR_L<br />
CPU_IGNNE_L<br />
CPU_INIT_L<br />
CPU_INTR<br />
CPU_NMI<br />
CPU_PROCHOT_L<br />
CPU_PWRGD<br />
CPU_SMI_L<br />
CPU_STPCLK_L<br />
PM_THRMTRIP_L<br />
FSB_CPUSLP_L<br />
CPU_DPSLP_L<br />
CPU_DPRSTP_L<br />
FSB_DPWR_L<br />
MCP_BCLK_VML_COMP_VDD<br />
MCP_BCLK_VML_COMP_GND<br />
MCP_CPU_COMP_VCC<br />
MCP_CPU_COMP_GND<br />
FSB_CLK_CPU<br />
CLK_FSB_100D CLK_FSB<br />
FSB_CLK_CPU_P<br />
FSB_CLK_CPU<br />
CLK_FSB_100D CLK_FSB<br />
FSB_CLK_CPU_N<br />
FSB_CLK_ITP<br />
CLK_FSB_100D CLK_FSB<br />
FSB_CLK_ITP_P<br />
FSB_CLK_ITP CLK_FSB_100D CLK_FSB FSB_CLK_ITP_N<br />
FSB_CLK_MCP<br />
CLK_FSB_100D CLK_FSB<br />
FSB_CLK_MCP_P<br />
FSB_CLK_MCP<br />
CLK_FSB_100D CLK_FSB<br />
FSB_CLK_MCP_N<br />
CPU_IERR_L CPU_50S CPU_IERR_L<br />
PM_DPRSLPVR CPU_50S<br />
CPU_AGTL PM_DPRSLPVR<br />
(See above)<br />
CPU_50S CPU_AGTL IMVP_DPRSLPVR<br />
CPU_GTLREF<br />
CPU_50S<br />
CPU_GTLREF CPU_GTLREF<br />
CPU_COMP CPU_50S CPU_COMP CPU_COMP<br />
CPU_COMP<br />
CPU_27P4S<br />
CPU_COMP CPU_COMP<br />
CPU_COMP<br />
CPU_50S<br />
CPU_COMP CPU_COMP<br />
CPU_COMP<br />
CPU_27P4S<br />
CPU_COMP CPU_COMP<br />
XDP_TDI CPU_50S CPU_ITP XDP_TDI<br />
XDP_TDO CPU_50S CPU_ITP XDP_TDO<br />
XDP_TMS CPU_50S CPU_ITP XDP_TMS<br />
XDP_TCK CPU_50S CPU_ITP XDP_TCK<br />
XDP_TRST_L CPU_50S CPU_ITP XDP_TRST_L<br />
XDP_BPM_L CPU_50S CPU_ITP<br />
XDP_BPM_L<br />
XDP_BPM_L5 CPU_50S CPU_ITP XDP_BPM_L<br />
(FSB_CPURST_L)<br />
CPU_50S<br />
CPU_ITP<br />
XDP_CPURST_L<br />
9C8 13A3<br />
8B2 9B4<br />
9C8 13B7<br />
9C8 13A3<br />
9D6 13A3<br />
9C8 13A3<br />
9B8 13A3<br />
9C5 13B6 41D4 62C8<br />
9B2 12C7 13A3<br />
9B8 13A3<br />
9C8 13A3<br />
9C6 13B7 41C4<br />
9B2 13A3<br />
9B2 13A3<br />
9B2 13A3 62C7<br />
9B2 13A3<br />
13A6<br />
13A6<br />
13A6<br />
13A6<br />
9B6 13B3<br />
9B6 13B3<br />
12C3 13B3<br />
12C3 13B3<br />
13A4<br />
13A4<br />
9D6<br />
20C7 62D8<br />
62C7<br />
9B4 25B1<br />
9B3<br />
9B3<br />
9B3<br />
9B3<br />
9B6 9C6 12B3<br />
9B6 9C6 12B3<br />
9B6 9C6 12B3<br />
9A6 9C6 12B6<br />
9A6 9C6 12B3<br />
9C6 12C6<br />
9C5 12C6<br />
12C4<br />
B<br />
A<br />
CPU_VID<br />
CPU_50S<br />
CPU_8MIL<br />
IMVP6_VID<br />
CPU_50S<br />
CPU_8MIL<br />
CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_P<br />
CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_N<br />
(CPU_VCCSENSE)<br />
CPU_27P4S CPU_VCCSENSE IMVP6_VSEN_P<br />
(CPU_VCCSENSE)<br />
IMVP6_VSEN_N<br />
CPU_27P4S<br />
CPU_VCCSENSE<br />
10B6 62C7<br />
10B5 62A5<br />
10A5 62A5<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
CPU/FSB Constraints<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
SYNC_DATE=01/04/2008<br />
A<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
73<br />
81<br />
8 7 6 5 4 3 2 1
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
8 7 6 5 4 3 2 1<br />
Memory Bus Constraints<br />
Memory Net Properties<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
ELECTRICAL_CONSTRAINT_SET<br />
NET_TYPE<br />
PHYSICAL<br />
SPACING<br />
MEM_40S<br />
MEM_40S_VDD<br />
* =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE<br />
=STANDARD<br />
=STANDARD<br />
* =40_OHM_SE<br />
=40_OHM_SE<br />
=40_OHM_SE<br />
=40_OHM_SE<br />
=STANDARD<br />
=STANDARD<br />
MEM_A_CLK<br />
MEM_A_CLK<br />
MEM_70D_VDD<br />
MEM_70D_VDD<br />
MEM_CLK<br />
MEM_CLK<br />
MEM_A_CLK_P<br />
MEM_A_CLK_N<br />
14B5 26C5 26C7<br />
14B5 26C5 26C7<br />
MEM_70D<br />
MEM_70D_VDD<br />
=70_OHM_DIFF<br />
=70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF<br />
* =70_OHM_DIFF =70_OHM_DIFF<br />
* =70_OHM_DIFF =70_OHM_DIFF<br />
=70_OHM_DIFF<br />
=70_OHM_DIFF<br />
=70_OHM_DIFF<br />
=70_OHM_DIFF<br />
MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_CKE<br />
MEM_A_CNTL<br />
MEM_40S_VDD MEM_CTRL MEM_A_CS_L<br />
MEM_A_CNTL<br />
MEM_40S_VDD MEM_CTRL MEM_A_ODT<br />
14A5 26D5 26D7<br />
14B5 26C5 26C7<br />
14B5 26C5<br />
D<br />
SPACING_RULE_SET<br />
LAYER<br />
LINE-TO-LINE SPACING<br />
MEM_CLK2MEM * =4:1_SPACING<br />
?<br />
MEM_CTRL2CTRL<br />
* =2:1_SPACING<br />
?<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
MEM_A_CMD<br />
MEM_A_CMD<br />
MEM_A_CMD<br />
MEM_40S_VDD MEM_CMD<br />
MEM_A_A<br />
MEM_40S_VDD MEM_CMD<br />
MEM_A_BA<br />
MEM_40S_VDD MEM_CMD MEM_A_RAS_L<br />
MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_CAS_L<br />
MEM_A_CMD<br />
MEM_40S_VDD MEM_CMD<br />
MEM_A_WE_L<br />
14B5 14C5 26C5 26C7<br />
14C5 26C5 26C7<br />
14C5 26C5<br />
14C5 26C7<br />
14C5 26C7<br />
D<br />
MEM_CTRL2MEM * =2.5:1_SPACING<br />
?<br />
MEM_CMD2CMD * =1.5:1_SPACING<br />
?<br />
MEM_CMD2MEM * =3:1_SPACING<br />
?<br />
MEM_DATA2DATA * =1.5:1_SPACING<br />
?<br />
MEM_A_DQ_BYTE0<br />
MEM_A_DQ_BYTE1<br />
MEM_A_DQ_BYTE2<br />
MEM_A_DQ_BYTE3<br />
MEM_40S<br />
MEM_DATA MEM_A_DQ<br />
MEM_40S<br />
MEM_DATA MEM_A_DQ<br />
MEM_40S MEM_DATA MEM_A_DQ<br />
MEM_40S<br />
MEM_DATA MEM_A_DQ<br />
MEM_A_DQ_BYTE4 MEM_40S<br />
MEM_DATA MEM_A_DQ<br />
14B7 26C2 26C4 26D2 26D4<br />
14B7 26C2 26C4<br />
14B7 14C7 26B2 26B4 26C2 26C4<br />
14C7 26C2 26C4<br />
14C7 26B5 26B7 26C5 26C7<br />
MEM_DATA2MEM<br />
MEM_DQS2MEM *<br />
* =3:1_SPACING<br />
?<br />
=3:1_SPACING<br />
?<br />
MEM_A_DQ_BYTE5 MEM_40S<br />
MEM_DATA MEM_A_DQ<br />
MEM_A_DQ_BYTE6<br />
MEM_40S<br />
MEM_DATA MEM_A_DQ<br />
MEM_A_DQ_BYTE7<br />
MEM_40S MEM_DATA MEM_A_DQ<br />
14C7 14D7 26B5 26B7<br />
14D7 26B5 26B7<br />
14D7 26A5 26A7 26B5 26B7<br />
MEM_2OTHER * 25 MIL<br />
?<br />
Memory Bus Spacing Group Assignments<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
MEM_CLK MEM_CLK *<br />
MEM_CLK2MEM<br />
MEM_CLK MEM_CTRL *<br />
MEM_CLK2MEM<br />
NET_SPACING_TYPE1<br />
MEM_CMD<br />
NET_SPACING_TYPE2<br />
MEM_CTRL<br />
AREA_TYPE<br />
*<br />
SPACING_RULE_SET<br />
MEM_CMD MEM_CLK<br />
* MEM_CMD2MEM<br />
MEM_CMD2MEM<br />
MEM_A_DQ_BYTE0<br />
MEM_40S<br />
MEM_DATA MEM_A_DM<br />
MEM_A_DQ_BYTE1<br />
MEM_40S<br />
MEM_DATA MEM_A_DM<br />
MEM_A_DQ_BYTE2 MEM_40S<br />
MEM_DATA MEM_A_DM<br />
MEM_A_DQ_BYTE3<br />
MEM_40S<br />
MEM_DATA MEM_A_DM<br />
MEM_A_DQ_BYTE4 MEM_40S<br />
MEM_DATA MEM_A_DM<br />
MEM_A_DQ_BYTE5 MEM_40S<br />
MEM_DATA MEM_A_DM<br />
MEM_A_DQ_BYTE6<br />
MEM_40S<br />
MEM_DATA MEM_A_DM<br />
MEM_A_DQ_BYTE7<br />
MEM_40S<br />
MEM_DATA MEM_A_DM<br />
14A7 26C4<br />
14A7 26C2<br />
14B7 26B4<br />
14B7 26C2<br />
14B7 26B5<br />
14B7 26B7<br />
14B7 26B5<br />
14B7 26A7<br />
C<br />
MEM_CLK MEM_CMD<br />
*<br />
MEM_CLK<br />
MEM_CLK MEM_DQS<br />
*<br />
NET_SPACING_TYPE1<br />
MEM_CTRL<br />
MEM_CTRL<br />
MEM_CTRL<br />
MEM_CTRL<br />
NET_SPACING_TYPE1<br />
MEM_DATA *<br />
NET_SPACING_TYPE2<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
MEM_CLK *<br />
MEM_CTRL *<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
MEM_CMD * MEM_CTRL2MEM<br />
MEM_DATA<br />
MEM_CTRL2MEM<br />
MEM_CTRL MEM_DQS<br />
* MEM_CTRL2MEM<br />
MEM_DQS<br />
*<br />
MEM_CLK2MEM<br />
MEM_CLK2MEM<br />
MEM_CLK2MEM<br />
MEM_CTRL2MEM<br />
MEM_CTRL2CTRL<br />
SPACING_RULE_SET<br />
MEM_CLK * MEM_DQS2MEM<br />
MEM_CMD MEM_CMD *<br />
MEM_CMD2CMD<br />
MEM_CMD<br />
MEM_CMD MEM_DQS<br />
*<br />
NET_SPACING_TYPE1<br />
MEM_DATA<br />
NET_SPACING_TYPE1<br />
MEM_DATA<br />
NET_SPACING_TYPE2<br />
MEM_CLK<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
MEM_DATA MEM_CMD<br />
*<br />
MEM_DATA MEM_DATA<br />
*<br />
MEM_DATA MEM_DQS<br />
*<br />
AREA_TYPE<br />
MEM_CLK *<br />
*<br />
MEM_CMD2MEM<br />
SPACING_RULE_SET<br />
* MEM_DATA2MEM<br />
MEM_DATA MEM_CTRL<br />
* MEM_DATA2MEM<br />
*<br />
MEM_CMD2MEM<br />
MEM_DATA2MEM<br />
MEM_DATA2DATA<br />
MEM_DATA2MEM<br />
SPACING_RULE_SET<br />
MEM_2OTHER<br />
MEM_A_DQS0<br />
MEM_A_DQS0<br />
MEM_A_DQS1<br />
MEM_A_DQS1<br />
MEM_A_DQS2<br />
MEM_A_DQS2<br />
MEM_A_DQS3<br />
MEM_A_DQS3<br />
MEM_A_DQS4<br />
MEM_A_DQS4<br />
MEM_A_DQS5<br />
MEM_A_DQS5<br />
MEM_A_DQS6<br />
MEM_A_DQS6<br />
MEM_A_DQS7<br />
MEM_A_DQS7<br />
MEM_70D<br />
MEM_DQS<br />
MEM_A_DQS_P<br />
MEM_70D MEM_DQS MEM_A_DQS_N<br />
MEM_70D<br />
MEM_DQS<br />
MEM_A_DQS_P<br />
MEM_70D MEM_DQS MEM_A_DQS_N<br />
MEM_70D MEM_DQS MEM_A_DQS_P<br />
MEM_70D<br />
MEM_DQS<br />
MEM_A_DQS_N<br />
MEM_70D MEM_DQS MEM_A_DQS_P<br />
MEM_70D MEM_DQS MEM_A_DQS_N<br />
MEM_70D MEM_DQS MEM_A_DQS_P<br />
MEM_70D<br />
MEM_DQS<br />
MEM_A_DQS_N<br />
MEM_70D MEM_DQS MEM_A_DQS_P<br />
MEM_70D MEM_DQS MEM_A_DQS_N<br />
MEM_70D<br />
MEM_DQS<br />
MEM_A_DQS_P<br />
MEM_70D<br />
MEM_DQS<br />
MEM_A_DQS_N<br />
MEM_70D MEM_DQS MEM_A_DQS_P<br />
MEM_70D<br />
MEM_DQS<br />
MEM_A_DQS_N<br />
MEM_B_CLK MEM_70D_VDD MEM_CLK MEM_B_CLK_P<br />
MEM_B_CLK<br />
MEM_70D_VDD MEM_CLK<br />
MEM_B_CLK_N<br />
14D5 26C2<br />
14D5 26D2<br />
14D5 26C4<br />
14D5 26C4<br />
14D5 26B2<br />
14D5 26C2<br />
14D5 26C4<br />
14D5 26C4<br />
14D5 26B7<br />
14D5 26B7<br />
14D5 26B5<br />
14D5 26B5<br />
14D5 26B7<br />
14D5 26B7<br />
14D5 26A5<br />
14D5 26A5<br />
14B1 27C5 27C7<br />
14B1 27C5 27C7<br />
C<br />
B<br />
MEM_DQS<br />
MEM_DQS<br />
MEM_DQS<br />
MEM_DQS<br />
MEM_CTRL * MEM_DQS2MEM<br />
MEM_CMD<br />
MEM_DATA * MEM_DQS2MEM<br />
MEM_DQS<br />
MEM_DQS2MEM<br />
Need to support MEM_*-style wildcards!<br />
DDR2:<br />
DQ signals should be matched within 20 ps of associated DQS pair.<br />
DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.<br />
All DQS pairs should be matched within 100 ps of clocks.<br />
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.<br />
A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.<br />
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).<br />
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.<br />
DDR3:<br />
DQ signals should be matched within 5 ps of associated DQS pair.<br />
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps<br />
No DQS to clock matching requirement.<br />
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.<br />
A/BA/cmd signals should be matched within 5 ps of CLK pairs.<br />
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).<br />
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.<br />
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3<br />
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2<br />
*<br />
*<br />
MEM_DQS2MEM<br />
MEM_CTRL * *<br />
MEM_CMD *<br />
*<br />
MEM_DATA * *<br />
MEM_DQS *<br />
*<br />
MEM_2OTHER<br />
MEM_2OTHER<br />
MEM_2OTHER<br />
MEM_2OTHER<br />
MEM_B_CNTL<br />
MEM_B_CNTL<br />
MEM_B_CNTL<br />
MEM_B_CMD<br />
MEM_B_CMD<br />
MEM_B_CMD<br />
MEM_B_CMD<br />
MEM_B_CMD<br />
MEM_B_DQ_BYTE0<br />
MEM_B_DQ_BYTE1<br />
MEM_B_DQ_BYTE2<br />
MEM_B_DQ_BYTE3<br />
MEM_B_DQ_BYTE4<br />
MEM_B_DQ_BYTE5<br />
MEM_B_DQ_BYTE6<br />
MEM_B_DQ_BYTE7<br />
MEM_B_DQ_BYTE0<br />
MEM_B_DQ_BYTE1<br />
MEM_B_DQ_BYTE2<br />
MEM_B_DQ_BYTE3<br />
MEM_B_DQ_BYTE4<br />
MEM_B_DQ_BYTE5<br />
MEM_B_DQ_BYTE6<br />
MEM_B_DQ_BYTE7<br />
MEM_40S_VDD<br />
MEM_40S_VDD<br />
MEM_40S_VDD<br />
MEM_40S<br />
MEM_40S<br />
MEM_40S<br />
MEM_40S<br />
MEM_CTRL<br />
MEM_DATA<br />
MEM_DATA<br />
MEM_DATA<br />
MEM_DATA<br />
MEM_B_CKE<br />
MEM_B_CS_L<br />
MEM_B_ODT<br />
MEM_40S_VDD MEM_CMD<br />
MEM_B_A<br />
MEM_40S_VDD MEM_CMD MEM_B_BA<br />
MEM_40S_VDD MEM_CMD MEM_B_RAS_L<br />
MEM_40S_VDD MEM_CMD MEM_B_CAS_L<br />
MEM_40S_VDD MEM_CMD MEM_B_WE_L<br />
MEM_40S<br />
MEM_40S<br />
MEM_40S<br />
MEM_40S<br />
MEM_40S<br />
MEM_40S<br />
MEM_40S<br />
MEM_40S<br />
MEM_40S<br />
MEM_40S<br />
MEM_40S<br />
MEM_40S<br />
MEM_CTRL<br />
MEM_CTRL<br />
MEM_DATA<br />
MEM_DATA<br />
MEM_DATA<br />
MEM_DATA<br />
MEM_DATA<br />
MEM_DATA<br />
MEM_DATA<br />
MEM_DATA<br />
MEM_DATA<br />
MEM_DATA<br />
MEM_DATA<br />
MEM_DATA<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DM<br />
MEM_B_DM<br />
MEM_B_DM<br />
MEM_B_DM<br />
MEM_B_DM<br />
MEM_B_DM<br />
MEM_B_DM<br />
MEM_B_DM<br />
14A1 27D5 27D7<br />
14B1 27C5 27C7<br />
14B1 27C5<br />
14B1 14C1 27C5 27C7<br />
14C1 27C5 27C7<br />
14C1 27C5<br />
14C1 27C7<br />
14C1 27C7<br />
14B3 27C2 27C4 27D2 27D4<br />
14B3 27C2 27C4<br />
14B3 14C3 27C2 27C4<br />
14C3 27B2 27B4 27C2 27C4<br />
14C3 27B5 27B7 27C5 27C7<br />
14C3 14D3 27B5 27B7<br />
14D3 27B5 27B7<br />
14D3 27A5 27A7 27B5 27B7<br />
14A3 27C4<br />
14A3 27C2<br />
14B3 27C2<br />
14B3 27B4<br />
14B3 27B5<br />
14B3 27B7<br />
14B3 27B5<br />
14B3 27A7<br />
B<br />
A<br />
MCP MEM COMP Signal Constraints<br />
PHYSICAL_RULE_SET<br />
SPACING_RULE_SET<br />
MCP_MEM_COMP<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
MCP_MEM_COMP * Y<br />
7 MIL<br />
7 MIL<br />
=STANDARD<br />
=STANDARD =STANDARD<br />
LAYER<br />
LINE-TO-LINE SPACING<br />
* 8 MIL<br />
?<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4<br />
MEM_B_DQS0<br />
MEM_B_DQS0<br />
MEM_B_DQS1<br />
MEM_B_DQS1<br />
MEM_B_DQS2<br />
MEM_B_DQS2<br />
MEM_B_DQS3<br />
MEM_B_DQS3<br />
MEM_B_DQS4<br />
MEM_B_DQS4<br />
MEM_B_DQS5<br />
MEM_B_DQS5<br />
MEM_B_DQS6<br />
MEM_B_DQS6<br />
MEM_B_DQS7<br />
MEM_B_DQS7<br />
MCP_MEM_COMP<br />
MCP_MEM_COMP<br />
MEM_70D<br />
MEM_70D<br />
MEM_70D<br />
MEM_70D<br />
MEM_70D<br />
MEM_70D<br />
MEM_70D<br />
MEM_70D<br />
MEM_70D<br />
MEM_70D<br />
MEM_70D<br />
MEM_70D<br />
MEM_70D<br />
MEM_70D<br />
MEM_70D<br />
MEM_70D<br />
MCP_MEM_COMP<br />
MCP_MEM_COMP<br />
MEM_DQS<br />
MEM_DQS<br />
MEM_DQS<br />
MEM_DQS<br />
MEM_DQS<br />
MEM_DQS<br />
MEM_DQS<br />
MEM_DQS<br />
MEM_DQS<br />
MEM_DQS<br />
MEM_DQS<br />
MEM_DQS<br />
MEM_DQS<br />
MEM_DQS<br />
MEM_DQS<br />
MEM_DQS<br />
MCP_MEM_COMP<br />
MCP_MEM_COMP<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MCP_MEM_COMP_VDD<br />
MCP_MEM_COMP_GND<br />
14D1 27C2<br />
14D1 27D2<br />
14D1 27C4<br />
14D1 27C4<br />
14D1 27C4<br />
14D1 27C4<br />
14D1 27B2<br />
14D1 27C2<br />
14D1 27B7<br />
14D1 27B7<br />
14D1 27B5<br />
14D1 27B5<br />
14D1 27B7<br />
14D1 27B7<br />
14D1 27A5<br />
14D1 27A5<br />
15C6<br />
15C6<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
Memory Constraints<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
SYNC_DATE=01/04/2008<br />
A<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
74 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
8 7 6 5 4 3 2 1<br />
PCI-Express<br />
ELECTRICAL_CONSTRAINT_SET<br />
NET_TYPE<br />
PHYSICAL<br />
SPACING<br />
PHYSICAL_RULE_SET<br />
SPACING_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF<br />
CLK_PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF<br />
=100_OHM_DIFF =100_OHM_DIFF<br />
LAYER<br />
LINE-TO-LINE SPACING<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
SPACING_RULE_SET<br />
LAYER<br />
LINE-TO-LINE SPACING<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
PCIE_MINI_R2D<br />
PCIE_MINI_D2R<br />
PCIE_90D<br />
PCIE_90D<br />
PCIE_90D<br />
PCIE_90D<br />
PCIE_90D<br />
PCIE_90D<br />
PCIE<br />
PCIE<br />
PCIE<br />
PCIE<br />
PCIE<br />
PCIE<br />
PCIE_MINI_R2D_P<br />
PCIE_MINI_R2D_N<br />
PCIE_MINI_R2D_C_P<br />
PCIE_MINI_R2D_C_N<br />
PCIE_MINI_D2R_P<br />
PCIE_MINI_D2R_N<br />
6D5 29C7<br />
6D5 29C7<br />
16B3 29C5<br />
16B3 29C5<br />
6D5 16B6 29C7<br />
6D5 16B6 29C7<br />
D<br />
PCIE * =3X_DIELECTRIC<br />
?<br />
CLK_PCIE<br />
* 20 MIL<br />
?<br />
MCP_PEX_COMP * 8 MIL ?<br />
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4<br />
PCIE TOP,BOTTOM =4X_DIELECTRIC ?<br />
PCIE_FW_R2D<br />
PCIE_FW_D2R<br />
PCIE_90D<br />
PCIE_90D<br />
PCIE_90D<br />
PCIE_90D<br />
PCIE_90D<br />
PCIE_90D<br />
PCIE_90D<br />
PCIE_90D<br />
PCIE<br />
PCIE<br />
PCIE<br />
PCIE<br />
PCIE<br />
PCIE<br />
PCIE<br />
PCIE<br />
PCIE_FW_R2D_P<br />
PCIE_FW_R2D_N<br />
PCIE_FW_R2D_C_P<br />
PCIE_FW_R2D_C_N<br />
PCIE_FW_D2R_P<br />
PCIE_FW_D2R_N<br />
PCIE_FW_D2R_C_P<br />
PCIE_FW_D2R_C_N<br />
34C3<br />
34C3<br />
16B3 34C1<br />
16B3 34C1<br />
16B6 34C1<br />
16B6 34C1<br />
34C3<br />
34C3<br />
D<br />
MCP_PE1_REFCLK<br />
CLK_PCIE_100D<br />
CLK_PCIE_100D<br />
CLK_PCIE_100D<br />
CLK_PCIE_100D<br />
CLK_PCIE<br />
CLK_PCIE<br />
CLK_PCIE<br />
CLK_PCIE<br />
PCIE_CLK100M_MINI_P<br />
PCIE_CLK100M_MINI_N<br />
PCIE_CLK100M_MINI_CONN_P<br />
PCIE_CLK100M_MINI_CONN_N<br />
16C3 29C5<br />
16C3 29C5<br />
6D5 29C7<br />
6D5 29C7<br />
MCP_PE4_REFCLK<br />
CLK_PCIE_100D<br />
CLK_PCIE_100D<br />
CLK_PCIE<br />
CLK_PCIE<br />
PCIE_CLK100M_FC_P<br />
PCIE_CLK100M_FC_N<br />
MCP_PEX_CLK_COMP MCP_PEX_COMP MCP_PEX_CLK_COMP<br />
16A6<br />
C<br />
Digital Video Signal Constraints<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
C<br />
DP_100D<br />
* =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF<br />
LVDS_100D<br />
MCP_DV_COMP<br />
* =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF<br />
* Y 20 MIL 20 MIL =STANDARD =STANDARD =STANDARD<br />
TMDS_IG_TXC DP_100D DISPLAYPORT<br />
TMDS_IG_TXC<br />
TMDS_IG_TXD<br />
DP_100D<br />
DP_100D<br />
DISPLAYPORT<br />
DISPLAYPORT<br />
TMDS_IG_TXC_P<br />
TMDS_IG_TXC_N<br />
TMDS_IG_TXD_P<br />
TMDS_IG_TXD DP_100D DISPLAYPORT TMDS_IG_TXD_N<br />
B<br />
SPACING_RULE_SET<br />
DISPLAYPORT<br />
LVDS<br />
PHYSICAL_RULE_SET<br />
SPACING_RULE_SET<br />
LAYER<br />
*<br />
*<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
LAYER<br />
LINE-TO-LINE SPACING<br />
=3x_DIELECTRIC ?<br />
=3x_DIELECTRIC ?<br />
LINE-TO-LINE SPACING<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
SPACING_RULE_SET<br />
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.<br />
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.<br />
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.<br />
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.<br />
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.<br />
SATA Interface Constraints<br />
SATA_100D<br />
SATA_90D_HDD<br />
SATA *<br />
*<br />
SPACING_RULE_SET<br />
LAYER<br />
LAYER<br />
LINE-TO-LINE SPACING<br />
DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ?<br />
LVDS TOP,BOTTOM =4x_DIELECTRIC ?<br />
SATA<br />
TOP,BOTTOM<br />
LINE-TO-LINE SPACING<br />
=3x_DIELECTRIC ?<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF<br />
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF<br />
* =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF<br />
=4x_DIELECTRIC<br />
?<br />
=90_OHM_DIFF<br />
=90_OHM_DIFF<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
=90_OHM_DIFF<br />
DP_ML DP_100D DISPLAYPORT DP_ML_P<br />
DP_100D<br />
DISPLAYPORT DP_ML_C_P<br />
DP_ML<br />
DP_100D<br />
DISPLAYPORT DP_ML_N<br />
DP_100D<br />
DISPLAYPORT DP_ML_C_N<br />
DP_AUX_CH<br />
DP_100D<br />
DISPLAYPORT DP_IG_AUX_CH_P<br />
DP_100D<br />
DISPLAYPORT DP_IG_AUX_CH_N<br />
DP_100D<br />
DISPLAYPORT DP_AUX_CH_SW_P<br />
DP_100D<br />
DISPLAYPORT DP_AUX_CH_SW_N<br />
DP_100D<br />
DISPLAYPORT DP_AUX_CH_C_P<br />
DP_100D DISPLAYPORT DP_AUX_CH_C_N<br />
MCP_HDMI_RSET<br />
MCP_HDMI_VPROBE<br />
LVDS_IG_A_CLK<br />
LVDS_IG_A_CLK<br />
LVDS_IG_A_DATA<br />
MCP_DV_COMP<br />
MCP_DV_COMP<br />
LVDS_100D<br />
LVDS_100D<br />
LVDS_100D<br />
LVDS_100D<br />
LVDS_100D<br />
LVDS<br />
LVDS<br />
LVDS<br />
LVDS<br />
LVDS<br />
MCP_HDMI_RSET<br />
MCP_HDMI_VPROBE<br />
LVDS_IG_A_CLK_P<br />
LVDS_IG_A_CLK_F_P<br />
LVDS_IG_A_CLK_N<br />
LVDS_IG_A_CLK_F_N<br />
LVDS_IG_A_DATA_P<br />
LVDS_IG_A_DATA LVDS_100D<br />
LVDS LVDS_IG_A_DATA_N<br />
69D1 70C1 70C8<br />
70C2 70C7<br />
69D1 70C1 70C8<br />
70C2 70C7<br />
17B6 69C7<br />
17B6 69C7<br />
69C6<br />
69C5<br />
69C4 70C8<br />
69D4 70C8<br />
17A6 23C7<br />
17A6 23C7<br />
17B3 68B3<br />
6C7 68C2<br />
17B3 68B3<br />
6C7 68C2<br />
6C7 17B3 68C2<br />
6C7 17B3 68C2<br />
B<br />
SATA_TERMP * 8 MIL<br />
?<br />
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.<br />
I183<br />
I182<br />
DP_ML<br />
DP_100D<br />
DP_100D<br />
DISPLAYPORT<br />
DISPLAYPORT<br />
DP_ML_CONN_P<br />
DP_ML_CONN_N<br />
70C3 70C4 70C5<br />
70C3 70C4 70C5<br />
MCP_IFPAB_RSET<br />
MCP_IFPAB_VPROBE<br />
MCP_DV_COMP<br />
MCP_IFPAB_RSET<br />
MCP_IFPAB_VPROBE<br />
17A3 23C6<br />
17A3 23C6<br />
A<br />
SATA_HDD_R2D SATA_90D_HDD SATA SATA_HDD_R2D_C_P<br />
SATA_90D_HDD SATA<br />
SATA_HDD_R2D_C_N<br />
SATA_90D_HDD SATA<br />
SATA_HDD_R2D_P<br />
SATA_90D_HDD SATA<br />
SATA_HDD_R2D_N<br />
SATA_90D_HDD SATA<br />
SATA_HDD_R2D_UF_P<br />
SATA_90D_HDD SATA<br />
SATA_HDD_R2D_UF_N<br />
SATA_HDD_D2R<br />
SATA_90D_HDD SATA<br />
SATA_HDD_D2R_P<br />
SATA_90D_HDD SATA<br />
SATA_HDD_D2R_N<br />
SATA_90D_HDD SATA<br />
SATA_HDD_D2R_C_P<br />
SATA_90D_HDD SATA<br />
SATA_HDD_D2R_C_N<br />
SATA_90D_HDD SATA<br />
SATA_HDD_D2R_UF_P<br />
SATA_90D_HDD SATA<br />
SATA_HDD_D2R_UF_N<br />
SATA_ODD_R2D SATA_100D SATA SATA_ODD_R2D_C_P<br />
SATA_100D<br />
SATA<br />
SATA_ODD_R2D_C_N<br />
SATA_100D<br />
SATA<br />
SATA_ODD_R2D_P<br />
SATA_100D SATA SATA_ODD_R2D_N<br />
SATA_100D SATA SATA_ODD_R2D_UF_P<br />
SATA_100D SATA SATA_ODD_R2D_UF_N<br />
SATA_ODD_D2R<br />
SATA_100D<br />
SATA<br />
SATA_ODD_D2R_P<br />
SATA_100D<br />
SATA<br />
SATA_ODD_D2R_N<br />
SATA_100D<br />
SATA<br />
SATA_ODD_D2R_C_P<br />
SATA_100D<br />
SATA<br />
SATA_ODD_D2R_C_N<br />
SATA_100D<br />
SATA<br />
SATA_ODD_D2R_UF_P<br />
SATA_100D SATA SATA_ODD_D2R_UF_N<br />
MCP_SATA_TERMP SATA_TERMP MCP_SATA_TERMP<br />
19D6 37A2<br />
19D6 37A2<br />
6B7 37A5<br />
6B7 37A5<br />
37A4<br />
37A4<br />
19D6 37B2<br />
19D6 37B2<br />
6B7 37B5<br />
6B7 37B5<br />
37B4<br />
37B4<br />
19D6 37C3<br />
19D6 37C3<br />
6B7 37C6<br />
6A7 6B7 37C6<br />
37C4<br />
37C4<br />
19D6 37C3<br />
19D6 37C3<br />
6B7 37C6<br />
6B7 37C6<br />
37C4<br />
37C4<br />
19A6<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
APPLE INC.<br />
MCP Constraints 1<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
75<br />
SYNC_DATE=01/04/2008<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
A<br />
8 7 6 5 4 3 2 1
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
8 7 6 5 4 3 2 1<br />
PCI Bus Constraints<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
ELECTRICAL_CONSTRAINT_SET<br />
PHYSICAL<br />
NET_TYPE<br />
SPACING<br />
D<br />
PCI_55S<br />
CLK_PCI_55S<br />
SPACING_RULE_SET<br />
PHYSICAL_RULE_SET<br />
SPACING_RULE_SET<br />
LAYER<br />
LPC Bus Constraints<br />
* =55_OHM_SE<br />
=55_OHM_SE<br />
=55_OHM_SE<br />
=55_OHM_SE<br />
=STANDARD<br />
=STANDARD<br />
*<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
LAYER<br />
=55_OHM_SE<br />
LINE-TO-LINE SPACING<br />
LINE-TO-LINE SPACING<br />
=55_OHM_SE<br />
PCI *<br />
=STANDARD<br />
?<br />
CLK_PCI *<br />
8 MIL<br />
?<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1.<br />
=55_OHM_SE<br />
=55_OHM_SE<br />
=STANDARD<br />
LPC_55S * =55_OHM_SE<br />
=55_OHM_SE<br />
=55_OHM_SE<br />
=55_OHM_SE<br />
=STANDARD<br />
CLK_LPC_55S<br />
LPC *<br />
6 MIL<br />
?<br />
CLK_LPC<br />
*<br />
=55_OHM_SE<br />
=55_OHM_SE<br />
* 8 MIL<br />
?<br />
=55_OHM_SE<br />
=55_OHM_SE<br />
=STANDARD<br />
=STANDARD<br />
=STANDARD<br />
=STANDARD<br />
MCP_DEBUG<br />
PCI_55S<br />
PCI<br />
MCP_DEBUG<br />
PCI_AD<br />
PCI_55S<br />
PCI<br />
PCI_AD<br />
PCI_AD24<br />
PCI_55S<br />
PCI<br />
PCI_AD<br />
PCI_AD<br />
PCI_55S PCI PCI_AD<br />
PCI_AD<br />
PCI_55S<br />
PCI<br />
PCI_PAR<br />
PCI_C_BE_L PCI_55S PCI<br />
PCI_C_BE_L<br />
PCI_CNTL<br />
PCI_55S<br />
PCI<br />
PCI_IRDY_L<br />
PCI_CNTL<br />
PCI_55S<br />
PCI<br />
PCI_DEVSEL_L<br />
PCI_CNTL<br />
PCI_55S<br />
PCI<br />
PCI_PERR_L<br />
PCI_CNTL<br />
PCI_55S<br />
PCI<br />
PCI_SERR_L<br />
PCI_CNTL<br />
PCI_55S<br />
PCI<br />
PCI_STOP_L<br />
PCI_CNTL<br />
PCI_55S<br />
PCI<br />
PCI_TRDY_L<br />
PCI_CNTL PCI_55S PCI<br />
PCI_FRAME_L<br />
PCI_REQ0_L<br />
PCI_55S<br />
PCI<br />
PCI_REQ0_L<br />
PCI_GNT0_L PCI_55S PCI<br />
PCI_GNT0_L<br />
PCI_REQ1_L<br />
PCI_55S PCI PCI_REQ1_L<br />
PCI_GNT1_L<br />
PCI_55S<br />
PCI<br />
PCI_GNT1_L<br />
PCI_INTW_L<br />
PCI_55S<br />
PCI<br />
PCI_INTW_L<br />
PCI_INTX_L PCI_55S PCI<br />
PCI_INTX_L<br />
PCI_INTY_L<br />
PCI_55S<br />
PCI<br />
PCI_INTY_L<br />
PCI_INTZ_L<br />
PCI_55S<br />
PCI<br />
PCI_INTZ_L<br />
MCP_PCI_CLK2<br />
CLK_PCI_55S<br />
CLK_PCI_55S<br />
CLK_PCI<br />
CLK_PCI<br />
PCI_CLK33M_MCP_R<br />
PCI_CLK33M_MCP<br />
12C3 18D7<br />
18D2 18D7<br />
18D2 18D7<br />
18C5<br />
18C5<br />
D<br />
USB 2.0 Interface Constraints<br />
PHYSICAL_RULE_SET<br />
MCP_USB_RBIAS<br />
USB_90D<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
* =STANDARD<br />
8 MIL<br />
8 MIL<br />
=STANDARD<br />
=STANDARD<br />
=STANDARD<br />
* =90_OHM_DIFF =90_OHM_DIFF<br />
=90_OHM_DIFF<br />
=90_OHM_DIFF<br />
=90_OHM_DIFF<br />
=90_OHM_DIFF<br />
LPC_AD<br />
LPC_FRAME_L<br />
LPC_RESET_L<br />
MCP_LPC_CLK0<br />
LPC_55S<br />
LPC_55S<br />
LPC_55S<br />
LPC<br />
LPC<br />
LPC<br />
LPC_AD<br />
LPC_FRAME_L<br />
LPC_RESET_L<br />
CLK_LPC_55S CLK_LPC<br />
LPC_CLK33M_SMC_R<br />
CLK_LPC_55S CLK_LPC LPC_CLK33M_SMC<br />
CLK_LPC_55S CLK_LPC LPC_CLK33M_LPCPLUS<br />
18B3 40C8 42D3 42D5<br />
18C3 40C8 42D5<br />
18C3 24D4<br />
18B3 24B4<br />
24B1 40C8<br />
24B1 42D3<br />
C<br />
SPACING_RULE_SET<br />
LAYER<br />
LINE-TO-LINE SPACING<br />
USB * =2x_DIELECTRIC<br />
?<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.<br />
SMBus Interface Constraints<br />
SPACING_RULE_SET<br />
USB<br />
LAYER<br />
LINE-TO-LINE SPACING<br />
TOP,BOTTOM =4x_DIELECTRIC<br />
?<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
USB_EXTA<br />
USB_90D<br />
USB_90D<br />
USB_90D<br />
USB_90D<br />
USB_90D<br />
USB_90D<br />
USB<br />
USB<br />
USB<br />
USB<br />
USB<br />
USB<br />
USB_EXTA_P<br />
USB_EXTA_N<br />
USB_EXTA_MUXED_P<br />
USB_EXTA_MUXED_N<br />
CONN_USB_EXTA_P<br />
CONN_USB_EXTA_N<br />
19D3 38A8<br />
19D3 38A8<br />
38C4<br />
38C4<br />
38C3<br />
38C3<br />
C<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
B<br />
SMB_55S<br />
SPACING_RULE_SET<br />
PHYSICAL_RULE_SET<br />
SPACING_RULE_SET<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
LAYER<br />
LINE-TO-LINE SPACING<br />
SMB * =2x_DIELECTRIC<br />
?<br />
LINE-TO-LINE SPACING<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1.<br />
HD Audio Interface Constraints<br />
HDA_55S *<br />
=55_OHM_SE<br />
=55_OHM_SE<br />
=55_OHM_SE<br />
=55_OHM_SE<br />
=STANDARD =STANDARD<br />
HDA<br />
MCP_HDA_COMP<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1.<br />
SIO Signal Constraints<br />
CLK_SLOW_55S<br />
* =55_OHM_SE<br />
*<br />
=2x_DIELECTRIC<br />
=55_OHM_SE<br />
* 8 MIL<br />
?<br />
?<br />
=55_OHM_SE<br />
=55_OHM_SE<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
* =55_OHM_SE<br />
=55_OHM_SE<br />
=55_OHM_SE<br />
=55_OHM_SE<br />
=STANDARD<br />
=STANDARD<br />
=STANDARD<br />
=STANDARD<br />
USB_CAMERA<br />
USB_BT<br />
USB_TPAD<br />
USB_IR<br />
USB_EXTB<br />
USB_SD<br />
MCP_USB_RBIAS<br />
USB_90D<br />
USB<br />
USB_CAMERA_P<br />
USB_90D<br />
USB<br />
USB_CAMERA_N<br />
USB_90D USB USB_CAMERA_CONN_P<br />
USB_90D<br />
USB<br />
USB_CAMERA_CONN_N<br />
USB_90D USB USB_BT_P<br />
USB_90D<br />
USB<br />
USB_BT_N<br />
USB_90D<br />
USB<br />
CONN_USB2_BT_P<br />
USB_90D<br />
USB<br />
CONN_USB2_BT_N<br />
USB_90D<br />
USB<br />
USB_TPAD_P<br />
USB_90D<br />
USB<br />
USB_TPAD_N<br />
USB_90D<br />
USB<br />
USB_TPAD_R_P<br />
USB_90D<br />
USB<br />
USB_TPAD_R_N<br />
USB_90D<br />
USB<br />
USB_IR_P<br />
USB_90D<br />
USB<br />
USB_IR_N<br />
USB_90D<br />
USB<br />
USB_EXTB_P<br />
USB_90D<br />
USB<br />
USB_EXTB_N<br />
USB_90D USB CONN_USB_EXTB_P<br />
USB_90D<br />
USB<br />
CONN_USB_EXTB_N<br />
USB_90D<br />
USB<br />
USB_CARDREADER_P<br />
USB_90D<br />
USB<br />
USB_CARDREADER_N<br />
MCP_USB_RBIAS<br />
MCP_USB_RBIAS_GND<br />
19D3 29B5<br />
19D3 29B5<br />
6D5 29B7<br />
6D5 29B7<br />
19D3 29B5<br />
19C3 29B5<br />
6D5 29B7<br />
6D5 29B7<br />
19D3 48B8<br />
19D3 48B8<br />
48B7<br />
48B7<br />
19D3 39D7<br />
19D3 39D7<br />
19C3 38A4<br />
19C3 38B4<br />
38B3<br />
38B3<br />
19C3 30C7<br />
19C3 30C7<br />
19C4<br />
B<br />
SPACING_RULE_SET<br />
LAYER<br />
CLK_SLOW *<br />
LINE-TO-LINE SPACING<br />
8 MIL ?<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
SMBUS_MCP_0_CLK<br />
SMB_55S<br />
SMB<br />
SMBUS_MCP_0_CLK<br />
SMBUS_MCP_0_DATA SMB_55S<br />
SMB SMBUS_MCP_0_DATA<br />
SMBUS_MCP_1_CLK<br />
SMB_55S<br />
SMB<br />
SMBUS_MCP_1_CLK<br />
SMBUS_MCP_1_DATA<br />
SMB_55S<br />
SMB<br />
SMBUS_MCP_1_DATA<br />
12B6 20C3 43D8<br />
12B6 20C3 43D8<br />
20C3 43B8<br />
20C3 43B8<br />
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.<br />
SPI Interface Constraints<br />
PHYSICAL_RULE_SET<br />
SPI_55S<br />
SPACING_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
* =55_OHM_SE<br />
=55_OHM_SE<br />
=55_OHM_SE<br />
=55_OHM_SE<br />
=STANDARD =STANDARD<br />
LAYER<br />
SPI *<br />
LINE-TO-LINE SPACING<br />
8 MIL ?<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
HDA_BIT_CLK<br />
HDA_SYNC<br />
HDA_RST_L<br />
HDA_SDIN0<br />
HDA_SDOUT<br />
HDA_55S<br />
HDA_55S<br />
HDA_55S<br />
HDA_55S<br />
HDA_55S<br />
HDA_55S<br />
HDA_55S<br />
HDA_55S<br />
HDA_55S<br />
HDA_55S<br />
HDA<br />
HDA<br />
HDA<br />
HDA<br />
HDA<br />
HDA<br />
HDA<br />
HDA<br />
HDA<br />
HDA<br />
HDA_BIT_CLK<br />
HDA_BIT_CLK_R<br />
HDA_SYNC<br />
HDA_SYNC_R<br />
HDA_RST_R_L<br />
HDA_RST_L<br />
HDA_SDIN0<br />
HDA_SDIN_CODEC<br />
HDA_SDOUT<br />
HDA_SDOUT_R<br />
20D2 52C7<br />
20A7 20D4<br />
20D2 52C7<br />
20A7 20D4<br />
20A7 20D4<br />
20D2 52C7<br />
20D7 52C7<br />
20D2 52C7<br />
20A7 20D4<br />
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14.<br />
MCP_HDA_PULLDN_COMP<br />
MCP_HDA_COMP MCP_HDA_PULLDN_COMP<br />
MCP_SUS_CLK CLK_SLOW_55S CLK_SLOW PM_CLK32K_SUSCLK_R<br />
CLK_SLOW_55S CLK_SLOW PM_CLK32K_SUSCLK<br />
20C7<br />
20B3 24B4<br />
24B1 40C5<br />
A<br />
SPI_CLK<br />
SPI_55S<br />
SPI<br />
SPI_CLK_R<br />
SPI_55S<br />
SPI<br />
SPI_CLK<br />
SPI_55S<br />
SPI<br />
SPI_ALT_CLK<br />
SPI_MOSI<br />
SPI_55S<br />
SPI<br />
SPI_MOSI_R<br />
SPI_55S SPI SPI_MOSI<br />
SPI_55S<br />
SPI<br />
SPI_ALT_MOSI<br />
SPI_MISO<br />
SPI_55S<br />
SPI<br />
SPI_MISO<br />
SPI_55S<br />
SPI<br />
SPI_MISO_R<br />
SPI_55S<br />
SPI<br />
SPI_ALT_MISO<br />
SPI_CS0 SPI_55S SPI<br />
SPI_CS0_R_L<br />
SPI_55S<br />
SPI<br />
SPI_CS0_L<br />
SPI_55S<br />
SPI<br />
SPI_CS1_R_L<br />
SPI_55S<br />
SPI<br />
SPI_CS1_R_L_USE_<strong>MLB</strong><br />
20B3 42A5 42C8<br />
51C5<br />
42C5 42D3<br />
20B3 42A5 42C7<br />
51C4<br />
42C5 42D5<br />
20B3 42A5 42B7<br />
51C4<br />
42B5 42D5<br />
20B3 42B7<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
APPLE INC.<br />
MCP Constraints 2<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
SYNC_DATE=12/14/2007<br />
OF<br />
76 81<br />
REV.<br />
4.7.0<br />
A<br />
8 7 6 5 4 3 2 1
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
8 7 6 5 4 3 2 1<br />
MCP RGMII (Ethernet) Constraints<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
ELECTRICAL_CONSTRAINT_SET<br />
NET_TYPE<br />
PHYSICAL<br />
SPACING<br />
MCP_MII_COMP * =STANDARD 7.5 MIL 7.5 MIL =STANDARD<br />
=STANDARD<br />
=STANDARD<br />
ENET_MII_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE<br />
=STANDARD<br />
=STANDARD<br />
MCP_MII_COMP<br />
MCP_MII_COMP<br />
MCP_MII_COMP<br />
MCP_MII_COMP<br />
MCP_MII_COMP_VDD<br />
MCP_MII_COMP_GND<br />
17C6<br />
17C6<br />
SPACING_RULE_SET<br />
LAYER<br />
LINE-TO-LINE SPACING<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
MCP_CLK25M_BUF0 ENET_MII_55S MCP_BUF0_CLK MCP_CLK25M_BUF0_R<br />
ENET_MII_55S MCP_BUF0_CLK RTL8211_CLK25M_CKXTAL1<br />
17C3 32A5<br />
31B6 32A3<br />
D<br />
MCP_BUF0_CLK * =3:1_SPACING<br />
?<br />
ENET_MII * 12 MIL<br />
?<br />
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4<br />
88E1116R (Ethernet PHY) Constraints<br />
PHYSICAL_RULE_SET<br />
ENET_MDI_100D<br />
SPACING_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
* =100_OHM_DIFF<br />
LAYER<br />
LINE-TO-LINE SPACING<br />
=100_OHM_DIFF<br />
ENET_MDI * 25 MIL<br />
?<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4<br />
=100_OHM_DIFF<br />
=100_OHM_DIFF<br />
=100_OHM_DIFF<br />
=100_OHM_DIFF<br />
ENET_INTR_L<br />
ENET_MDIO<br />
ENET_MDC<br />
ENET_PWRDWN_L<br />
ENET_RXCLK<br />
ENET_RXD<br />
ENET_RXD_STRAP<br />
ENET_RXD<br />
ENET_TXCLK<br />
ENET_TXD0<br />
ENET_TXD<br />
ENET_TXD<br />
ENET_MII_55S<br />
ENET_MII_55S<br />
ENET_MII_55S<br />
ENET_MII_55S<br />
ENET_MII<br />
ENET_MII<br />
ENET_MII<br />
ENET_MII<br />
ENET_INTR_L<br />
ENET_MDIO<br />
ENET_MDC<br />
ENET_PWRDWN_L<br />
ENET_MII_55S ENET_MII ENET_CLK125M_RXCLK_R<br />
ENET_MII_55S ENET_MII ENET_CLK125M_RXCLK<br />
ENET_MII_55S ENET_MII ENET_RXD_R<br />
ENET_MII_55S ENET_MII ENET_RXD<br />
ENET_MII_55S ENET_MII ENET_RXD<br />
ENET_MII_55S ENET_MII ENET_RX_CTRL<br />
ENET_MII_55S ENET_MII ENET_RXCTL_R<br />
ENET_MII_55S ENET_MII ENET_CLK125M_TXCLK_R<br />
ENET_MII_55S ENET_MII ENET_CLK125M_TXCLK<br />
ENET_MII_55S ENET_MII ENET_TXD<br />
ENET_MII_55S ENET_MII ENET_TXD<br />
ENET_MII_55S ENET_MII ENET_TX_CTRL<br />
17C3 31B6<br />
17D3 31B6<br />
31C4<br />
17D6 31C1<br />
31C4<br />
17D6 31C1<br />
17D6 31C1<br />
17D6 31B1<br />
31B4<br />
31C6<br />
17D3 31C8<br />
17D3 31C6<br />
17D3 31C6<br />
17D3 31B6<br />
D<br />
ENET_MII_55S<br />
ENET_MII<br />
ENET_RESET_L<br />
17C3 31B7<br />
ENET_MDI ENET_MDI_100D ENET_MDI ENET_MDI_P<br />
ENET_MDI_100D ENET_MDI ENET_MDI_N<br />
ENET_MDI_100D ENET_MDI ENET_MDI_TRAN_P<br />
ENET_MDI_100D ENET_MDI ENET_MDI_TRAN_N<br />
31B3 33B8 33C8<br />
31B3 33B8 33C8<br />
33B4 33C4 33C5<br />
33B4 33C4 33C5<br />
C<br />
C<br />
B<br />
B<br />
A<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
Ethernet Constraints<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=03/19/2008<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
77<br />
81<br />
8 7 6 5 4 3 2 1
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
8 7 6 5 4 3 2 1<br />
FireWire Interface Constraints<br />
FireWire Net Properties<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
ELECTRICAL_CONSTRAINT_SET<br />
PHYSICAL<br />
NET_TYPE<br />
SPACING<br />
D<br />
FW_110D =110_OHM_DIFF =110_OHM_DIFF<br />
* =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF<br />
=110_OHM_DIFF<br />
SPACING_RULE_SET<br />
LAYER<br />
LINE-TO-LINE SPACING<br />
FW_TP *<br />
=3:1_SPACING<br />
?<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
FW_P0_TPA<br />
FW_110D<br />
FW_TP<br />
FW_P0_TPA<br />
FW_110D<br />
FW_TP<br />
FW_P0_TPB<br />
FW_110D<br />
FW_TP<br />
FW_P0_TPB<br />
FW_110D<br />
FW_TP<br />
FW_P1_TPA<br />
FW_110D<br />
FW_TP<br />
FW_P1_TPA<br />
FW_110D<br />
FW_TP<br />
FW_P1_TPB FW_110D FW_TP<br />
FW_P1_TPB FW_110D FW_TP<br />
FW_P0_TPA_P<br />
FW_P0_TPA_N<br />
FW_P0_TPB_P<br />
FW_P0_TPB_N<br />
FW_P1_TPA_P<br />
FW_P1_TPA_N<br />
FW_P1_TPB_P<br />
FW_P1_TPB_N<br />
34B6 36C4<br />
34C6 36C4<br />
34B6 36C4<br />
34B6 36C4<br />
34B6 36B8<br />
34B6 36B8<br />
34B6 36B8<br />
34B6 36B8<br />
D<br />
Port 2 Not Used<br />
SD CARD NET PROPERTIES<br />
NET_TYPE<br />
SD CARD INTERFACE CONSTRAINTS<br />
PHYSICAL_RULE_SET<br />
SD_55S<br />
SPACING_RULE_SET<br />
SD_INTERFACE<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
*<br />
LAYER<br />
=55_OHM_SE =55_OHM_SE<br />
=55_OHM_SE =55_OHM_SE<br />
=STANDARD =STANDARD<br />
LINE-TO-LINE SPACING<br />
* =3X_DIELECTRIC<br />
?<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
ELECTRICAL_CONSTRAINT_SET<br />
PHYSICAL<br />
SPACING<br />
I23 SD_DATA<br />
SD_55S<br />
SD_INTERFACE<br />
I24 SD_DATA<br />
SD_55S<br />
SD_INTERFACE<br />
I25 SD_DATA<br />
SD_55S<br />
SD_INTERFACE<br />
I26 SD_DATA<br />
SD_55S<br />
SD_INTERFACE<br />
I27 SD_DATA<br />
SD_55S<br />
SD_INTERFACE<br />
I28 SD_DATA SD_55S SD_INTERFACE<br />
I29 SD_DATA<br />
SD_55S<br />
SD_INTERFACE<br />
I30 SD_DATA<br />
SD_55S<br />
SD_INTERFACE<br />
SD_D<br />
SD_D<br />
SD_D<br />
SD_D<br />
SD_D<br />
SD_D<br />
SD_D<br />
SD_D<br />
30C2<br />
30C2<br />
30C2<br />
30C2<br />
30C2<br />
30C2<br />
30C2<br />
30C2<br />
I32<br />
I31<br />
SD_CLK<br />
SD_CMD<br />
SD_55S<br />
SD_55S<br />
SD_INTERFACE<br />
SD_INTERFACE<br />
SD_CLK<br />
SD_CMD<br />
30C2<br />
30C2<br />
C<br />
C<br />
B<br />
B<br />
A<br />
SYNC_MASTER=K19_<strong>MLB</strong><br />
FireWire Constraints<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=12/01/2008<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
78<br />
81<br />
8 7 6 5 4 3 2 1
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
8 7 6 5 4 3 2 1<br />
SMC SMBus Net Properties<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
ELECTRICAL_CONSTRAINT_SET<br />
PHYSICAL<br />
NET_TYPE<br />
SPACING<br />
D<br />
1TO1_DIFFPAIR * =STANDARD =STANDARD<br />
=STANDARD<br />
=STANDARD<br />
0.1 MM<br />
0.1 MM<br />
SMBUS_SMC_A_S3_SCL<br />
SMB_55S<br />
SMB<br />
SMBUS_SMC_A_S3_SCL<br />
SMBUS_SMC_A_S3_SDA<br />
SMB_55S<br />
SMB<br />
SMBUS_SMC_A_S3_SDA<br />
SMBUS_SMC_B_S0_SCL<br />
SMB_55S<br />
SMB<br />
SMBUS_SMC_B_S0_SCL<br />
SMBUS_SMC_B_S0_SDA<br />
SMB_55S<br />
SMB<br />
SMBUS_SMC_B_S0_SDA<br />
SMBUS_SMC_0_S0_SCL<br />
SMB_55S SMB SMBUS_SMC_0_S0_SCL<br />
SMBUS_SMC_0_S0_SDA<br />
SMB_55S<br />
SMB<br />
SMBUS_SMC_0_S0_SDA<br />
SMBUS_SMC_BSA_SCL<br />
SMB_55S<br />
SMB<br />
SMBUS_SMC_BSA_SCL<br />
SMBUS_SMC_BSA_SDA<br />
SMB_55S<br />
SMB<br />
SMBUS_SMC_BSA_SDA<br />
SMBUS_SMC_MGMT_SCL SMB_55S SMB<br />
SMBUS_SMC_MGMT_SCL<br />
SMBUS_SMC_MGMT_SDA<br />
SMB_55S<br />
SMB<br />
SMBUS_SMC_MGMT_SDA<br />
6C5 6D5 43D2<br />
6C5 6D5 43D2<br />
43C2<br />
43C2<br />
43D5<br />
43D5<br />
6A7 43C5<br />
6A7 43C5<br />
43B5<br />
43B5<br />
D<br />
SMBus Charger Net Properties<br />
NET_TYPE<br />
ELECTRICAL_CONSTRAINT_SET<br />
PHYSICAL<br />
SPACING<br />
CHGR_CSI 1TO1_DIFFPAIR CHGR_CSI_P<br />
1TO1_DIFFPAIR<br />
CHGR_CSI_N<br />
CHGR_CSO 1TO1_DIFFPAIR CHGR_CSO_P<br />
1TO1_DIFFPAIR<br />
CHGR_CSO_N<br />
C<br />
C<br />
B<br />
B<br />
A<br />
SYNC_MASTER=T18_<strong>MLB</strong><br />
SMC Constraints<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
SYNC_DATE=01/04/2008<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
OF<br />
79 81<br />
REV.<br />
4.7.0<br />
8 7 6 5 4 3 2 1
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
8 7 6 5 4 3 2 1<br />
<strong>K24</strong> SENSOR NET PROPERTIES<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
ELECTRICAL_CONSTRAINT_SET<br />
PHYSICAL<br />
NET_TYPE<br />
SPACING<br />
D<br />
DIFFPAIR<br />
* =STANDARD<br />
=STANDARD<br />
=STANDARD<br />
=STANDARD<br />
0.1 MM<br />
0.1 MM<br />
DIFFPAIR<br />
DIFFPAIR<br />
DIFFPAIR<br />
DIFFPAIR<br />
DIFFPAIR<br />
DIFFPAIR<br />
DIFFPAIR<br />
DIFFPAIR<br />
DIFFPAIR<br />
DIFFPAIR<br />
DIFFPAIR<br />
DIFFPAIR<br />
DIFFPAIR<br />
DIFFPAIR<br />
DIFFPAIR<br />
DIFFPAIR<br />
CHGR_CSO_R_P<br />
CHGR_CSO_R_N<br />
CPUTHMSNS_D2_P<br />
CPUTHMSNS_D2_N<br />
CPU_THERMD_P<br />
CPU_THERMD_N<br />
ISNS_CPUVTT_P<br />
ISNS_CPUVTT_N<br />
ISNS_P1V5S0MCP_P<br />
ISNS_P1V5S0MCP_N<br />
ISNS_PVCORES0MCP_P<br />
ISNS_PVCORES0MCP_N<br />
MCPTHMSNS_D2_P<br />
MCPTHMSNS_D2_N<br />
MCP_THMDIODE_P<br />
MCP_THMDIODE_N<br />
45A8 59B3<br />
45A8 59B3<br />
46C5<br />
46C5<br />
9C6 46D5<br />
9C6 46D5<br />
45B7<br />
45B7<br />
6C7 46B5<br />
6C7 46B5<br />
20C3 46B5<br />
20C3 46B5<br />
D<br />
C<br />
C<br />
B<br />
B<br />
A<br />
<strong>K24</strong> SPECIAL CONSTRAINTS<br />
SYNC_MASTER=M97_<strong>MLB</strong><br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
051-7898<br />
80<br />
OF<br />
REV.<br />
81<br />
4.7.0<br />
8 7 6 5 4 3 2 1
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_BOARD_INFO<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_PHYSICAL_ASSIGNMENT_HEAD<br />
TABLE_PHYSICAL_ASSIGNMENT_ITEM<br />
TABLE_PHYSICAL_ASSIGNMENT_ITEM<br />
8 7 6 5 4 3 2 1<br />
<strong>K24</strong> BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS<br />
BOARD LAYERS<br />
BOARD AREAS<br />
BOARD UNITS<br />
(MIL or MM)<br />
ALLEGRO<br />
VERSION<br />
SPACING_RULE_SET<br />
LAYER<br />
LINE-TO-LINE SPACING<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
NET_PHYSICAL_TYPE<br />
AREA_TYPE<br />
PHYSICAL_RULE_SET<br />
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM<br />
NO_TYPE,BGA_P1MM<br />
MM<br />
15.5.1<br />
DEFAULT *<br />
0.1 MM<br />
?<br />
*<br />
*<br />
BGA_P1MM<br />
BGA_P1MM<br />
MEM_40S<br />
BGA_P1MM<br />
STANDARD<br />
PHYSICAL_RULE_SET<br />
DEFAULT<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
* Y<br />
=50_OHM_SE<br />
0.100MM<br />
30 MM<br />
0 MM<br />
0 MM<br />
STANDARD<br />
BGA_P1MM<br />
*<br />
=DEFAULT ?<br />
* =DEFAULT<br />
?<br />
MEM_CLK *<br />
BGA_P1MM BGA_P2MM<br />
CLK_FSB * BGA_P1MM<br />
BGA_P2MM<br />
MEM_40S_VDD BGA_P1MM STANDARD<br />
STANDARD<br />
=DEFAULT<br />
Y 12.7 MM =DEFAULT<br />
* =DEFAULT =DEFAULT<br />
BGA_P2MM<br />
*<br />
=DEFAULT<br />
?<br />
CLK_LPC<br />
* BGA_P1MM<br />
BGA_P2MM<br />
D<br />
PHYSICAL_RULE_SET<br />
55_OHM_SE<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
TOP,BOTTOM<br />
Y<br />
0.090 MM<br />
0.090 MM<br />
BGA_P3MM *<br />
=DEFAULT<br />
?<br />
SPACING_RULE_SET<br />
LAYER<br />
LINE-TO-LINE SPACING<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
CLK_PCI * BGA_P1MM<br />
BGA_P2MM<br />
CLK_PCIE * BGA_P1MM BGA_P2MM<br />
CLK_SLOW<br />
*<br />
BGA_P1MM<br />
BGA_P2MM<br />
D<br />
55_OHM_SE<br />
*<br />
Y 0.076 MM<br />
0.076 MM<br />
=STANDARD<br />
=STANDARD =STANDARD<br />
1.5:1_SPACING<br />
*<br />
0.15 MM<br />
?<br />
FSB_DSTB<br />
FSB_DSTB<br />
BGA_P1MM<br />
BGA_P3MM<br />
2:1_SPACING<br />
* 0.2 MM<br />
?<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
2.5:1_SPACING *<br />
0.25 MM<br />
?<br />
50_OHM_SE<br />
TOP,BOTTOM<br />
Y<br />
0.115 MM<br />
0.115 MM<br />
3:1_SPACING *<br />
0.3 MM<br />
?<br />
50_OHM_SE<br />
*<br />
Y<br />
0.076 MM 0.076 MM =STANDARD<br />
=STANDARD<br />
=STANDARD<br />
4:1_SPACING<br />
* 0.4 MM<br />
?<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
40_OHM_SE TOP,BOTTOM Y<br />
0.165 MM<br />
0.100 MM<br />
Y<br />
0.100 MM<br />
=STANDARD<br />
40_OHM_SE * =STANDARD<br />
0.126 MM =STANDARD<br />
SPACING_RULE_SET<br />
LAYER<br />
LINE-TO-LINE SPACING<br />
2X_DIELECTRIC TOP,BOTTOM<br />
0.140 MM<br />
?<br />
3X_DIELECTRIC TOP,BOTTOM<br />
0.210 MM<br />
?<br />
TABLE_SPACING_RULE_HEAD<br />
WEIGHT<br />
PHYSICAL_RULE_SET<br />
27P4_OHM_SE<br />
27P4_OHM_SE<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
TOP,BOTTOM<br />
*<br />
Y<br />
Y<br />
0.310 MM<br />
0.310 MM<br />
0.222 MM 0.222 MM<br />
=STANDARD<br />
=STANDARD<br />
=STANDARD<br />
4X_DIELECTRIC<br />
TOP,BOTTOM 0.280 MM<br />
?<br />
5X_DIELECTRIC TOP,BOTTOM<br />
0.350 MM<br />
?<br />
2X_DIELECTRIC<br />
3X_DIELECTRIC<br />
*<br />
0.126 MM ?<br />
* 0.189 MM<br />
?<br />
4X_DIELECTRIC<br />
* 0.252 MM<br />
?<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
5X_DIELECTRIC<br />
* 0.315 MM<br />
?<br />
C<br />
70_OHM_DIFF<br />
* N<br />
=STANDARD<br />
=STANDARD =STANDARD<br />
=STANDARD<br />
=STANDARD<br />
70_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y<br />
0.151 MM<br />
0.100 MM<br />
=STANDARD<br />
0.224 MM<br />
0.224 MM<br />
70_OHM_DIFF TOP,BOTTOM Y<br />
0.185 MM<br />
0.100 MM<br />
0.200 MM 0.200 MM<br />
C<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
90_OHM_DIFF *<br />
N<br />
=STANDARD =STANDARD<br />
=STANDARD<br />
=STANDARD<br />
=STANDARD<br />
90_OHM_DIFF<br />
ISL3,ISL4,ISL9,ISL10<br />
Y<br />
0.095 MM<br />
0.095 MM<br />
0.234 MM<br />
0.234 MM<br />
90_OHM_DIFF<br />
TOP,BOTTOM<br />
Y<br />
0.112 MM 0.112 MM 0.220 MM<br />
0.220 MM<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
100_OHM_DIFF<br />
* N<br />
=STANDARD<br />
=STANDARD<br />
=STANDARD<br />
=STANDARD<br />
=STANDARD<br />
100_OHM_DIFF<br />
ISL3,ISL4,ISL9,ISL10 Y 0.075 MM<br />
0.075 MM<br />
0.244 MM 0.244 MM<br />
100_OHM_DIFF<br />
TOP,BOTTOM<br />
Y 0.091 MM 0.091 MM<br />
0.230 MM<br />
0.230 MM<br />
B<br />
PHYSICAL_RULE_SET<br />
110_OHM_DIFF<br />
110_OHM_DIFF<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
N =STANDARD =STANDARD<br />
* =STANDARD<br />
ISL3,ISL4,ISL9,ISL10<br />
Y<br />
=STANDARD<br />
=STANDARD<br />
0.075 MM 0.075 MM 0.330 MM<br />
0.330 MM<br />
B<br />
110_OHM_DIFF<br />
TOP,BOTTOM<br />
Y<br />
0.077 MM 0.077 MM 0.330 MM<br />
0.330 MM<br />
PHYSICAL_RULE_SET<br />
1:1_DIFFPAIR<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP<br />
*<br />
Y =STANDARD<br />
=STANDARD =STANDARD 0.1 MM 0.1 MM<br />
A<br />
SYNC_MASTER=M97_<strong>MLB</strong><br />
<strong>K24</strong> RULE DEFINITIONS<br />
NOTICE OF PROPRIETARY PROPERTY<br />
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY<br />
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR<br />
AGREES TO THE FOLLOWING<br />
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART<br />
A<br />
APPLE INC.<br />
SIZE<br />
D<br />
SCALE<br />
DRAWING NUMBER<br />
NONE<br />
SHT<br />
OF<br />
REV.<br />
051-7898 4.7.0<br />
81<br />
81<br />
8 7 6 5 4 3 2 1
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