IBM 5150 PC Technical Reference (6025005, August, 1981) (PDF)

IBM 5150 PC Technical Reference (6025005, August, 1981) (PDF) IBM 5150 PC Technical Reference (6025005, August, 1981) (PDF)

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Programming Considerations Programming the 6845 CRT Controller The following table summarizes the 6845 Internal Data Registers and their functions and parameters. For the IBM Monochrome Display, r--.., the values in the table must be programmed into the 6845 to insure proper initialization of the device. Table 2. 6845 INITIALIZATION PARAMETERS REGISTER REGISTER PROGRAM 80x25 # FILE UNIT MONOCHROME RO HORIZONTAL TOTAL CHARACTERS 61H Rl HORIZONTAL OISPLAYED CHARACTERS 50H R2 HSYNC POSITION CHARACTERS 52H R3 HSYNC WIDTH CHARACTERS FH R4 VERTICAL TOTAL CHAR ROWS 19H R5 VTOTAL ADJUST SCAN LINE 6H R6 VERTICAL DISPLAYED CHAR ROW 19H R7 VSYNC POSITION CHAR ROW 19H RS INTERLACE MODE --- 02 R9 MAX SCAN LINE ADDRESS SCAN LINE DH R10 CURSOR START SCAN LINE BH Rll CURSOR END SCAN LINE CH R12 START ADDRESS (H) --- DOH R13 START ADDRESS (L) --- DOH R14 CURSOR (H) --- DOH R15 CURSOR (L) --- DOH R16 RESERVED --- --­ R17 RESERVED --- --­ Sequence of Events The first command issued to this attachment must be to output to PORT 3B8, hex 01, to set high resolution mode. Ifthe high resolution mode is not set, an infinite CPU wait-state will occur! Memory Requirements The attachment has 4K bytes of memory which is used for the display buffer. The memory supports one screen of 25 rows of 80 characters, plus a character attribute for each display character. No parity is provided on the memory. No system Read/Write memory is required for the monochrome adapter portion. The display buffer starts at address 'BOOOO'. 2-41

DMA Channels The display buffer will support a DMA operation, however CPU wait-states will be inserted during DMA. Interrupt Levels Interrupt Level 7 is used on the parallel interface. Interrupts can be enabled or disabled via the Printer Control Port. The interrupt is a high level active signal. I/O Address and Bit Map The table below breaks down the functions ofthe I/O Address decode for the card. The I/O address decode is from '3BO' through '3BF'. The bit assignment for each I/O address follows: I/O Address Function 3BO Not Used 3Bl Not Used 3B2 Not Used 3B3 Not Used 3B4 6845 Index Register 3B5 6845 Data Register -. 3B6 Not Used r , 3B7 Not Used 3B8 CRT Control Port 1 3B9 Reserved 3BA CRT Status Port 3BB Reserved 3BC Parallel Data Port 3BD Printer Status Port 3BE Printer Control Port 3BF Not Used The 6845 Index and Data Registers are used to program the CRT controller to interface to the high resolution Monochrome Display. • CRT Output Port 1 (I/O Address '3B8') Bit :#= Function +high resolution mode 2-42 o 1 Not used 2 Not used 3 + video enable 4 Not used 5 + enable blink 6,7 Not used

Programming Considerations<br />

Programming the 6845 CRT Controller<br />

The following table summarizes the 6845 Internal Data Registers and<br />

their functions and parameters. For the <strong>IBM</strong> Monochrome Display,<br />

r--.., the values in the table must be programmed into the 6845 to insure<br />

proper initialization of the device.<br />

Table 2. 6845 INITIALIZATION PARAMETERS<br />

REGISTER REGISTER PROGRAM 80x25<br />

# FILE UNIT MONOCHROME<br />

RO HORIZONTAL TOTAL CHARACTERS 61H<br />

Rl HORIZONTAL OISPLAYED CHARACTERS 50H<br />

R2 HSYNC POSITION CHARACTERS 52H<br />

R3 HSYNC WIDTH CHARACTERS FH<br />

R4 VERTICAL TOTAL CHAR ROWS 19H<br />

R5 VTOTAL ADJUST SCAN LINE 6H<br />

R6 VERTICAL DISPLAYED CHAR ROW 19H<br />

R7 VSYNC POSITION CHAR ROW 19H<br />

RS INTERLACE MODE --- 02<br />

R9 MAX SCAN LINE ADDRESS SCAN LINE DH<br />

R10 CURSOR START SCAN LINE BH<br />

Rll CURSOR END SCAN LINE CH<br />

R12 START ADDRESS (H) --- DOH<br />

R13 START ADDRESS (L) --- DOH<br />

R14 CURSOR (H) --- DOH<br />

R15 CURSOR (L) --- DOH<br />

R16 RESERVED --- --­<br />

R17 RESERVED --- --­<br />

Sequence of Events<br />

The first command issued to this attachment must be to output to<br />

PORT 3B8, hex 01, to set high resolution mode. Ifthe high resolution<br />

mode is not set, an infinite CPU wait-state will occur!<br />

Memory Requirements<br />

The attachment has 4K bytes of memory which is used for the display<br />

buffer. The memory supports one screen of 25 rows of 80 characters,<br />

plus a character attribute for each display character. No parity is<br />

provided on the memory. No system Read/Write memory is required<br />

for the monochrome adapter portion. The display buffer starts at<br />

address 'BOOOO'.<br />

2-41

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