Interlayer Cooling of 3D Stacked ICs - Microelectronic Systems ...

Master Project 

Microelectronic Systems Laboratory 

Interlayer cooling of 3D stacked IC 

3D Integration Strategies – Heat Transfer Stack 

January 2009 

Student: Supervisors: Professor: 

Alexandre Pascarella Fengda Sun, Yuksel Temiz Yusuf Leblebici 

SMT LSM LSM


Abstract 

In a 3D chip, power density must be taken in account as a major parameter. Thermal 

management inside of a 3D stacked integrated circuit (often reported as 3D-SIC) cannot be 

solved with actual external cooling techniques. To overcome this limitation, current 

researches lead to the use of a single phase or two-phase flow interlayer cooling directly 

integrated through the chip. The idea is to use thermal properties of liquids or two-phase 

flows to carry out the heat from the 3D stack with the use of a structured interface between 

each tier and in a microscale level. 

This work is mainly dedicated to the design and fabrication of a test setup to characterize heat 

transfer capabilities of integrated interlayer cooling systems and to validate thermal models of 

microstructured heat exchangers. 

Alexandre Pascarella P a g e | 2


Table of contents: 

1 INTRODUCTION ....................................................................................................................................... 7 

1.1 3D INTEGRATION TECHNOLOGY AND STACKED LAYERS APPROACH........................................................... 8 

1.2 PROJECT DESCRIPTION ............................................................................................................................... 9 

2 CLEAN ROOM EQUIPMENTS .............................................................................................................. 10 

2.1 LASER LITHOGRAPHY SYSTEM - HEIDELBERG DWL200 .......................................................................... 10 

2.2 MASK AND THICK POSITIVE RESIST DEVELOPER - DV10 .......................................................................... 10 

2.3 WET BENCHES ......................................................................................................................................... 11 

2.4 AUTOMATIC RESIST PROCESSING CLUSTER – EVG 150 .......................................................................... 12 

2.5 DOUBLE SIDE MASK ALIGNER – MA6 ...................................................................................................... 12 

2.6 E-GUN AND THERMAL EVAPORATOR – LEYBOLD - OPTICS LAB 600 H ................................................... 12 

2.7 HIGH VACUUM SPUTTER CLUSTER SYSTEM – PFEIFFER SPIDER 600 ....................................................... 13 

2.8 PLASMA ETCHER - AMS 200 DSE (DIELECTRIC AND SILICON ETCHER) ................................................. 14 

2.9 MANUAL PROBER STATION – KARL SÜSS PM8 ....................................................................................... 16 

3 FIRST EXPERIMENTS IN 3D DESIGNS ............................................................................................. 17 

3.1 HEATING 3D STACKED CHIP .................................................................................................................... 17 

3.1.1 Microheaters ................................................................................................................................. 18 

3.1.2 Resistance Temperature Detectors (RTDs) ................................................................................... 20 

3.1.3 Layout design ................................................................................................................................ 21 

3.1.4 Materials, methods and processes ................................................................................................. 27 

3.1.5 Results ........................................................................................................................................... 31 

3.2 WAFER THINNING .................................................................................................................................... 35 

3.2.1 Grinding and polishing machine ................................................................................................... 35 

3.2.2 Thinning experiments .................................................................................................................... 36 

3.2.3 Results ........................................................................................................................................... 36 

4 HEAT TRANSFER SETUP ..................................................................................................................... 40 

4.1 HEAT TRANSFER STACK ........................................................................................................................... 41 

4.1.1 Heat transfer ................................................................................................................................. 42 

4.1.2 Layout design ................................................................................................................................ 43 

4.1.3 Materials, methods and processes ................................................................................................. 51 

4.2 PCB ......................................................................................................................................................... 55 

4.3 HOUSING COMPONENTS ........................................................................................................................... 58 

4.4 RESULTS .................................................................................................................................................. 59 

5 CONCLUSION .......................................................................................................................................... 66 

6 ACKNOWLEDGMENT ........................................................................................................................... 67 

7 BIBLIOGRAPHY ...................................................................................................................................... 68 

8 APPENDICES............................................................................................................................................ 70 

8.1 APPENDIX A: TEMPLATE FOR SCREEN PRINTING ...................................................................................... 70 

8.2 APPENDIX B: EPOXY ADHESIVE ............................................................................................................... 71 

8.3 APPENDIX C: HOUSING COMPONENTS DESIGN SKETCHES ........................................................................ 72 

8.4 APPENDIX D: FLUID CONNECTORS ........................................................................................................... 74 



Table of figures: 

Figure 1.1 : Chip-to-chip interconnect length reduction with microchannel cooled 3D-ICs [17] 

Sekar et al. .................................................................................................................................. 7 

Figure 1.2 : Model for one-dimensional thermal analysis of vertically integrated circuits. [9] 

Kleiner et al. ............................................................................................................................... 8 

Figure 1.3 : A microchannel cooled 3D integrated circuit [17] Sekar et al. .............................. 9 

Figure 2.1 : DWL200 Laser lithography system ...................................................................... 10 

Figure 2.2 : Mask writing system ............................................................................................. 10 

Figure 2.3 : DV10 Mask and thick resist developer ................................................................. 10 

Figure 2.4 : Wet benches .......................................................................................................... 11 

Figure 2.5 : EVG150 Automatic resist processing cluster ....................................................... 12 

Figure 2.6 : MA6 Double side mask aligner ............................................................................ 12 

Figure 2.7 : LAB600H Evaporator ........................................................................................... 13 

Figure 2.8 : Room inside .......................................................................................................... 13 

Figure 2.9 : SPIDER 600 sputtering system ............................................................................ 13 

Figure 2.10 : AMS 200 Plasma etcher ..................................................................................... 14 

Figure 2.11 : AMS 200 User interface ..................................................................................... 14 

Figure 2.12 : Reaction chamber ............................................................................................... 15 

Figure 2.13 : Manual prober station ......................................................................................... 16 

Figure 3.1: Five tier 3D heating stack ...................................................................................... 17 

Figure 3.2 : Microheater surrounded by a resistance temperature detector (RTD) with 

connecting wires ....................................................................................................................... 18 

Figure 3.3 : 3 wires microheater ............................................................................................... 19 

Figure 3.4 : 4-wire measurement method ................................................................................. 20 

Figure 3.5 : Wafer layout ......................................................................................................... 21 

Figure 3.6 : Devices configurations ......................................................................................... 22 

Figure 3.7 : Microheaters random configuration with surrounding RTDs............................... 23 

Figure 3.8 : Layer_1 ................................................................................................................. 23 

Figure 3.9 : Layer_2 ................................................................................................................. 23 

Figure 3.10 : Microheaters aligned configuration with surrounding RTDs ............................. 24 

Figure 3.11 : RTDs dots for temperature map ......................................................................... 25 

Figure 3.12 : 2D and 3D temperature map ............................................................................... 25 

Figure 3.13 : Circular RTD ...................................................................................................... 26 

Figure 3.14 : Microheaters random configuration with circular RTDs .................................... 26 

Figure 3.15 : Process flow used for a first trial with Al metallization ..................................... 28 

Figure 3.16 : Pads opened in a silox bath ................................................................................. 29 

Figure 3.17 : Al surface after pad opening in a silox bath ....................................................... 29 

Figure 3.18 : Final wafer after processing steps ....................................................................... 29 

Figure 3.19 : Screen printer EKRA .......................................................................................... 30 

Figure 3.20 : Screen printing : principle .................................................................................. 30 

Figure 3.21 : 3D stacked chip, configuration n°1 .................................................................... 31 



Figure 3.22 : 3D stacked chip, configuration n°3 .................................................................... 31 

Figure 3.23 : Test setup with prober station, power supplies and multimeter ......................... 32 

Figure 3.24 : Probes on a stacked chip during measurement ................................................... 32 

Figure 3.25 : RTD response to the heat provided by its linked microheater ............................ 33 

Figure 3.26 : Thinning equipments. (a) rotating plate with moving arm, (b) mechanical holder, 

(c) complete system .................................................................................................................. 35 

Figure 3.27 : Assembly profile and holder ............................................................................... 36 

Figure 3.28 : 100µm thick thinned Si component with TSVs .................................................. 36 

Figure 3.29 : Holes dry etched in silicon and opened on the other side by thinning (depth: 

100µm, diameter 100µm) ........................................................................................................ 37 

Figure 3.30 : Holes dry etched in silicon and opened on the other side by thinning (depth: 

100µm, diameter 50µm) .......................................................................................................... 38 

Figure 3.31 : 50µm diameter hole opened by thinning ............................................................ 39 

Figure 4.1 : Heat transfer device with integrated fluid path (on the right: cross section in a 

fluid opening) ........................................................................................................................... 40 

Figure 4.2 : Heat transfer single layer. (a) Single die with microheater and fluid openings, (b) 

structured backside ................................................................................................................... 40 

Figure 4.3 : Profile of the 3D stacked heat transfer setup ........................................................ 41 

Figure 4.4 : In-line flow and corner flow configurations (orange: microheaters; blue: fluid 

paths) ........................................................................................................................................ 41 

Figure 4.5 : Schematic of the thermal circuit with a microchannel [16] Koo et al. ................. 42 

Figure 4.6 : 80Ω multi-wires rectangular microheater with RTD in the middle part for in-line 

flow configuration .................................................................................................................... 43 

Figure 4.7 : 80Ω multi-wires square microheater with RTD in the middle part for corner flow 

configuration ............................................................................................................................ 43 

Figure 4.8 : Layer 1 (top layer) for in-line flow heat transfer stack ......................................... 44 

Figure 4.9 : Layer 1 (top layer) for corner flow heat transfer stack ......................................... 45 

Figure 4.10 : Layer 2 with microheaters for in-line flow heat transfer stack ........................... 46 

Figure 4.11 : Layer 2 with microheaters for corner flow heat transfer stack ........................... 47 

Figure 4.12 : Pad configuration for a microheater and its sensor............................................. 48 

Figure 4.13 : Wafer layout for in-line flow heat transfer stack ................................................ 49 

Figure 4.14 : Wafer layout for corner flow heat transfer stack ................................................ 50 

Figure 4.15 : Front side and backside alignment marks ........................................................... 50 

Figure 4.16 : Process flow for microchannels, pin fin and fluid openings dry etching ........... 52 

Figure 4.17 : Recipes used for SiO 2 and Si dry etching with AMS 200 .................................. 53 

Figure 4.18 : Schematic process for polyimide bonding .......................................................... 54 

Figure 4.19 : Chip assembled to a small PCB and mounted on a larger one ........................... 55 

Figure 4.20 : Chip and connectors footprints on small PCB .................................................... 55 

Figure 4.21 : Connecting wires from bonding pads to connectors on small PCB. Red lines: 

PCB front side. Blue lines: PCB backside. .............................................................................. 55 

Figure 4.22 : Pads configuration. On the left : pads from stacked chip. On the right : pads 

from PCB .................................................................................................................................. 56 

Figure 4.23 : Wire bonding configuration for a microheater and its sensor ............................ 57 



Figure 4.24 : Polymer components. (a) housing for in-line flow chip, (b) housing for corner 

flow chip, (c) housing for in-line flow chip with push-in fluid connections, (d) housing for 

corner flow chip with push-in fluid connections ...................................................................... 58 

Figure 4.25 : Aluminum evaporation on platinum thin film (400nm Al on 200nm Pt) ........... 59 

Figure 4.26 : Non-uniformity and delamination after oxide sputtering ................................... 59 

Figure 4.27 : Alternative layout for Al layer ............................................................................ 60 

Figure 4.28 : Al stripes on leads ............................................................................................... 60 

Figure 4.29 : Al stripes evaporation on platinum thin film (400nm Al on 200nm Pt) ............. 60 

Figure 4.30 : Al stripes on platinum thin film and 1mm 2 square Al single layer, both after 

oxide sputtering ........................................................................................................................ 61 

Figure 4.31 : Ti/Pt/Al/SiO2 and Al/SiO2 surfaces comparison ............................................... 61 

Figure 4.32 : 200µm deep microchannels dry etched on wafer backside and linked to the fluid 

opening ..................................................................................................................................... 62 

Figure 4.33 : 200µm high pillars dry etched on wafer backside and linked to the fluid opening 

.................................................................................................................................................. 62 

Figure 4.34 : Microchannels and fluid opening ....................................................................... 63 

Figure 4.35 : Pin fin and fluid opening .................................................................................... 63 

Figure 4.36 : Pillars network .................................................................................................... 64 

Figure 4.37 : Pillars with higher magnification ........................................................................ 64 

Figure 4.38 : Right-angled microchannels ............................................................................... 65 



1 Introduction 

Meet the requirements ever more demanding needed for high performance chips while scaling 

down the dimensions brings new technological challenges. Indeed, miniaturization and 

density increase start to reach some limits with planar technology. Top-down microfabrication 

technologies which are widely used nowadays are facing more and more to physical limits 

due to the scaling of the components as well as the resolution limits of photolithography 

processes; while bottom-up micro or nanofabrication technologies, whose some are probably 

promising, have not yet reached a sufficient stage of development. Therefore, exploiting the 

third dimension available by stacking some vertically interconnected layers seems to be a 

solution in the middle able to push away some limitations and 3D integration technologies 

that are arising might become fundamental for next chips generations. 

This type of technology should enable to overlay the components and by the way to increase 

the density per “surface” unit, avoiding precisely to stay in one horizontal surface. But 

advantages are multiple, and one of the main is the opportunity to shorten the electrical 

connections, resulting in faster operations with logic and memory stacked one upon the other 

for example. Heterogeneous integration brings completely new approaches for system 

designs. 

Figure 1.1 : Chip-to-chip interconnect length reduction with 

microchannel cooled 3D-ICs [17] Sekar et al. 

To go further in the development of devices with a very high integration level, heat 

dissipation must be taken in account as an essential parameter among other critical 

considerations. Potential powerful new architectures could be realized, but to make the most 

of 3D integration, a suitable and reliable cooling solution must be implemented to remove the 

dissipated heat from the chip. Even more than in a common chip, high power densities will 

stand in a 3D-IC stack and the dissipated heat must be pulled out as well from the center part 

of the chip as from the surfaces. Each die will dissipate heat that added on the same surface 



cannot still be removed by standard air cooling systems. T.Brunschwiler et al. demonstrated 

the limitations of back-side heat removal for 3D stacked layers and the necessity to use an 

advanced cooling system [15]. Then, to enhance heat transfer capabilities of a cooling system, 

it should be in this case directly integrated in the device instead of acting as an external 

interface. A conceivable way to cool down a multi-level chip or processor may be with the 

use of an interlayer fluid flow between the stack levels. Single-phase liquid or two-phase flow 

convective cooling directly through the chip might provide an efficient heat transfer. 

This project is mainly dedicated to the design and fabrication of a test setup for thermal 

modeling of 3D-ICs. 

1.1 3D integration technology and stacked layers approach 

3D architectures can lead to powerful applications and have a great potential to increase 

electrical performances of miniaturized systems. To go further in high integration level and 

components miniaturization, stacked dies with vertical interconnections can be an issue to 

many technological limitations imposed by planar designs. 

Key technologies that must be developed and implemented to realize 3D chips are mainly the 

vertical connections through silicon dies and the thermal management of the 3D stack. 

Another concern is the fact that this kind of technology compels to work with very thin layers 

required for vertical interconnections. 

With miniaturization, power density increases and heat removal becomes less efficient. The 

heat has smaller thermally conducting paths to be extracted from dense power dissipating 

zones resulting in a higher thermal resistance. This concern becomes even more relevant 

when thinking about 3D integration with several levels. And each die is composed of several 

material layers with different thermal conductivities. Silicon is much more conductive 

compared to SiO 2 . Then in an intermediate level of a CMOS 3D chip, a thin silicon layer will 

be enclosed between two oxide layers with a lower thermal conductivity and acting as a 

barrier for heat transfer. 

Figure 1.2 : Model for one-dimensional thermal analysis of vertically 

integrated circuits. [9] Kleiner et al. 



To solve this problem, current researches [15] [17] lead to the use of a single phase or twophase 

flow interlayer cooling directly integrated through the chip. The idea is to create a 

cooling interface between each single die to carry out the heat from the center part of the chip. 

This cooling interface must be compatible with electronic components and with a high density 

vertical interconnection network like TSVs that will be needed in a functional chip. 

Figure 1.3 : A microchannel cooled 3D integrated 

circuit [17] Sekar et al. 

Another advantage of these kinds of integrated cooling systems is that they let the opportunity 

to use a larger area on the top surface of the chip for an optical or radio frequency access 

instead of using this surface for heat removal covered with a heat sink. 

1.2 Project description 

This project has been done in two phases. First, a design has been done to build a first 3D 

stack with microheaters and thermal sensors on each die. Microheaters were placed to emulate 

the power dissipated by a CMOS chip. The goal was to have heating elements on each level to 

characterize the heat distribution and spreading inside of the stack on each layer. These first 

experiments were also the opportunity to learn how to use equipments for microfabrication 

steps and test the process flow on a wafer level. Stacking has then been done on a die level. 

Second part of the project was to build a heat transfer setup with an integrated fluid cooling 

system. The starting point to do this is the work of T. Brunschwiler et al. presented in the 

paper “Forced convective interlayer cooling in vertically integrated packages” [15]. This 

paper shows comparisons and heat transfer capabilities of microstructures suitable for 

interlayer cooling and compatible with vertical interconnections. 



2 Clean Room Equipments 

Many steps of the project relating to microfabrication and requiring clean room equipments 

have been done at the Center of MicroNanoTechnology (CMI) from EPFL. This section 

presents firstly an overview of the main tools used throughout the project in the clean room. 

For these machines, trainings have been offered by the CMI’s staff to allow using them 

independently and in a safe and right manner. 

2.1 Laser lithography system - Heidelberg DWL200 

Figure 2.1 : DWL200 Laser lithography system 

Figure 2.2 : Mask writing system 

The DWL200 equipment allows patterning optically a surface by scanning it with a laser. This 

laser lithography system can be used to produce chromium masks for photolithographic 

processes. The machine is composed of a Kr blue laser light source (Gaussian beam – 413nm 

wavelength) providing the power for the exposure and allow to write structures down to 

800nm. All tables and the XY positioning table are made of granite to guarantee the thermal 

stability. The mask is loaded on the table by an automated arm. [23] 

2.2 Mask and thick positive resist developer - DV10 

DV10 equipment allows the development of the 

masks exposed with the laser lithography system. 

The development liquid (developer) is put on the 

surface and the mask rotate with an oscillating 

motion during reaction time. [23] 

Figure 2.3 : DV10 Mask and thick resist developer 



2.3 Wet Benches 

Chromium etching, resist stripping, lift-off and oxide wet etching have been done with wet 

benches. 

Wet bench for oxide and metal etch: this bench has among others a bath dedicated to wet 

etching of Cr and Cr oxide with photoresist mask. The bath is an acid/oxidizer solution of 

perchloric acid, cerium ammonium nitrate and water (Formula: HClO 4 + Ce (NH 4 ) 2 (NO 3 ) 6 + 

H 2 O). Perchloric acid is a strong acid and cerium ammonium nitrate is an oxidizing agent. Cr- 

Etch bath is at 20°C. 

Wet bench for resist development and resist stripping: this 

bench has a bath for resist development that is a basic 

solution comprising tetramethylammonium hydroxide 

(TMAH, (CH 3 ) 4 NOH, strong base). This bath is at 20°C. 

The bench has two others bathes (“old” bath and “new” 

bath) dedicated to the photoresist stripping. They contain a 

solution of N-Methylpyrrolidone (NMP) that is a good 

solvent to dissolve polymers. These bathes are at 70°C. 

Wet bench for solvent: this bench has two baths dedicated 

to lift-off. These baths are NMP solution (remover 1165) at 

room temperature. One is a static bath while the other has 

activation and an ultrasonic system. 

Wet bench for wet etching: this bench is dedicated to oxide 

and metal etch, it has among others a Silox (Pad etch) bath 

selective to Al that has been used for pad opening. 

Figure 2.4 : Wet benches 

On each wet bench, specific baskets are dedicated to rinse the samples. First rinse (Quik 

Dump and Rince - QDR) is cycles of a DI water shower and N 2 agitation. Final rinse (Ultra 

Clean - UC) is a bath of DI water with resistivity measurement of the bath. 

On some benches these baskets are FFR (Fast Fill Rinse) and TT (Trickle Tank). 

The drying of the samples can be done with a N 2 gun for masks and with spinners for wafers 

or with spin-rinse-dryer (SRD). [23] 



2.4 Automatic Resist Processing Cluster – EVG 150 

This equipment is an automatic coater and 

developer system. 

The cluster comprises cassette carriers for loading 

unloading the wafers, an automated arm, 

hotplates, a coater module (spinner chuck with 

two resist dispense arms: resist lines or spray 

coating), a developer module and a coolplate. [23] 

2.5 Double side mask aligner – MA6 

Figure 2.5 : EVG150 Automatic resist processing 

cluster 

This tool allows the alignment between a mask 

and the top or back side of a wafer and the UV 

exposure of the photoresist to transfer the 

desired pattern. 

Figure 2.6 : MA6 Double side mask aligner 

Microscopes with cameras allow the alignment 

on a screen splitted into two parts for each side 

(left and right) of the wafer. Main parameters 

that can be set are the exposure time, the power 

of the UV source and the proximity (gap 

between mask and wafer) or contact mode. [23] 

2.6 E-gun and thermal evaporator – Leybold - Optics LAB 600 H 

Thin metallic or dielectric layers can be deposited on wafers with this equipment. Materials 

are evaporated by resistive thermal evaporation or by e-beam. High vacuum inside of the 

chamber (~1.10 -7 mbar) assures a very low contamination during the deposition. 

With the e-beam, metal is bombarded and evaporated by a high energy electrons beam. The 

source of electrons is created by heating a tungsten wire traveled by a current. A high voltage 

difference accelerates the electrons and these ones are deflected and guided by a magnetic 

field. Metal is excited by the beam focused on its surface, kinetic energy of the electrons is 

converted into heat at the impact point and allows the evaporation. 



Figure 2.7 : LAB600H Evaporator 

Figure 2.8 : Room inside 

The distance between the evaporated material source and substrates is about 1m in high 

configuration, which makes this equipment especially suitable for “lift-off” processes (but this 

distance can be shortened). Furthermore, substrates are rotated to ensure a good uniformity 

during the deposition. 

The preliminary step before deposition is to ensure a sufficient vacuum within the chamber. 

This pumping is part of the process that requires most of the time (several tens of minutes or 

hours for a high vacuum). The deposition itself takes a few minutes. [23] 

2.7 High vacuum sputter cluster system – Pfeiffer SPIDER 600 

SPIDER600 equipment is a multi-chamber sputtering 

system. It allows the deposition of metallic layers 

and dielectrics with good thickness uniformity. For 

the sputtering, a plasma is created (often with argon). 

First, vacuum is done in the chamber, then the gas is 

injected within it. For the deposition of metallic 

layers a DC potential is applied between two 

electrodes. Ions are accelerated by the electrical field 

and metallic atoms are then extracted from the target. 

Figure 2.9 : SPIDER 600 sputtering system 



For the deposition of dielectric layers, radio frequency sputtering is used to have an 

alternation of the electrodes potentials that allow the deposition of an insulator. 

Physical sputtering and reactive sputtering (with N 2 or O 2 ) can be done depending on the 

application. [23] 

2.8 Plasma Etcher - AMS 200 DSE (Dielectric and Silicon Etcher) 

Figure 2.10 : AMS 200 Plasma etcher 

Figure 2.11 : AMS 200 User interface 

AMS 200 DSE is a plasma etching machine from the family of dry etching process. The 

technology used is a high density plasma of ICP type (Inductively Coupled Plasma) working 

in a temperature controlled chamber. 

The wafer transfer from the airlock to the plasma chamber is done automatically by an 

automated arm. This way enables to keep a secondary vacuum inside the reaction chamber 

during loading/unloading operations what saves time during process. 

Many kinds of specific process can be used with this plasma etcher. Parameters that can be 

adjusted are the followings: substrate polarization (Radio Frequency or pulsed Low 

Frequency), temperature (control of process stability and chamber contamination), process 

type, etc. All the parameters are edited through a computer interface. 

The center part of the machine is the reaction chamber mainly made up of an ICP source, a 

diffusion chamber and a substrate holder. 



Figure 2.12 : Reaction chamber 

ICP source is composed of an antenna connected to a frequency generator placed around an 

alumina (dielectric, Al 2 O 3 ) cylinder. The power of the frequency generator (energy of the 

oscillating current, 13.56 MHz for RF mode) in the antenna induces an electromagnetic field 

inside of the alumina tube and thus is coupled to the plasma. The plasma is formed by 

collisions of energetic electrons excited by the oscillations of the electromagnetic field with 

neutral atoms creating ions. Only some mobile electrons are excited because the ions are too 

heavy to follow the variations of the magnetic field. Gases are injected in the alumina 

chamber and the pressure is controlled. A coil around the source generates a magnetic field to 

imprison the plasma and avoid losses on the walls. 

The diffusion chamber allows to enhance the uniformity of the plasma. Permanents magnets 

around the chamber generate a constant magnetic field to keep the plasma inside of it. The 

temperature inside the diffusion chamber is controlled (heating) for the process stability and 

to avoid chamber contamination. 

The substrate holder where the wafer is placed is controlled in temperature (-20°C to ambient 

temp.) which is an important parameter depending on the process used. 

When the etching is not operating vacuum (about 10 -7 mb) is hold inside of the chamber by 

pumps. During the process these pumps allows to control the pressure and thus the gas flow 

knowing that a high gas flow can in some cases increase the etching speed. 



Gases in the reaction chamber can be the followings: (with their flow measurement in 

"standard cubic centimeters per minute") 

• SF 6 [0-1000 sccm] 

• C 4 F 8 [0-400 sccm] 

• C 4 F 8 [0-100 sccm] 

• CH 4 [0-100 sccm] 

• O 2 [0-100 sccm] 

• Ar [0-200 sccm] 

• He [0-200 sccm] 

During the etching a laser beam can be used to measure the etching speed of transparent 

layers (like SiO 2 or Si 3 N 4 ) and therefore the depth etched and to detect the end of the etching 

when another layer is reached (other material). Technique used is the interferometry. The 

laser directed on the surface (905nm) is reflected and its measured intensity is modulated 

depending on the layer thickness that decreases during the etching process. Thus the 

interferences evolve during the time creating an oscillating signal. When the transparent layer 

is totally etched the beam is then reflected without interferences and the intensity becomes 

constant showing the end of the process. [23] 

2.9 Manual Prober Station – Karl Süss PM8 

Electrical measurements have been done with a prober station. Test setup comprises 

micromanipulators to position thin tungsten tips on the sample surface with the help of a 

microscope. Tips are held at the micromanipulators arms extremity and provide the electrical 

contact with the sample. Micromanipulators allow moving the tips in the three axes. The table 

that holds the sample with a vacuum and the microscope can also be moved in every 

direction. [23] 

Figure 2.13 : Manual prober station 



3 First experiments in 3D designs 

3.1 Heating 3D stacked chip 

The departure point of this project was to create a multi-level chip, build by stacking silicon 

layers one upon the other. This first stack should represent or extrapolate the thermal 

properties of a 3D chip, without considering here its functional properties. 

Power dissipated in a chip is not uniform on its surface. Some elements of a microprocessor 

unit dissipate much more power than others. MPU hot spots per example can dissipate 

between 200 to 300W/cm 2 while memory only dissipates about 10W/cm 2 . [15] 

On each layer microheaters are placed with different configurations to simulate the heat 

dissipated by the integrated components of a circuit design that stands in a useful chip. Some 

thermal sensors are also placed in specific places as detector devices to monitor the 

temperature inside of the stack and check the heat dissipated and the heat interactions between 

neighboring microheaters. In a further setup design, these sensors should allow to observe the 

heat transfer capabilities of integrated cooling systems. 

Figure 3.1: Five tier 3D heating stack 

The chip consists of a 1cm 2 stack made of 5 layers. Depending on the level, under layers are 

larger on one side, making steps, to allow to connect the heaters and sensors by wire bonding 

on a PCB. All pads are then on one side of the chip. This configuration enables to align the 

layers easily for a manual stacking with a corner angle on the opposite side. 



3.1.1 Microheaters 

Microheaters are placed on the surface of each layer to provide heat to the device. The shape 

of these heaters is a serpentine wire made with thin-film technologies. Platinum has been 

chosen as a suitable material for its capability to operate at very high temperature, for its longterm 

stability and because it’s also the appropriate material for the temperature sensors which 

enables to manufacture these two components at the same time in a single step during the 

process. 

Figure 3.2 : Microheater surrounded by a resistance temperature detector (RTD) with connecting wires 

Microheaters have been designed to correspond to hot spots at the surface of the chip which 

represent a value of 300 W/cm 2 . Then each one of the 1mm 2 heater should dissipate 3W. 

Power dissipation: 

Resistances are designed using: 

= 

= 

With a platinum “bulk” resistivity of: = 10.6 ∙ 10 Ω ∙ . 

In this configuration, RTDs are placed around the heaters. These RTDs are designed for a 

value of 100 Ohm (Pt100) and are driven with a current of 1mA. External wires are placed at 

the end points of the RTD to measure the voltage while the two others supply the 1mA 

current. 



Figure 3.3 : 3 wires microheater 

For each kind of chip on the layout a modification has been made by separating the heaters in 

many wires to avoid hot spots in the corners of the serpentine and enhance the temperature 

uniformity. With a single wire, electrons follow the shorter path due to the potential gradient 

in the wire and current density is larger near inside corners of the serpentine increasing power 

dissipation at these small areas. By separating the single wire in several others, current will be 

forced to follow parallel different paths and dissipate power more regularly on the surface. 

We can notice that the length, width (and of course thickness) of each separated wire is the 

same, so total current is divided by the number of wires for the same potential. Total 

resistance can be considered like a single wire by taking in account the spacing (subtracting) 

in the total metal width or like several higher resistances in parallel. On the layout, sizes and 

configurations are the same as those in single wire microheaters. 

Each group of layers on the wafer denominated with “n°a” on Figure 3.6 have this kind of 

heaters. 



3.1.2 Resistance Temperature Detectors (RTDs) 

Thermal sensors that have been used on each layer are Resistance Temperature Detectors 

(RTDs). 

The resistivity temperature dependence of platinum is described by the following equation: 

(only for positive temperatures, for negative temperatures an additional term must be 

included) 

= (1 + + ) 

With R T the resistance at temperature T, R 0 the nominal resistance at 0 °C, α = 3.9083e -3 °C -1 

and β = -5.775e -7 °C -2 . 

Constant β is very low which means that the resistivity temperature dependence is nearly a 

linear characteristic (resistivity increase with temperature) making this material very suitable 

for sensing. Furthermore, it has a fast response time, a low drift, and can operate in a wide 

range of temperature. 

Normalized 100Ω platinum (Pt100) have been designed. In Pt100 standard, 100 Ω represents 

the nominal resistance at 0°C. The resistance at 20°C is then 107.8 Ω. 

A 4-wire measurement method has been used to sense the temperature only in the active part 

and to avoid the influence of the connecting wires. This method consists in measuring the 

voltage with two other wires at both extremities of the resistive sensor because for a voltage 

measurement no current flows in these wires. 

V 

I 

R sensor 

Figure 3.4 : 4-wire measurement method 

Pt100 can be driven by a current of 1mA. 



3.1.3 Layout design 

Design has been done with the software “CleWin” that is a computer-aided design tool. 

All the dimensioning has been done for a 500nm layer of platinum (which is not the metal that 

has been deposited in the end during the microfabrication process). 

Wafer layout: 

Figure 3.5 : Wafer layout 

The wafer layout comprise three different kinds of chips with various configurations for the 

heaters and sensors, each one has 5 layers. For each kind of chip, a duplicate with the same 

design but with the multi-wires heaters as shown in Figure 3.3 is set on the layout. Finally, six 

chips can be done by stacking these layers; their configurations are shown in Figure 3.6. 

Chips must be properly aligned on the wafer to allow the dicing. The cuts are straights from 

one side to another. The chips must be arranged in an orthogonal network and dedicated 

alignment marks (crosses) must be placed regularly on the layout at the desired cutting 

location. 



3 

1 

1a 

2 

3a 

2a 

Figure 3.6 : Devices configurations 

Configuration n°1: Heaters are placed randomly on the layer surface, an alternation of two 

random configurations allows to misalign also vertically the heaters from one layer to another. 

Sensors are surrounding the heaters. 1a has the same configuration but with the multi-wires 

heaters as shown in Figure 3.3. 

Configuration n°2: Heaters are aligned in the plane but also vertically out of the plane when 

stacking the layers. Sensors are surrounding the heaters. 2a has the same configuration but 

with the multi-wires heaters as shown in Figure 3.3. 

Configuration n°3: Heaters are placed randomly, a different random configuration has been 

done for each layer, so the heaters are placed randomly in the whole chip’s volume. The 

sensors are small dots on the surface to have a temperature map. 3a has the same 

configuration but with the multi-wires heaters as shown in Figure 3.3. 

These configurations are shown more in details in the next pages. 



Configuration n°1: (random_surrounding_RTD) 

Figure 3.7 : Microheaters random configuration with surrounding RTDs 

Each layer of chip n°1 comprises 10 heaters of 1mm square (to be quite similar to small 

processing elements) that are filling 10% of the total surface (10x10mm 2 ). The first layer (top 

layer) of the chip is shown here. 

The heaters have been placed randomly on layer_1 and randomly on layer_2 at different 

places, then on the 3 rd layer, same layout than on layer_1 is again used and so on… in 

alternation until layer 5. 

Figure 3.8 : Layer_1 

Figure 3.9 : Layer_2 



Configuration n°2: (aligned_surrounding_RTD) 

Figure 3.10 : Microheaters aligned configuration with surrounding RTDs 

Each layer of chip n°2 comprises also 10 heaters of 1mm square that are filling 10% of the 

total surface (10x10mm 2 ). The first layer (top layer) of the chip is shown here. 

Here the heaters are aligned in 3 vertical lines. The 5 layers of the stack have the same 

configuration so the alignment of the heaters appears also out of the plane. 

In this configuration, RTDs are still placed around the heaters. 



Configuration n°3: (random_circular_RTD) 

Figure 3.11 : RTDs dots for temperature map 

For the 3 rd chip the sensors are small dots on the surface to give a temperature map. They are 

exactly at the same position on the 5 layers. 

A circular repartition of 9 sensors has been done to sense the temperature from the center part 

toward the externals. 

This configuration results in a 3D grid map: 

Figure 3.12 : 2D and 3D temperature map 



These small dots are circular RTDs. They have been designed for a value of 100 Ω. Again a 

4-points measurement method is used. 

Figure 3.13 : Circular RTD 

Each layer of chip n°3 comprises also 10 heaters of 1mm square that are filling 10% of the 

total surface (10x10mm 2 ). The first layer (top layer) of the chip is shown here. In this design, 

heaters are placed randomly on the surface and their locations are different for each of the 5 

layers. 

Figure 3.14 : Microheaters random configuration with circular RTDs 



3.1.4 Materials, methods and processes 

Masks used for photolithographic steps are “Chrome Blank 5'' Nanofilm”. It’s a 5x5 inch 

square plate glass covered on one side by a thin chromium layer and a thin photoresist layer. 

Two masks are needed, the first one for microheaters and sensors (in blue in the layout) and 

the second for PADs opening (in black in the layout). 

They have been patterned with the laser lithography system (DWL200) and developed with 

the DV10 equipment. Then the chromium has been etched in the bath dedicated to wet 

etching of chromium. Masks are designed for positive photoresists. 

Wafers used were 100 ± 0.5 mm in diameter and 525 ± 25 µm thick. They have been oxidized 

(200nm wet oxide) as an insulation layer for the heaters and sensors. If these components 

were deposited directly on the silicon surface some current may flow in the semiconductor 

choosing non-appropriate way through the material (not following the metallic path) with an 

energy loss at the desired place. Other influences like Schottky diode effects may appear. 

For microheaters and sensors, all the design and dimensioning have been done for a 500nm 

platinum evaporation on the surface. These structures are created using a lift-off process 

which involves a low-pressure vapor deposition (evaporation must be done instead of 

sputtering). To do this, a large distance between source and substrates is needed for a lift-off 

process (what is the case with LAB600H equipment) and then a larger amount of material is 

used (what is not welcome here due to high cost of platinum). As 500nm is quite large for a 

platinum deposition, then for a first trial aluminum has been evaporated instead of platinum to 

try the process. 

The process flow that has been used in the end is the following: 

Step Process description Cross-section after process 

01 

Substrate: Si 525µm 

Wet Oxidation 

Machine: Centrotherm 

Thickness: 200nm 

02 

Photolithography 

Machine: EVG 150 

PR : AZ1512 

Recipe : LOR-AZ1512 700nm 



03/04 

Metal Evaporation + Lift-off 

Machine: LAB 600 H 

Metal: Ti / Al 

Thickness: 10 nm / 0.5 µm 

+ Remover 

05 

Oxide sputtering 

Machine: SPIDER 600 

Thickness: 1.3 µm 

(0.8 µm more than Al layer) 

06 

Coating (Back Side) 

Oxide protection 


PR : AZ1512 – 1.5µm 

07 

Photolithography 


PR : AZ1512 – 1.5µm 

80 µm 

PAD 

100 µm 

08 

Oxide Wet Etch (SILOX) 

Material : Si02 

Machine: Wet bench SILOX 

Depth : 0.8 µm 

+ Resist Strip 

PAD 

Figure 3.15 : Process flow used for a first trial with Al metallization 

Aluminum is suitable for wire bonding, if platinum would have been evaporated as planed at 

the beginning, a soft metal must be evaporated on it in the pad location. 



First wafers have been processed with the following steps and recipes: 

Photolithography: AZ1512_on_LOR_700nm with EVG. 

Aluminum metallization with titanium adhesion layer: 10nm Ti + 500nm Al with LAB600 

and Lift-off / RT / No_IS parameters. 

Oxide sputtering with SPIDER600. Recipe SiO2-1, duration: 30min at 42.3 nm/min. 

Coating backside: AZ1512 1um5_NoEBR 

Front side photolithography: AZ1512 1um5 

(Start from the backside to avoid having two times the softbake of useful side and recipe 

without solvent on the backside during coating on EVG) 

Wet etching in SILOX bath (pad etch) with activation. 

Figure 3.16 : Pads opened in a silox bath 

Figure 3.17 : Al surface after pad opening in a silox bath 

Measured resistances (with manual prober station) for Al devices: 

Microheater 1wire: 24.6 Ω 

Microheater 3wires: 24 Ω 

RTD surrounding: 39 Ω 

RTD circular: 34.7 Ω 

(measurements include leads 

resistances) 

Figure 3.18 : Final wafer after processing steps 



Single chips have been diced with a diamond-tipped blade by an automatic dicing saw 

(DISCO DAD321). 

Stacking: 

To build the stack, single layers have been glued on top of 

each other. To have a thin uniform thickness, glue has 

been deposited by screen printing. To do this, a semiautomatic 

machine (EKRA) dedicated to thick layers 

fabrication and suitable also for gluing has been used. 

These steps have been done at LPM (“Laboratoire de 

Production Microtechnique”) - Thick-film technology 

group [25]. 

Figure 3.19 : Screen printer EKRA 

Figure 3.20 : Screen printing : principle 

The technique consists of applying the glue through a screen (a metallic grid) with the desired 

shape. After the removal of this screen, an array of small paste dots stands on the surface. 

With glue, this array changes into a uniform thin layer coating the surface. 

The screen must first be prepared, for this a layout with the desired shape is needed. This 

layout has been done simply by printing a square (on a transparent sheet to transfer it for the 

screen production) with the right dimensions (square dimensions just a bit smaller than the 

chip surface to avoid overflowing on the edges of the stack). The layout used is shown in 

appendix A. 

An epoxy resist has been used. To avoid the creation of a thermal insulating layer at the 

interface, the resist has been filled with alumina particles (Al 2 O 3 ) to lower the thermal 

resistance. Thickness deposited is around 20 - 30µm. Datasheet of the epoxy resist is shown in 

appendix B. 

Stacking itself has been done manually. For the alignment, layers have been leaned against a 

corner angle. 

Stacks have been cured 2 hours at 150°C. 



3.1.5 Results 

Figure 3.21 : 3D stacked chip, configuration n°1 

Figure 3.22 : 3D stacked chip, configuration n°3 



After the baking in an oven, first samples of 3D chips are ready. 

The connecting side is somewhat sloping because for a first try a 525µm thick wafer has been 

used. (Then stacked chips are 5x525µm thick). 

Here, the wire bonding connection of many pads seems to be quite difficult, then some tests 

have been done with a prober station. 

Multimeter 

Power supply 

Figure 3.23 : Test setup with prober station, power supplies and 

multimeter 

Resistance temperature dependence of a sensor has been tested on the chip. As aluminum has 

been evaporated instead of platinum, sensor resistance is much lower than the 100Ohm 

expected with platinum. These tests have been done on a chip where sensors are surrounding 

the heaters. 

For the experiment, a 1mA constant current is set to drive the sensor while the voltage is 

measured with the two others wires at both ends of the resistance. A current from zero to 1A 

is set in the microheater. Then several probes are needed to do the measurements for one 

device. 

Figure 3.24 : Probes on a stacked chip during measurement 



V sensor functions of I heater : 

V sensor [mV] 

40 

35 

30 

25 

20 

15 

10 

5 

0 

Al RTD 

50 

100 

150 

200 

250 

300 

350 

400 

450 

500 

550 

600 

650 

700 

750 

800 

850 

900 

950 

1000 

I heater [mA] 

Figure 3.25 : RTD response to the heat provided by its linked microheater 

The evolution of the resistance can be read directly on the voltage scale because the sensor is 

driven by a 1mA current. We can see that as expected the resistance increases with the 

temperature (typical curve for a metal). Heat provided by the microheater is the power 

dissipated as a function of the resistance multiplied by the square of the current: 

= 

So, increasing linearly the current increase the power dissipated as a square function and 

temperature variation can be considered as defined in ref. [4]: 

Heat generation - Heat dissipation = Change in internal energy 

Heat generation: 

= 

Heat dissipation: = ( ) 

 

= ∆ 

 

with R th : thermal resistance 

Change in internal energy: 

Equation becomes: 

= 

 

 

− ∆ 

 

= 

 

 

with the steady state solution: 

∆ = ∙ 

Then, temperature increase also as a square function following the power dissipated. 



We can notice that during this experiment, resistance of the microheater increases too with the 

temperature. 

For temperature measurement, the sensor should first be calibrated with an external heat 

source (a setup with a hotplate and a controlled temperature bath per example) in the range 

where it will be used. Meaning the creation of a table with incremented temperatures values 

matched to resistance values. This calibration has not been done due to lack of connections to 

the chip pads. Only simple measurements with the prober station were possible at that time. 

In Figure 3.25 the graph shows that without considering calibration and non-linearities, the 

resistance of the sensor increases with a curve shape corresponding to the equation for the 

temperature evolution as a square function of the current in the heater. 

In these first 3D stacked chips, temperature sensors are often placed around the microheaters. 

Due to the higher thermal conductivity of silicon compared to SiO 2 , heat spreads much more 

in the silicon layer. The temperature profile under the microheater is a radial gradient (a 

conduction shape factor can be defined for the thermal resistance to the substrate) and the 

highest temperature is in the middle of the microheater surface. Then in further setups, 

temperature sensors will be placed in the middle of the microheater surface to measure the 

maximal value of the hot spot, that will be the limit for the acceptable value in a functional 

chip. 



3.2 Wafer thinning 

Building a stack to create a 3D chip to take advantage of an additional dimension involves 

interconnections between these levels. This 3D concept saves surface space but foremost 

shorten the length of the connections. Then multi-layer vertical interconnections must be 

created directly through the silicon to link the levels, requiring therefore very thin layers. 

Thinning experiments have been done on chip level to reduce the thickness of small cleaved 

silicon parts from a wafer where TSV shapes were previously dry etched. The goal was to 

check the feasibility of opening the holes in an experimental way by thinning the backside of 

the silicon sample to reach the bottom holes and make real vias. 

3.2.1 Grinding and polishing machine 

To thin the silicon sample, a grinding and polishing machine has been used. This machine is 

composed of a rotating plate, a moving arm and a cylindrical mechanical system. 

(a) (b) (c) 

Figure 3.26 : Thinning equipments. (a) rotating plate with moving arm, (b) mechanical holder, (c) complete system 

The sample is held in the center part under the mechanical system with a polishing resist. A 

spring allows to adjust the force applied with which the sample is pressed on the rotating 

plate. The sample is thinned and polished on a silicon carbide paper. Several grain sizes can 

be used progressively during the process. Lubrication is done with water. 



3.2.2 Thinning experiments 

The goal was to thin a small silicon part down to 100µm to open the holes etched on its 

surface. To hold the sample a polishing resist is used, this resist is hard at room temperature 

and must be soften to be applied. To do this, it’s the metallic holder that has been heated with 

a hotplate (set at 150°C). A first test has been done by gluing the sample on the holder with 

the polishing resist that has shown significant erosion due to water lubrication and stress on 

the material. To avoid this, the sample has been prepared to be more protected during the 

thinning. First, it has been laid on “blue tape” to protect the holes. Then to hold it, a resist 

frame has been set to maintain the blue tape and to protect the edges of the sample. Like this, 

no resist remains under the sample, which enhances flatness. 

Holder 

Figure 3.27 : Assembly profile and holder 

Original sample thickness was 525mµ. 

Thicknesses have been measured throughout the grinding and polishing process on five 

different points of the sample (center and corners) with a digital dial gauge. Thinning speed 

depends on grain size, spring force (a counterweight can be used to fasten the process at the 

beginning) and table rotation speed. The rates were situated between some µm / 10 min and 

45 µm / 10 min. 

3.2.3 Results 

The result is a very thin silicon slice. The surface is shiny and reflecting. A 100µm thickness 

has been reached with openings on both sides making an array of through silicon vias. 

Figure 3.28 : 100µm thick thinned Si component with TSVs 

Holes are shown more in details in the next pages. 



Holes diameter: 100µm 

Frontside 

Backside (thinned side) 

Figure 3.29 : Holes dry etched in silicon and opened on the other side by thinning (depth: 100µm, diameter 100µm) 



Holes diameter: 50µm 

Frontside 

Backside (thinned side) 

Figure 3.30 : Holes dry etched in silicon and opened on the other side by thinning (depth: 100µm, diameter 50µm) 



Figure 3.31 : 50µm diameter hole opened by thinning 

A zoom on a 50µm diameter hole shows that it is a bit more affected by the polishing than a 

100µm hole. However, the general shape and functionality is still preserved. 



4 Heat Transfer Setup 

To build a heat transfer setup with an integrated cooling system, a new design has been done. 

Figure 4.1 : Heat transfer device with integrated fluid path (on the 

right: cross section in a fluid opening) 

The setup is composed of the chip stack glued and wire bonded to a printed circuit board. 

Microheaters provide the heat while backside microstructured cooling paths are integrated to 

study their heat transfer capabilities when dies are stacked in a complete system. A polymer 

housing component with fluid inlet/outlet and fluid connections will be placed on the top of 

the stack to lead the cooling fluid directly through the chip. Fluid openings are integrated in 

the chip. Structured interlayer opens on these fluid inlets/outlets. 

(a) 

(b) 

Figure 4.2 : Heat transfer single layer. (a) Single die with microheater and fluid openings, (b) structured backside 

Alexandre Pascarella 

P a g e | 40


4.1 Heat transfer stack 

Figure 4.3 : Profile of the 3D stacked heat transfer setup 

The stack is composed of five layers. The three layers in the middle have microheaters and 

sensors on one side and microstructured cooling pattern on the other side. The top layer is 

only structured on the backside but without heaters on the front side while the bottom layer is 

only the base of the stack. 

Two kinds of chips have been designed, one with a straight fluid path and another with a fluid 

path making a bend on the surface to carry the flow from one side to the perpendicular side of 

the chip. 

Figure 4.4 : In-line flow and corner flow configurations (orange: microheaters; blue: fluid paths) 

The heat transfer area is 10x10mm 2 and the haters are placed in line for the straight flow and 

in square for the corner flow. To sense the temperature, RTDs are again set, this time in the 

center of each heater. 



For each kind of chip, two cooling patterns are placed on the backside of the 10x10mm 2 heat 

transfer area. One is parallel microchannels, the other is a pillar array (pin fin). These patterns 

are microstructured by dry etching. 

Each layer comprises four heaters. Total area covered by the heaters is 4x10% = 40% of the 

heat transfer area. (4x10mm 2 ) 

Power density wanted for these hot zones is 200W/cm 2 . Then, the power of each 10mm 2 

heater is 20W (80W per level, 240W per stack). 

4.1.1 Heat transfer 

Heat transfer model of the stack involves heat sources from the CMOS layers, various thermal 

resistances for each layer and interface (here Si, SiO 2 and cooling fluids). Conductive and 

convective heat transfer must be taken in account in the model. Koo et al. investigate a one 

dimensional heat transfer analysis for a microchannel interlayer cooling with the previously 

mentioned parameters [16]. 

Figure 4.5 : Schematic of the thermal circuit with a 

microchannel [16] Koo et al. 

Heat transfer capabilities of the microstructured interlayer patterns are dependant of structures 

geometries. As presented in the paper “Forced convective interlayer cooling in vertically 

integrated packages” [15] from IBM, in-line pin fin has shown interesting heat transfer 

properties. Chip with perpendicular fluid openings and in line pin fin has been designed to 

have a test setup for their new ongoing porous media approach researches. The 10x10mm 2 

heat transfer area has been chosen to be in accordance with the thermal model. 

Single-phase liquid or two-phase flow advanced cooling techniques can be used. Heat transfer 

efficiency will depend on many parameters that are not exactly defined at this stage of the 

project. De-ionized water or specific refrigerants may be used. 

Dimensions of structures must also be taken in account for pressure drop considerations and 

flow rate. 



4.1.2 Layout design 

The new design mainly comprises the microheaters, thermal sensors and the fluid paths. For 

the heating and sensing elements, all the dimensioning has been done for a 200nm layer of 

platinum. 

Microheaters and RTDs (PT100) are set on three layers in the middle of the stack. Heaters are 

designed as a 80 Ohm resistance for a voltage up to 40V and a current of 0.5A per heater. The 

serpentine wire is divided into five lines to avoid hot spots in the corners. 

The sensor is located in heater center with its 4 connecting wires on the side. 

Figure 4.6 : 80Ω multi-wires rectangular microheater with RTD in the middle part for in-line flow configuration 

For devices with a straight flow, 80Ω rectangular heaters are placed on the surface. 

Dimensions are 2x5mm 2 . 

Figure 4.7 : 80Ω multi-wires square microheater with RTD in the middle part for corner flow configuration 

For devices with a corner flow, 80Ω square heaters are placed on the surface. Dimensions are 

3.16x3.16mm 2 . 



Layer 1 (top layer) in_line_flow: (layouts are shown here for microchannels, same layouts 

have been done for pin fin) 

20mm 

16mm 

Opening in 

housing 

Fluid connection diameter: 

2.4mm 

Nut diameter (of 

fluid connection) 

Figure 4.8 : Layer 1 (top layer) for in-line flow heat transfer stack 

Light-blue is the fluid inlet/outlet. This layer is etched through the whole wafer thickness. In 

blue: microchannels (width: 50µm, pitch: 100µm). They cover the 10x10mm 2 heat transfer 

area and overlap a bit these openings to guarantee the channels opening. Other marks give 

only information about the housing component that covers the stack for the fluid circuit. 



Layer 1 (top layer) corner_flow: 

20mm 

20mm 

Fluid barrier 

Opening in housing 

(tool diameter: 4mm) 

M5 

Fluid connection diameter: 

2.4mm 

Nut diameter (of 

fluid connection) 

Figure 4.9 : Layer 1 (top layer) for corner flow heat transfer stack 

In the second layout, microchannels (width: 50µm, pitch: 100µm) make straight-angles 

between the two perpendicular openings. 



Layer 2 in_line_flow: 

Figure 4.10 : Layer 2 with microheaters for in-line flow heat transfer stack 

Leads have been designed as large as possible to avoid power dissipation on other zones than 

on desired areas. Doing this for the platinum layer, two leads are still 10% (8Ω) of the total 

heater resistance. To decrease this value, aluminum can be evaporated on the leads (dark 

layer). Heat transfer area (10x10mm 2 ) is delimited by the microchannels in the center part 

(blue lines). 

Next two under layers have the same design but pads are shifted on the right (800µm) for 

stacking with a stair shape. 



Layer 2 corner_flow: 

Figure 4.11 : Layer 2 with microheaters for corner flow heat transfer stack 

On the second layout, the four microheaters are placed in a square arrangement. Sensors are 

again placed in the middle of the heaters surfaces. Fluid openings are smaller to separate them 

at the corner down on the left. Heat transfer area (10x10mm 2 ) is delimited by the 

microchannels (blue lines). Leads and pads are larger than in the in-line chip. 



Connections and pads are on the right side: (example for one heater and its sensor on 

in_line_flow layout) 

1mA 

500mA 

800µm 

Figure 4.12 : Pad configuration for a 

microheater and its sensor 

The width of the pad is a critical dimension because it must provide a sufficient area for the 

wire bonding. Many wires must be bonded to handle a 500mA current needed for the heater. 

All pads are addressable individually. 



Final layouts: 

Four kinds of chips have been designed: 

- In_line_flow with microchannels 

- In_line_flow with pin fin 

- Corner_flow with microchannels 

- Corner_flow with pin fin 

Each chip has four layers that need to be processed on a wafer. These layers have been placed 

on two wafers because of lack of space on a single wafer. For the dicing back-end step, the 

layers must be aligned in an orthogonal network. They have also been oriented to place the 

useful areas as much as possible in the center part of the wafer. 

First wafer comprises the “in_line_flow_microchannels” chip on the left column and the 

“in_line_flow_pin_fin” chip on the right column. 

Figure 4.13 : Wafer layout for in-line flow heat transfer stack 



Figure 4.14 : Wafer layout for corner flow heat transfer stack 

Second wafer comprises the “corner_flow_microchannels” chip on the left column and the 

“corner_flow_pin_fin” chip on the right column. 

Dedicated front side and backside alignment 

marks must be placed corresponding to each 

layer and ordered in accordance with the 

process. 

To facilitate the alignment a border 

surrounding the marks can be placed to have 

an open window to find wafer crosses more 

easily through the mask. 

Figure 4.15 : Front side and backside alignment marks 



4.1.3 Materials, methods and processes 

To process the wafers, a complete set of 10 masks has been done (5 masks per layout) 

- n°1: PR patterning for Ti/Pt evaporation 

- n°2: PR patterning for Al evaporation 

- n°3: PR patterning for pad opening 

- n°4: PR patterning for microchannels and pin fin dry etching 

- n°5: PR patterning for fluid inlet/outlet dry etching 

Wafers used were 100 ± 0.2 mm in diameter, 380 ± 10 µm thick and both side polished. They 

have been oxidized (200nm wet oxide on both sides) as an insulation layer for the heaters and 

sensors. 

Process flow that has been used for metallization, oxide sputtering, pad opening, etc. is the 

same kind of process that has been done for the first chip stack but with some additional steps. 

Steps and recipes for both layouts: 

Photolithography: AZ1512_on_LOR_400nm with EVG. 

Platinum metallization with titanium adhesion layer: 10nm Ti + 200nm Pt with LAB600 and 

Lift-off / RT / No_IS parameters. 

Aluminum metallization: 400nm Al with EVA 600 (E-gun and Joule effect evaporator). 

To facilitate lift-off for metallization, more openings should be placed on vacant area on the 

layout to shorten the required time of the process. 

Oxide sputtering with SPIDER600. Recipe SiO2 - wait - SiO2 – 1 

1µm - wait 15min - 1µm speed : 50nm/min 

Oxide sputtering has been done with a 15min break between two 1µm depositions to try to 

avoid pin holes on the surface that could lead to short circuit with the liquid through the 

oxide. The 15min break let time to the sample to cool down and release strain. Then second 

deposition is made directly on the surface with assumption that potential cracks may appear at 

other locations. To check this, a test wafer has been made with dummy Al heaters and with 

this method. After having protected the pads with tape, 3µm of aluminum have been sputtered 

on the surface to fill these potential pin holes. Measurement with prober station has shown no 

conductivity between a heater pad and aluminum sputtered surface. 

Coating backside: AZ1512 1um5_NoEBR 

Front side photolithography: AZ1512 1um5 

(Start from the backside to avoid having two times the softbake of useful side and recipe 

without solvent on the backside during coating on EVG) 

Wet etching in SILOX bath (pad etch) with activation (6min). 



Process flow for microchannels, pin fin and fluid openings dry etching: 

Step Process description Cross-section after process 

1 

Photolithography (Back 

Side) 

Machine: EVG 150, MA6 

PR : AZ9260 – 5µm 

2 

Dry Etch 

Microchannels and pin fin 

etching 

Material : Si02 & Si 

Machine: AMS 200 

Depth : 200µm 

3 Resist stripping 

4 

Photolithography (Front 

Side) 

Machine: EVG 150, MA6 

PR : AZ9260 – 8µm 

5 

Dry Etch – Front Side 

Fluid inlet/outlet opening 

Material : Si02 & Si 

Machine: AMS 200 

Depth : 380µm 

(through all) 

90° rotation: 

Figure 4.16 : Process flow for microchannels, pin fin and fluid openings dry etching 



Dry etching has been done with AMS 200 plasma etcher. Two processes have been used: 

Configuration: 

Materials to 

etch and 

Temperature 

Process 

• Distance ICP source 

- substrate holder 

• Substrate 

polarization (RF or 

pulsed LF) 

Mask 

Selectivity / 

mask 

Etching 

speed 

(µm/min) 

SiO 2 @ 0°C 

SiO2_PR_1:1 

200mm 

RF polarization 

PR =1:1 0.3 

Si deep 

anisotropic 

etching @ 20°C 

SOI_accurate 

++ 

200mm 

Pulsed LF polarization 

PR 

SiO 2 

> 75:1 for PR 

> 150:1 for SiO 2 

(SiO 2 etching speed 

= 20nm/min) 

4.3 

Figure 4.17 : Recipes used for SiO 2 and Si dry etching with AMS 200 

To etch microchannels, pin fin and fluid openings, as we can see on the process flow, first the 

top oxide must be removed then a deep anisotropic etching of silicon must be done to create 

the heat transfer structures with a high aspect ratio. Microchannels and pillars should be 

etched with sidewalls as vertical as possible. 

Plasma etching that has been used is a physical-chemical process as a combination of ionic 

bombardment and chemical reactions at the surface. For these two processes etchant species 

are created in the gas of the plasma. These species react with the sample surface and products 

from the reaction (substrate change into another material by chemical reaction) detach and 

diffuse again into the gas. To etch the silicon oxide layer, the process (SiO2_PR_1:1) starts 

with a thermalization at 0°C of the substrate. Substrate is polarized with a radio frequency 

(13.56MHz). Gas injected in the chamber is C 4 F 8 with a flow rate of 15sccm and a pressure of 

8.0E-3mbar. 

For Si deep etching, a Bosch process is used. It’s a pulsed process with etching and 

passivation in alternation. Sidewalls are protected by species from the reaction (organic 

compounds) that redeposit on these surfaces and avoid undercutting. Ionic bombardment 

removes this layer on horizontal surfaces while only a few particles hit the sides. Two gases 

are injected in alternation in the chamber. First C 4 F 8 with a flow rate of 150sccm during 2sec. 

then SF 6 with a flow rate of 300sccm during 7sec. Substrate is polarized with a pulsed low 

frequency and etching is done at room temperature (thermalization at 20°C). 

Microchannels and pin fin have been etched with following parameters: 

SiO2_PR_1:1 duration: 50sec. (0.2µm oxide) 

SOI_accurate++ duration: 47min. (200µm Si) 

Fluid inlet/outlet have been etched with following parameters: 

SiO2_PR_1:1 duration: 8min 30sec. (2.2µm oxide) 

SOI_accurate++ duration: 75min. 



Stacking: 

To stack the layers, two ways have been considered: polyimide bonding of the dies or gold tin 

metal soldering. 

For polyimide bonding, a 4µm layer is structured with another photoresist and dry etched at 

the same time than other structures (equipment: STS Multiplex ICP). Then, the stack can be 

cured to do the bonding. 

Figure 4.18 : Schematic process for polyimide bonding 

For AuSn metal soldering, a wetting layer (100nm Ti / 50nm Pt) must be evaporated on both 

surfaces to be bonded. Then on one side a 4µm AuSn (80/20) is deposited. For the bonding, 

the sample is heated while a pressure is applied on the stack [15]. 

These two bonding methods have not been tested before project term. 



4.2 PCB 

3D chips can be glued with underfill (low viscosity adhesive) on a small PCB where the stack 

will be wire bonded and with male header connections all around the chip. Like this, this 

device can be plugged/unplugged on a larger PCB with female header connections and with 

larger jack connectors for power supplies and analyzers. Like this only one large PCB is 

needed and no wires are needed between the two PCBs. 

Chip 

Small PCB 

Large PCB 

Figure 4.19 : Chip assembled to a small PCB and mounted on a larger one 

For small PCBs both sides are used. Some connecting wires from bond pads to header 

footprint can be placed on the backside. Red lines are on PCB front side and blue lines are on 

PCB backside. 

Figure 4.20 : Chip and connectors footprints on small 

PCB 

Figure 4.21 : Connecting wires from bonding pads to 

connectors on small PCB. Red lines: PCB front side. 

Blue lines: PCB backside. 



Connection zone for the stack (for in_line_flow chip): 

800µm 

Figure 4.22 : Pads configuration. On the left : pads from stacked chip. On the right : pads from PCB 

Vias in PCB pads middle column are placed to connect some wires on the backside due to 

short spacing available for the wires. Minimal dimensions for wires width and spacing that 

can be realized at EPFL are 100µm, limiting components density. 



Connection zone for one heater and one sensor: 

Figure 4.23 : Wire bonding configuration for a microheater and its sensor 

For wire bonding, several wires must be bonded for the heaters. Current in the heater should 

reach 500mA. A 25µm gold wire can handle about 200mA. Pads from both sides must be 

placed close to each other to shorten the wires length. 4 small pads are dedicated to the sensor 

while 2 others act as readouts for the heater. So, one wire from the heater large pad must be 

connected to a small one. 



4.3 Housing components 

(a) 

(b) 

(c) 

(d) 

Figure 4.24 : Polymer components. (a) housing for in-line flow chip, (b) housing for corner flow chip, (c) 

housing for in-line flow chip with push-in fluid connections, (d) housing for corner flow chip with pushin 

fluid connections 

Housing components have been made for the fluid circuit. Two fluid connections can be 

screwed on top and two chambers are machined on the other side for the fluid inlet/outlet. 

Design sketches are shown in appendix C. Manufacturing has been done by the mechanical 

workshop using PMMA. (PC has higher thermal properties, but wasn’t available in supply at 

that time) 

Fluid connections (Festo QSML-M5-4) can be 360° rotated. A 4mm diameter tube can be 

plugged in these push-in components. More details are shown in appendix D. 



4.4 Results 

Figure 4.25 : Aluminum evaporation on platinum thin film (400nm Al on 200nm Pt) 

Evaporation of 400nm Al on 200nm Pt has given good results. 

Figure 4.26 : Non-uniformity and delamination after oxide sputtering 

After oxide sputtering, aluminum layer suffered from some problems. Oxide uniformity and 

adhesion were not suitable. This step was critical to go on with the processes to have a 

functional stack. After some time and processes, aluminum layer unstuck from platinum layer. 

Oxide sputtering step seems to have damaged the samples. Width and flatness of the leads 

could be involved. To try to avoid this problem and identify the causes of the delamination, 

another mask for the aluminum layer deposition with a patterned structured layer has been 

done (Figure 4.27). 



Figure 4.27 : Alternative layout for Al layer 

Figure 4.28 : Al stripes on leads 

On this layout, Al stripes have been placed to have a structured layer on the leads for the 

oxide sputtering step. Al resistance on one lead is still less than 1Ω with this configuration. 

Squares have also been placed on unused areas of the wafer to enhance the lift-off process and 

to check if the adhesion problem occurs because of the large surface of the leads. 

Figure 4.29 : Al stripes evaporation on platinum thin film (400nm Al on 200nm Pt) 

As the first time, evaporation of 400nm Al on 200nm Pt has given good results. 



Figure 4.30 : Al stripes on platinum thin film and 1mm 2 square Al single layer, both after oxide sputtering 

After oxide sputtering, aluminum surface of the stripes deposited on platinum change to a 

rougher surface while this effect doesn’t appear on the large square which is a single 

aluminum layer. 

Figure 4.31 : Ti/Pt/Al/SiO2 and Al/SiO2 surfaces comparison 

At the same scale level, we can see on Figure 4.31 that the two surfaces are significantly 

different and that superimposition of Al on Pt seems to be more involved than the width of the 

leads. Differences can be due to atomic diffusion that can create intermetallic compounds 

(platinum aluminides). Diverse stress levels in the layers during deposition (that are also 

dependant of the temperature of the deposition) can also lead to delamination. 

At this point, first electrical properties of the heaters and sensors should be measured (as the 

layer is stable). In case of non-conformity with the application, titanium or titanium nitride 

interdiffusion barriers can be deposited between these layers and also on top to avoid 

oxidation of aluminum. 



In the next SEM pictures, microchannels, pin fin and fluid openings that have been dry etched 

are shown in details. 

Figure 4.32 : 200µm deep microchannels dry etched on wafer backside and linked to the fluid opening 

Figure 4.33 : 200µm high pillars dry etched on wafer backside and linked to the fluid opening 



Figure 4.34 : Microchannels and fluid opening 

Figure 4.35 : Pin fin and fluid opening 



Figure 4.36 : Pillars network 

Figure 4.37 : Pillars with higher magnification 



Figure 4.38 : Right-angled microchannels 



5 Conclusion 

3D integration strategies have great potential for many technological applications. Multi-level 

devices and stacked layers may overcome many limitations. This promising technology for 

increasing integration density opens many research fields concerning its elaboration like 

vertical connections (Through Silicon Vias), wafer thinning, heterogeneous integration or heat 

transfer. 

Stacked layers can lead to faster, less power consuming and much more efficient integrated 

circuit by reducing the length of the interconnections. However, power management becomes 

a major parameter for their functionality because the power density per volume unit becomes 

very important with stacked chips. A suitable and reliable cooling system must be integrated 

to overcome these power limitations. 

During this project, first experiments have been done to manufacture a 3D stacked chip with 

heat sources and thermal sensors on each die to emulate the power dissipated by active 

components in a CMOS chip and to sense the temperature inside of the 3D stack. Chip 

thinning experiments have shown the feasibility of thinning a single die down to 100µm. 

Then, a heat transfer setup with an integrated fluid cooling system has been designed. Dies to 

be stacked have been made on a wafer level with microfabrication processes. Some effects 

that appeared after oxide sputtering on Pt/Al thin layers must still be more investigated and 

tested if electrical measurements are not as expected (this has not been tested yet). Titanium 

or titanium nitride interdiffusion barriers could be implemented in further devices to avoid the 

formation of intermetallic compounds. Deep reactive ion etching (DRIE) of backside 

microstructures and fluid openings has given good results with anisotropic etching process in 

silicon with straight vertical walls for microchannels and pillars. Polymer components have 

been designed and produced to integrate the full system in a fluid loop for further heat transfer 

measurements. Printed circuit boards have been designed with dedicated pads to make 

connections to the microheaters and sensors by wire bonding. These PCBs can be produced to 

try the wire bonding of multi-level chips and have useful connections for the measurements 

instead of using a prober station. 

This highly-multidisciplinary project involves thermal modeling, microfabrication, single 

phase and two-phase flow heat transfer and 3D design of new types of architectures. All these 

fields should interact and stand in a near future, highly integrated in a 3D chip with advanced 

cooling technologies. 

Lausanne, January 2009 

___________________ 

Alexandre Pascarella 



6 Acknowledgment 

I would like to thank Fengda Sun, Yuksel Temiz and Prof. Leblebici for their precious help 

throughout this project; Thomas Brunschwiler and Bruno Michel from IBM (Zurich Research 

Laboratory - Advanced Thermal Packaging) for the presentation of their research work and 

laboratory, for having answered to many of my questions and shared their knowledge. 

Thanks to CMI staff for their great and very helpful help in many situations and for the 

trainings on modern and powerful processing machines. 



7 Bibliography 

Books and Lecture Notes: 

[1] M.J. Madou, Fundamentals of microfabrication, CRC Press LLC, Boca Raton – Florida, 2002 

(Second Edition). 

[2] J.G. Collier, J.R. Thome, Convective boiling and condensation, Oxford science publications, 

1996 (Third Edition). 

[3] S. Mostafa Ghiaasiaan, Two-phase flow, boiling and condensation, Cambridge University 

Press, New York, 2008. 

[4] P. Renaud, H. Shea, Scaling in MEMS, lecture notes, EPFL, 2007. 

[5] M.A.M Gijs, Technologie des microstructures I+II, lecture notes, EPFL, 2005. 

[6] P. Renaud, Capteurs I+II, lecture notes, EPFL. 2005. 

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3D integration: 

[7] Koester, S. J., Young, A. M., Yu, R. R., Purushothaman, S., Chen, K.-N., La Tulipe Jr., D. C., 

Rana, N., Shi, L., Wordeman, M. R., & Sprogis, E. J. (2008). Wafer-level 3D integration 

technology. IBM J. RES. & DEV. VOL. 52 NO. 6, 583 - 597. 

[8] Souri, S. J., Banerjee, K., Mehrota, A., & Saraswat, K. C. (2000). Multiple si layers ICs: 

Motivation, performance analysis, and design implications. Paper presented at the 213-220. 

[9] Kleiner, M. B., Kuehn, S. A., Ramm, P., & Weber, W. (1995). Thermal analysis of vertically 

integrated circuits. Paper presented at the 487-490. 

[10] Schaper, L., Burkett, S., Gordon, M., Cai, L., Liu, Y., Jampana, G., et al. (2007). Integrated 

system development for 3-D VLSI. Paper presented at the 853-857. 

[11] Schaper, L. W., Burkett, S. L., Spiesshoefer, S., Vangara, G. V., Rahman, Z., & Polamreddy, 

S. (2005). Architectural implications and process development of 3-D VLSI Z-axis 

interconnects using through silicon vias. IEEE Transactions on Advanced Packaging, 28(3), 

356-366. 

Wafer thinning: 

[12] Chen, C. -. A., & Hsu, L. -. (2008). A process model of wafer thinning by diamond grinding. 

Journal of Materials Processing Technology, 201(1-3), 606-611. 

[13] Sandireddy, S., & Jiang, T. (2005). Advanced wafer thinning technologies to enable multichip 

packages. Paper presented at the , 2005 24-27. 

[14] Jindal, A., Lu, J. -., Kwon, Y., Rajagopalan, G., McMahon, J. J., Zeng, A. Y., et al. (2003). 

Wafer thinning for monolithic 3D integration. Paper presented at the , 766 21-26. 



Heat transfer and cooling technologies: 

[15] Brunschwiler, T., Michel, B., Rothuizen, H., Kloter, U., Wunderle, B., Oppermann, H., 

Reichl, H. (2008). Forced convective interlayer cooling in vertically integrated packages. 

11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic 

Systems, pp.1114-1125. 

[16] Koo, J. -., Im, S., Jiang, L., & Goodson, K. E. (2005). Integrated microchannel cooling for 

three-dimensional electronic circuit architectures. Journal of Heat Transfer, 127(1), 49-58. 

[17] Sekar, D., King, C., Dang, B., Spencer, T., Thacker, H., Joseph, P., et al. (2008). A 3D-IC 

technology with integrated microchannel cooling. Paper presented at the 13-15. 

[18] Agostini, B., Thome, J. R., Fabbri, M., Michel, B., Calmi, D., Kloter, U., & Michel, B. (2006). 

High heat flux flow boiling in silicon multi-microchannels - part I: Materials and Methods, 

Heat Transfer Characteristics. Preprint submitted to Elsevier. 

[19] Agostini, B., Thome, J. R., Fabbri, M., Michel, B., Calmi, D., & Kloter, U. (2008). High heat 

flux flow boiling in silicon multi-microchannels - part II: Heat transfer characteristics of 

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Websites: 

[23] http://cmi.epfl.ch 

[24] http://www.zurich.ibm.com/ 

[25] http://lpm.epfl.ch/ 



8 Appendices 

8.1 Appendix A: Template for screen printing 



8.2 Appendix B: Epoxy adhesive 



8.3 Appendix C: Housing components design sketches 

PC_in_line_flow: 



PC_corner_flow: 



8.4 Appendix D: Fluid connectors

Interlayer Cooling of 3D Stacked ICs - Microelectronic Systems ...

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