Yoshio NISHI - Fondation Nanosciences

Vendredi 23 Septembre 2011
à 12h30
Yoshio NISHI
Department of Electrical Engineering,
Center for Integrated Systems, Stanford University
Nanosciences Foundation Chair of Excellence
Présentera un séminaire intitulé :
Nanoelectronic Devices and Integrations on Silicon Platform
Today and Tomorrow
Une pause sandwich sera accessible après la fin de la conférence. L’inscription est
obligatoire sur http://www.minatec.com/midis
Amphi Maison MINATEC
3 parvis Louis Néel - 38000 Grenoble

Nanoelectronic Devices and Integrations on Silicon Platform
Today and Tomorrow
There is widely shared concern today that as we approach future technology nodes of CMOS
beyond sub-20nm, diminishing return in device performance and density combined with
serious increase in on-chip power consumption would force us to seek for possible
alternatives beyond simple scaling of the minimum geometry.
Applications of mechanical strain to MOSFET channel for improved transport characteristics,
material alternatives for conductive channel of MOSFET such as germanium and/or III-V
semiconductor, intensive study for partial replacement of on-chip interconnects with optical
interconnect, new nonvolatile memory phenomena thereby feasibility of new memory devices
such as resistive switching are only a part of such efforts in addition to global trend of going
3D devices and integration. Also mentioned should include a variety of “nano” materials such
as carbon nanotube, graphene, topological insulator etc, which might capture unique positions
in integrated circuit technology arsenal with further in-depth understanding and technological
break-through for controlling their characteristics.
This talk will discuss a perspective of a variety of nanoelectronic devices to be integrated on
silicon platform, and where they would likely be heading toward.

Biography of Yoshio NISHI
Yoshio Nishi received BS in material science and PhD in electronics engineering from
Waseda University and University of Tokyo, respectively. He joined Toshiba R&D Center
where he studied silicon process technology and MOS device physics, resulting in a variety
of achievements including discovery of Si-SiO2 interface paramagnetic PB center, the
structural origin of interface states.
Later he led the development of the world first 1Mbit CMOSDRAM, 16bit SOS
microprocessor. He joined Hewlett-Packard Laboratories in 1986 as director of silicon
process laboratory for high performance CMOS R&D, followed by joinning Texas Instruments
as senior vice president and director of R&D in 1995. Since 2002 he has been professor of
electrical engineering, Stanford University, where he serves as director of research for Center
for Integrated Systems, director, Stanford Site of National Nanotechnology Infrastructure
Network.
His research activities cover resistive switching nonvolatile memory, high performance
alternative material channel MOSFETs, Ge and Si optical transmitter and graphene research.
He published more than 250 papers and conference presentations and hold more than 50
patents in Japan and US. He is IEEE Fellow, and recipients of 1995 IEEE Jack Morton
Award, 2002 IEEE Robert Noyce Medal, 2007 Technology Management award, 2008 SEMI
Lifetime achievements award.
Yoshio NISHI
Email: nishiy@stanford.edu