O pe ra tin g S ys te ms P ro cessesand T h re ads P ro cess in th e O ...
O pe ra tin g S ys te ms P ro cessesand T h re ads P ro cess in th e O ...
O pe ra tin g S ys te ms P ro cessesand T h re ads P ro cess in th e O ...
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O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng><br />
P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong><br />
dr. Tomasz Jordan Kruk<br />
T.Kruk@ia.pw.edu.pl<br />
Institu<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng> of Cont<strong>ro</strong>l & Computation Eng<strong>in</strong>eer<strong>in</strong>g<br />
Warsaw University of Technology<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 1/32<br />
P<strong>ro</strong><strong>cess</strong> <strong>in</strong> <strong>th</strong>e O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>m<br />
P<strong>ro</strong><strong>cess</strong> - an abst<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>ction of a runn<strong>in</strong>g p<strong>ro</strong>g<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>m wi<strong>th</strong> its compu<st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g<br />
envi<strong>ro</strong>nment. P<strong>ro</strong><strong>cess</strong> is a basic dynamic object <strong>in</strong> <strong>th</strong>e o<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>m.<br />
Requi<strong>re</strong>ments to be met by <strong>th</strong>e o<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>m wi<strong>th</strong> <strong>re</strong>fe<strong>re</strong>nce to p<strong>ro</strong><strong>cess</strong>es:<br />
√ <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rleav<strong>in</strong>g <strong>th</strong>e execution of multiple p<strong>ro</strong><strong>cess</strong>es to maximize p<strong>ro</strong><strong>cess</strong>or<br />
utilization while p<strong>ro</strong>vid<strong>in</strong>g <strong>re</strong>asonable <strong>re</strong>sponse time,<br />
√ alloca<st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g <strong>re</strong>sources to p<strong>ro</strong><strong>cess</strong>es <strong>in</strong> conformance wi<strong>th</strong> a s<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>cified<br />
policy, while at <strong>th</strong>e same time avoid<strong>in</strong>g deadlock,<br />
√ suppor<st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rp<strong>ro</strong><strong>cess</strong> communication,<br />
√ suppor<st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g user c<strong>re</strong>ation of p<strong>ro</strong><strong>cess</strong>es.<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 2/32<br />
Multip<strong>ro</strong>g<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>mm<strong>in</strong>g<br />
One p<strong>ro</strong>g<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>m coun<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>r<br />
A<br />
B<br />
C<br />
P<strong>ro</strong><strong>cess</strong><br />
switch<br />
Four p<strong>ro</strong>g<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>m coun<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rs<br />
D<br />
C<br />
P<strong>ro</strong><strong>cess</strong><br />
A<br />
B C D<br />
B<br />
A<br />
D<br />
Time<br />
(a) (b) (c)<br />
√ p<strong>ro</strong><strong>cess</strong> must not be p<strong>ro</strong>g<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>mmed wi<strong>th</strong> built-<strong>in</strong> assumptions about<br />
tim<strong>in</strong>g,<br />
√ <strong>th</strong>e diffe<strong>re</strong>nce between a p<strong>ro</strong><strong>cess</strong> and a p<strong>ro</strong>g<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>m,<br />
√ p<strong>ro</strong><strong>cess</strong>es sequential, concur<strong>re</strong>nt, pa<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>llel and distribu<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>d,<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 3/32<br />
P<strong>ro</strong><strong>cess</strong> C<strong>re</strong>ation and Term<strong>in</strong>ation<br />
Four pr<strong>in</strong>cipal events <strong>th</strong>at cause p<strong>ro</strong><strong>cess</strong>es to be c<strong>re</strong>a<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>d:<br />
√ s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>m <strong>in</strong>itialization,<br />
√ execution of a p<strong>ro</strong><strong>cess</strong> c<strong>re</strong>ation s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>m call by a runn<strong>in</strong>g p<strong>ro</strong><strong>cess</strong>,<br />
√ a user <strong>re</strong>quest to c<strong>re</strong>a<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng> a new p<strong>ro</strong><strong>cess</strong>,<br />
√ <strong>in</strong>itiation of a batch job.<br />
P<strong>ro</strong><strong>cess</strong> may <st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rm<strong>in</strong>a<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng> due to one of <strong>th</strong>e follow<strong>in</strong>g conditions:<br />
√ normal exit (voluntary),<br />
√ er<strong>ro</strong>r exit (voluntary),<br />
√ fatal er<strong>ro</strong>r (<strong>in</strong>voluntary),<br />
√ killed by ano<strong>th</strong>er p<strong>ro</strong><strong>cess</strong> (<strong>in</strong>voluntary).<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 4/32
P<strong>ro</strong><strong>cess</strong> Sta<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>s<br />
Blocked<br />
Runn<strong>in</strong>g<br />
1 3<br />
2<br />
4<br />
Ready<br />
1. P<strong>ro</strong><strong>cess</strong> blocks for <strong>in</strong>put<br />
2. Scheduler picks ano<strong>th</strong>er p<strong>ro</strong><strong>cess</strong><br />
3. Scheduler picks <strong>th</strong>is p<strong>ro</strong><strong>cess</strong><br />
4. Input becomes available<br />
The basic sta<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>s of a p<strong>ro</strong><strong>cess</strong>:<br />
√ runn<strong>in</strong>g - actually us<strong>in</strong>g <strong>th</strong>e CPU at <strong>th</strong>at <strong>in</strong>stant,<br />
√ <strong>re</strong>ady - runnable, <st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>mpo<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>rily stop<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>d to let ano<strong>th</strong>er p<strong>ro</strong><strong>cess</strong> run,<br />
√ blocked - unable to run until some ex<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rnal event hap<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>ns.<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 5/32<br />
P<strong>ro</strong><strong>cess</strong> Sta<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>s <strong>in</strong> <strong>th</strong>e Unix S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>m<br />
√ user runn<strong>in</strong>g,<br />
√ kernel runn<strong>in</strong>g,<br />
√ <strong>re</strong>ady to run, <strong>in</strong> memory,<br />
√ asleep <strong>in</strong> memory,<br />
√ <strong>re</strong>ady to run, swap<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>d,<br />
√ sleep<strong>in</strong>g, swap<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>d,<br />
√ p<strong>re</strong>emp<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>d,<br />
√ c<strong>re</strong>a<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>d,<br />
√ zombie.<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 6/32<br />
Unix P<strong>ro</strong><strong>cess</strong> Sta<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng> T<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>nsition Diag<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>m<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 7/32<br />
Scheduler<br />
P<strong>ro</strong><strong>cess</strong>es<br />
0 1 n – 2 n – 1<br />
Scheduler<br />
The lowest layer of a p<strong>ro</strong><strong>cess</strong>-structu<strong>re</strong>d o<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>m handles <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupts<br />
and schedul<strong>in</strong>g. Above <strong>th</strong>at layer <strong>th</strong>e<strong>re</strong> a<strong>re</strong> sequential p<strong>ro</strong><strong>cess</strong>es.<br />
For p<strong>ro</strong><strong>cess</strong>or allocation for particular p<strong>ro</strong>cesess a piece of an OS kernel<br />
called scheduler is <strong>re</strong>sponsible.<br />
P<strong>ro</strong><strong>cess</strong> implementation:<br />
√ <strong>th</strong>e OS ma<strong>in</strong>ta<strong>in</strong>s a table (an ar<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>y of structu<strong>re</strong>s) called <strong>th</strong>e p<strong>ro</strong><strong>cess</strong><br />
table, wi<strong>th</strong> one entry <st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>r p<strong>ro</strong><strong>cess</strong>. Sometimes <strong>th</strong>ose entries a<strong>re</strong> called<br />
p<strong>ro</strong><strong>cess</strong> descriptors or p<strong>ro</strong><strong>cess</strong> cont<strong>ro</strong>l blocks, PCB.<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 8/32
Some Fields of a Typical P<strong>ro</strong><strong>cess</strong> Table Entry<br />
P<strong>ro</strong><strong>cess</strong> management Memory management<br />
Regis<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rs Po<strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>r to <st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>xt segment<br />
P<strong>ro</strong>g<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>m coun<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>r Po<strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>r to data segment<br />
P<strong>ro</strong>g<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>m Status Word Po<strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>r to stack segment<br />
Stack po<strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>r<br />
P<strong>ro</strong><strong>cess</strong> sta<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><br />
Priority<br />
Schedul<strong>in</strong>g pa<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>me<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rs File management<br />
P<strong>ro</strong><strong>cess</strong> ID <strong>ro</strong>ot di<strong>re</strong>ctory<br />
Pa<strong>re</strong>nt p<strong>ro</strong>ces Work<strong>in</strong>g di<strong>re</strong>ctory<br />
P<strong>ro</strong><strong>cess</strong> g<strong>ro</strong>up File descriptors<br />
Signals User ID<br />
Time when p<strong>ro</strong><strong>cess</strong> star<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>d G<strong>ro</strong>up ID<br />
CPU time used<br />
Time of next alarm<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 9/32<br />
In<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupt Revisi<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>d<br />
√ when an I/O device has f<strong>in</strong>ished <strong>th</strong>e work given to it, it causes an <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupt by<br />
asser<st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g a signal on a bus l<strong>in</strong>e it has been assigned,<br />
√ <strong>th</strong>e signal de<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>c<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>d by <strong>th</strong>e <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupt cont<strong>ro</strong>ller chip on <strong>th</strong>e mo<strong>th</strong>erboard,<br />
√ if no <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupts <st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>nd<strong>in</strong>g, <strong>th</strong>e <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupt cont<strong>ro</strong>ller p<strong>ro</strong><strong>cess</strong>es <strong>th</strong>e <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupt<br />
immedia<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>ly - it puts a number on <strong>th</strong>e add<strong>re</strong>ss l<strong>in</strong>es s<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>cify<strong>in</strong>g which device<br />
wants at<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>ntion and asserts a signal <strong>th</strong>at <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupts <strong>th</strong>e CPU,<br />
√ <strong>th</strong>e CPU stops cur<strong>re</strong>nt work and uses <strong>th</strong>e number on <strong>th</strong>e add<strong>re</strong>ss l<strong>in</strong>es as an<br />
<strong>in</strong>dex <strong>in</strong>to a table called <strong>th</strong>e <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupt vector to fetch a new p<strong>ro</strong>g<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>m coun<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>r,<br />
√ <strong>th</strong>e coun<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>r po<strong>in</strong>ts to <strong>th</strong>e start of <strong>th</strong>e cor<strong>re</strong>spond<strong>in</strong>g <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupt service p<strong>ro</strong>cedu<strong>re</strong>,<br />
√ shortly af<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>r star<st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g runn<strong>in</strong>g, <strong>th</strong>e <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupt service p<strong>ro</strong>cedu<strong>re</strong> acknowledges <strong>th</strong>e<br />
<strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupt by wri<st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g a certa<strong>in</strong> value to one of <strong>th</strong>e <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupt cont<strong>ro</strong>ller’s I/O ports -<br />
<strong>th</strong>e cont<strong>ro</strong>ller is now f<strong>re</strong>e to issue ano<strong>th</strong>er <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupt,<br />
√ <strong>th</strong>e hardwa<strong>re</strong> alwa<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng> saves certa<strong>in</strong> <strong>in</strong>formation befo<strong>re</strong> star<st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g <strong>th</strong>e service<br />
p<strong>ro</strong>cedu<strong>re</strong>, at least <strong>th</strong>e p<strong>ro</strong>g<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>m coun<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>r but <strong>in</strong> some archi<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>ctu<strong>re</strong>s all <strong>th</strong>e visible<br />
<strong>re</strong>gis<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rs and a large number of <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rnal ones.<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 10/32<br />
Activities of <strong>th</strong>e OS When an In<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupt Occurs<br />
1. Save any <strong>re</strong>gis<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rs (<strong>in</strong>clud<strong>in</strong>g <strong>th</strong>e PSW) <strong>th</strong>at have not al<strong>re</strong>ady been saved by <strong>th</strong>e<br />
<strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupt handler.<br />
2. Set up a con<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>xt for <strong>th</strong>e <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupt service p<strong>ro</strong>cedu<strong>re</strong>. Do<strong>in</strong>g <strong>th</strong>is may <strong>in</strong>volve<br />
set<st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g up <strong>th</strong>e TLB, MMU and a page table.<br />
3. Set up a stack for <strong>th</strong>e <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupt service p<strong>ro</strong>cedu<strong>re</strong>.<br />
4. Acknowledge <strong>th</strong>e <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupt cont<strong>ro</strong>ller. If <strong>th</strong>e<strong>re</strong> is no cent<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>lised <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupt<br />
cont<strong>ro</strong>ller, <strong>re</strong>enable <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupts.<br />
5. Copy <strong>th</strong>e <strong>re</strong>gis<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rs f<strong>ro</strong>m whe<strong>re</strong> <strong>th</strong>ey we<strong>re</strong> saved (possibly some stack) to <strong>th</strong>e<br />
p<strong>ro</strong><strong>cess</strong> table.<br />
6. Run <strong>th</strong>e <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupt service p<strong>ro</strong>cedu<strong>re</strong>. It will ext<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>ct <strong>in</strong>formation f<strong>ro</strong>m <strong>th</strong>e<br />
<strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrup<st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g device cont<strong>ro</strong>ller’s <strong>re</strong>gis<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rs.<br />
7. Choose which p<strong>ro</strong><strong>cess</strong> to run next.<br />
8. Set up <strong>th</strong>e MMU con<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>xt for <strong>th</strong>e p<strong>ro</strong><strong>cess</strong> to run next. Some TLB setup may also<br />
be needed.<br />
9. Load <strong>th</strong>e new p<strong>ro</strong><strong>cess</strong>’ <strong>re</strong>gis<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rs, <strong>in</strong>clud<strong>in</strong>g <strong>th</strong>e PSW.<br />
10. Start runn<strong>in</strong>g <strong>th</strong>e new p<strong>ro</strong><strong>cess</strong>.<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 11/32<br />
Th<strong>re</strong><strong>ads</strong> of Execution<br />
When <strong>th</strong>e<strong>re</strong> is a need for concur<strong>re</strong>nt <strong>th</strong><strong>re</strong><strong>ads</strong> of execution organized as a<br />
g<strong>ro</strong>up of p<strong>ro</strong><strong>cess</strong>es, hav<strong>in</strong>g sepa<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>d p<strong>ro</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>c<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>d add<strong>re</strong>ss spaces means:<br />
√ f<strong>ro</strong>m <strong>th</strong>e po<strong>in</strong>t of view of p<strong>ro</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>ction: an advantage, but he<strong>re</strong> we p<strong>ro</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>ct our<br />
p<strong>ro</strong><strong>cess</strong>es aga<strong>in</strong>st our p<strong>ro</strong><strong>cess</strong>es,<br />
√ f<strong>ro</strong>m <strong>th</strong>e po<strong>in</strong>t of view of communication: a d<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>wback,<br />
√ f<strong>ro</strong>m <strong>th</strong>e po<strong>in</strong>t of view of <strong>th</strong>e level of simplicity <strong>in</strong> shar<strong>in</strong>g <strong>re</strong>sources: a d<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>wback,<br />
√ f<strong>ro</strong>m <strong>th</strong>e po<strong>in</strong>t of view of <st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>rformance: a d<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>wback, at least if p<strong>ro</strong><strong>cess</strong>es not<br />
pa<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>llel,<br />
Thus, maybe we should consider put<st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g toge<strong>th</strong>er coo<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g <strong>th</strong><strong>re</strong><strong>ads</strong> of<br />
execution <strong>in</strong>to one sha<strong>re</strong>d add<strong>re</strong>ss space, and <strong>th</strong>is would meant:<br />
√ f<strong>ro</strong>m <strong>th</strong>e po<strong>in</strong>t of view of p<strong>ro</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>ction: a d<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>wback, but we a<strong>re</strong> <strong>th</strong>e au<strong>th</strong>or of <strong>th</strong>e<br />
coo<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g <strong>th</strong><strong>re</strong><strong>ads</strong> codes and we should know what we do,<br />
√ f<strong>ro</strong>m <strong>th</strong>e po<strong>in</strong>t of view of communication: an advantage,<br />
√ f<strong>ro</strong>m <strong>th</strong>e po<strong>in</strong>t of view of <strong>th</strong>e level of simplicity <strong>in</strong> shar<strong>in</strong>g <strong>re</strong>sources: an<br />
advantage.<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 12/32
P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> Attribu<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>s<br />
Per p<strong>ro</strong><strong>cess</strong> i<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> Per <strong>th</strong><strong>re</strong>ad i<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng><br />
Add<strong>re</strong>ss space P<strong>ro</strong>g<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>m coun<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>r<br />
Global variables Regis<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rs<br />
O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>n files Stack<br />
Child p<strong>ro</strong><strong>cess</strong>es Sta<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><br />
Pend<strong>in</strong>g alar<st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng><br />
Signals and signal handlers<br />
Accoun<st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g <strong>in</strong>formation<br />
Th<strong>re</strong><strong>ads</strong> of <strong>th</strong>e same p<strong>ro</strong><strong>cess</strong> may exchange <strong>in</strong>formation wi<strong>th</strong> usage of global<br />
variables of <strong>th</strong>e p<strong>ro</strong><strong>cess</strong>.<br />
√ what wi<strong>th</strong> <strong>th</strong><strong>re</strong><strong>ads</strong> as<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>cts when <strong>th</strong>e subp<strong>ro</strong><strong>cess</strong> is c<strong>re</strong>a<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>d?<br />
√ what is <strong>th</strong>e cor<strong>re</strong>ct layer for servic<strong>in</strong>g signals?<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 13/32<br />
Th<strong>re</strong><strong>ads</strong> Stack<br />
Th<strong>re</strong>ad 2<br />
Th<strong>re</strong>ad 1<br />
Th<strong>re</strong>ad 3<br />
P<strong>ro</strong><strong>cess</strong><br />
Th<strong>re</strong>ad 1's<br />
stack<br />
Th<strong>re</strong>ad 3's stack<br />
Kernel<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 14/32<br />
Multi<strong>th</strong><strong>re</strong>aded Server<br />
Web server p<strong>ro</strong><strong>cess</strong><br />
Dispatcher <strong>th</strong><strong>re</strong>ad<br />
Worker <strong>th</strong><strong>re</strong>ad<br />
User<br />
space<br />
Web page cache<br />
Kernel<br />
Kernel<br />
space<br />
Network<br />
connection<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 15/32<br />
An Outl<strong>in</strong>e of <strong>th</strong>e Multi<strong>th</strong><strong>re</strong>aded Server Algori<strong>th</strong>m<br />
while (TRUE) { while (TRUE) {<br />
get_next_<strong>re</strong>quest(&buf); wait_for_work(&buf)<br />
handoff_work(&buf); look_for_page_<strong>in</strong>_cache(&buf, &page);<br />
} if (page_not_<strong>in</strong>_cache(&page))<br />
<strong>re</strong>ad_page_f<strong>ro</strong>m_disk(&buf, &page);<br />
<strong>re</strong>turn_page(&page);<br />
}<br />
(a) (b)<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 16/32
Me<strong>th</strong>ods of Server Construction<br />
Th<strong>re</strong>e wa<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng> to construct a server<br />
√ <strong>th</strong><strong>re</strong><strong>ads</strong> - pa<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>llelism, block<strong>in</strong>g s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>m calls,<br />
√ s<strong>in</strong>gle-<strong>th</strong><strong>re</strong>aded p<strong>ro</strong><strong>cess</strong> - no pa<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>llelism, block<strong>in</strong>g s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>m calls,<br />
√ f<strong>in</strong>i<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>-sta<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng> mach<strong>in</strong>e - pa<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>llelism, nonblock<strong>in</strong>g s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>m calls, <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rrupts.<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 17/32<br />
Kernel-level <strong>th</strong><strong>re</strong><strong>ads</strong> and User-level Th<strong>re</strong><strong>ads</strong><br />
P<strong>ro</strong><strong>cess</strong> Th<strong>re</strong>ad P<strong>ro</strong><strong>cess</strong> Th<strong>re</strong>ad<br />
User<br />
space<br />
Kernel<br />
space<br />
Kernel<br />
Kernel<br />
Run-time<br />
s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>m<br />
Th<strong>re</strong>ad<br />
table<br />
P<strong>ro</strong><strong>cess</strong><br />
table<br />
P<strong>ro</strong><strong>cess</strong><br />
table<br />
Th<strong>re</strong>ad<br />
table<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 18/32<br />
Th<strong>re</strong><strong>ads</strong> – Hybrid Solutions<br />
Multiple user <strong>th</strong><strong>re</strong><strong>ads</strong><br />
on a kernel <strong>th</strong><strong>re</strong>ad<br />
User<br />
space<br />
Kernel<br />
Kernel <strong>th</strong><strong>re</strong>ad<br />
Kernel<br />
space<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 19/32<br />
Multi<strong>th</strong><strong>re</strong>aded Archi<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>ctu<strong>re</strong> under Solaris OS<br />
Solaris makes use of four sepa<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng> <strong>th</strong><strong>re</strong>ad-<strong>re</strong>la<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>d concepts:<br />
√ P<strong>ro</strong><strong>cess</strong> - <strong>th</strong>e normal Unix p<strong>ro</strong><strong>cess</strong>,<br />
√ User-level <strong>th</strong><strong>re</strong><strong>ads</strong> - ULTs, implemen<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>d <strong>th</strong><strong>ro</strong>ugh a <strong>th</strong><strong>re</strong><strong>ads</strong> lib<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>ry <strong>in</strong> <strong>th</strong>e<br />
add<strong>re</strong>ss space of a p<strong>ro</strong><strong>cess</strong>,<br />
⋆ <strong>in</strong>visible to <strong>th</strong>e o<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>m,<br />
⋆ <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rface for application pa<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>llelism.<br />
√ Lightweight p<strong>ro</strong><strong>cess</strong>es - LWPs, a mapp<strong>in</strong>g between ULTs and kernel<br />
<strong>th</strong><strong>re</strong><strong>ads</strong>,<br />
⋆ each LWP supports one or mo<strong>re</strong> ULTs and maps to one kernel <strong>th</strong><strong>re</strong>ad,<br />
⋆ LWPs a<strong>re</strong> scheduled by <strong>th</strong>e kernel <strong>in</strong>de<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>ndently,<br />
⋆ LWPs may execu<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng> <strong>in</strong> pa<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>llel on multip<strong>ro</strong><strong>cess</strong>ors.<br />
√ Kernel <strong>th</strong><strong>re</strong><strong>ads</strong> fundamental entities <strong>th</strong>at can be scheduled and<br />
dispatched to run on one of <strong>th</strong>e s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>m p<strong>ro</strong><strong>cess</strong>ors.<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 20/32
Th<strong>re</strong><strong>ads</strong> under Solaris – an Example<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 21/32<br />
Mig<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>tion to <strong>th</strong>e Multi<strong>th</strong><strong>re</strong>aded Code<br />
Th<strong>re</strong>ad 1 Th<strong>re</strong>ad 2<br />
Ac<strong>cess</strong> (errno set)<br />
O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>n (errno overwrit<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>n)<br />
Errno <strong>in</strong>s<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>c<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>d<br />
<br />
Time<br />
ex<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rn <strong>in</strong>t *___errno();<br />
#def<strong>in</strong>e errno (*(___errno()))<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 22/32<br />
(a)<br />
(b)<br />
Priva<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng> Global Variables<br />
Th<strong>re</strong>ad 1's<br />
code<br />
Th<strong>re</strong>ad 2's<br />
code<br />
Th<strong>re</strong>ad 1's<br />
stack<br />
Th<strong>re</strong>ad 2's<br />
stack<br />
Th<strong>re</strong>ad 1's<br />
globals<br />
Th<strong>re</strong>ad 2's<br />
globals<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 23/32<br />
P<strong>ro</strong><strong>cess</strong>or-bound and I/O-bound P<strong>ro</strong><strong>cess</strong>es<br />
Long CPU burst<br />
Short CPU burst<br />
Wai<st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g for I/O<br />
Time<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 24/32
P<strong>ro</strong><strong>cess</strong>es Schedul<strong>in</strong>g<br />
The<strong>re</strong> a<strong>re</strong> two basic schedul<strong>in</strong>g <st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>chniques:<br />
√ nonp<strong>re</strong>emptive schedul<strong>in</strong>g,<br />
√ p<strong>re</strong>emptive schedul<strong>in</strong>g.<br />
The<strong>re</strong> a<strong>re</strong> diffe<strong>re</strong>nt <strong>re</strong>qui<strong>re</strong>ments for diffe<strong>re</strong>nt envi<strong>ro</strong>nments: batch s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng>,<br />
<strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>ctive s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng>, <strong>re</strong>al-time s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng>.<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 25/32<br />
Featu<strong>re</strong>s of <strong>th</strong>e Good Schedul<strong>in</strong>g Algori<strong>th</strong>m<br />
All s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng><br />
√ fairness - giv<strong>in</strong>g each p<strong>ro</strong><strong>cess</strong> a fair sha<strong>re</strong> of <strong>th</strong>e CPU,<br />
√ policy enforcement - see<strong>in</strong>g <strong>th</strong>at sta<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>d policy is carried out,<br />
√ balance - keep<strong>in</strong>g all parts of <strong>th</strong>e s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>m busy.<br />
Batch s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng><br />
√ <strong>th</strong><strong>ro</strong>ughput - maximize jobs <st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>r hour,<br />
√ turna<strong>ro</strong>und time - m<strong>in</strong>imize time between submisission and <st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>rm<strong>in</strong>antion,<br />
√ CPU utilization - keep <strong>th</strong>e CPU busy all <strong>th</strong>e time.<br />
In<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>ctive s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng><br />
√ <strong>re</strong>sponse time - <strong>re</strong>spond to <strong>re</strong>quests quickly,<br />
√ p<strong>ro</strong>portionality - meet users’ ex<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>ctations.<br />
Real-time s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng><br />
√ mee<st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g deadl<strong>in</strong>es - avoid los<strong>in</strong>g data,<br />
√ p<strong>re</strong>dictability - avoid quality deg<st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>dation <strong>in</strong> mulimedia s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng>.<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 26/32<br />
Schedul<strong>in</strong>g <strong>in</strong> Batch S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng><br />
8 4 4 4<br />
4 4 4 8<br />
A B C D<br />
B C D A<br />
(a)<br />
Shor<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>st Job First Schedul<strong>in</strong>g<br />
(b)<br />
Schedul<strong>in</strong>g <strong>in</strong> batch s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng><br />
√ FCFS, First-Come First-Served,<br />
√ SJF, Shor<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>st Job First,<br />
√ SRTN, Shor<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>st Rema<strong>in</strong><strong>in</strong>g Time Next,<br />
√ Th<strong>re</strong>e-Level Schedul<strong>in</strong>g.<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 27/32<br />
Th<strong>re</strong>e-Level Schedul<strong>in</strong>g<br />
CPU<br />
CPU scheduler<br />
Arriv<strong>in</strong>g<br />
job<br />
Input<br />
queue<br />
Ma<strong>in</strong><br />
Memory<br />
Admission<br />
scheduler<br />
Memory<br />
scheduler<br />
Disk<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 28/32
Schedul<strong>in</strong>g <strong>in</strong> In<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>ctive S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng><br />
Cur<strong>re</strong>nt<br />
p<strong>ro</strong><strong>cess</strong><br />
Next<br />
p<strong>ro</strong><strong>cess</strong><br />
Cur<strong>re</strong>nt<br />
p<strong>ro</strong><strong>cess</strong><br />
B F D G A<br />
F D G A B<br />
(a)<br />
Round-Rob<strong>in</strong> schedul<strong>in</strong>g<br />
(b)<br />
Schedul<strong>in</strong>g <strong>in</strong> <strong>in</strong><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng>ctive s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng><br />
√ Round-Rob<strong>in</strong> algori<strong>th</strong>m,<br />
√ priority schedul<strong>in</strong>g,<br />
√ shor<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>st p<strong>ro</strong><strong>cess</strong> next (estimation).<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 29/32<br />
Schedul<strong>in</strong>g wi<strong>th</strong> Classes of Priorities<br />
Queue<br />
headers<br />
Runable p<strong>ro</strong><strong>cess</strong>es<br />
Priority 4<br />
(Highest priority)<br />
Priority 3<br />
Priority 2<br />
Priority 1<br />
(Lowest priority)<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 30/32<br />
Schedul<strong>in</strong>g <strong>in</strong> Real-time S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng><br />
√ s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> wi<strong>th</strong> soft and hard <strong>re</strong>qui<strong>re</strong>ments,<br />
√ <st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>riodic and a<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>riodic events,<br />
m∑<br />
Ci<br />
≤ 1<br />
i=1<br />
Pi<br />
A <strong>re</strong>al-time s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>m <strong>th</strong>at meets <strong>th</strong>is cri<st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>ria is said to be schedulable.<br />
√ C i time of one service of <st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>riodic event,<br />
√ P i <st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>riod of <st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng>riodic event occu<strong>re</strong>nce.<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 31/32<br />
Th<strong>re</strong><strong>ads</strong> Schedul<strong>in</strong>g<br />
Order <strong>in</strong> which<br />
<strong>th</strong><strong>re</strong><strong>ads</strong> run<br />
P<strong>ro</strong><strong>cess</strong> A P<strong>ro</strong><strong>cess</strong> B P<strong>ro</strong><strong>cess</strong> A P<strong>ro</strong><strong>cess</strong> B<br />
2. Runtime<br />
s<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng>m<br />
picks a<br />
<strong>th</strong><strong>re</strong>ad<br />
1 2 3 1 3 2<br />
1. Kernel picks a p<strong>ro</strong><strong>cess</strong> 1. Kernel picks a <strong>th</strong><strong>re</strong>ad<br />
Possible: A1, A2, A3, A1, A2, A3<br />
Not possible: A1, B1, A2, B2, A3, B3<br />
√ a. for user-level <strong>th</strong><strong>re</strong><strong>ads</strong>,<br />
√ b. for kernel-level <strong>th</strong><strong>re</strong><strong>ads</strong>.<br />
Possible: A1, A2, A3, A1, A2, A3<br />
Also possible: A1, B1, A2, B2, A3, B3<br />
(a) (b)<br />
Faculty of E&IT, Warsaw University of Technology O<st<strong>ro</strong>ng>pe</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ra</st<strong>ro</strong>ng><st<strong>ro</strong>ng>t<strong>in</strong></st<strong>ro</strong>ng>g S<st<strong>ro</strong>ng>ys</st<strong>ro</strong>ng><st<strong>ro</strong>ng>te</st<strong>ro</strong>ng><st<strong>ro</strong>ng>ms</st<strong>ro</strong>ng> / P<strong>ro</strong><strong>cess</strong>es and Th<strong>re</strong><strong>ads</strong> – p. 32/32