Crystal - cs5336.pdf

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CS5336, CS5338, CS5339 RECOMMENDED OPERATING CONDITIONS (AGND, LGND, DGND = 0V; all voltages with respect to ground) Parameter Symbol Min Typ Max Units DC Power Supplies: Positive Digital VD+ 4.75 5.0 VA+ V Positive Logic VL+ 4.75 5.0 VA+ V Positive Analog VA+ 4.75 5.0 5.25 V _ _ _ Negative Analog VA- 4.75 5.0 5.25 V Analog Input Voltage (Note 7) _ VAIN 3.68 - 3.68 V Notes: 7. The ADCs accept input voltages up to the analog supplies (VA+, VA-). They will produce a positive full-scale output for inputs above 3.68 V and negative full-scale output for inputs below -3.68 V. These values are subject to the gain error tolerance specification. Additional tag bits are output to indicate the amount of overdrive. Ferrite Bead +5V Analog 0.1 µF 0.1 µF + 1 µF 0.1 µF 51 Ω 4 25 18 28 VA+ VL+ VD+ APD VREF 10 µF 0.1 µF + DPD ACAL Left Analog Input DCAL 2 AINL CS5336 51 Ω 10 nF SMODE CS5338 CMODE Right Analog Input 27 AINR CS5339 51 Ω 10 nF A/D CONVERTER SDATA + 6 10 7 9 13 12 16 1 µF +5V Digital Power Down & Calibrate Control Mode Settings Audio Data Processor -5V Analog VA+ 3 ZEROL 26 ZEROR 1 AGND 8 22 NC NC VA- LGND DGND 5 24 19 0.1 µF L/R SCLK FSYNC ICLKD OCLKD ICLKA TST 11 14 15 17 20 21 23 Timing Logic & Clock Ferrite bead may be used if VD+ is derived from VA+. If used, do not drive any other logic from VD+. An example ferrite bead is Permag VK200-2.5/52 + 1 µF Figure 1. Typical Connection Diagram 3-44 DS23F1
CS5336, CS5338, CS5339 GENERAL DESCRIPTION The CS5336, CS5338, and CS5339 are 16-bit, 2- channel A/D converters designed specifically for stereo digital audio applications. The devices use two one-bit delta-sigma modulators which simultaneously sample the analog input signals at a 64 X sampling rate. The resulting serial bit streams are digitally filtered, yielding pairs of 16-bit values. This technique yields nearly ideal conversion performance independent of input frequency and amplitude. The converters do not require difficultto-design or expensive anti-alias filters, and do not require external sample-and-hold amplifiers or a voltage reference. An on-chip voltage reference provides for an input signal range of ± 3.68 volts. Any zero offset is internally calibrated out during a power-up selfcalibration cycle. Output data is available in serial form, coded as 2’s complement 16-bit numbers. Typical power consumption of only 400 mW can be further reduced by use of the power-down mode. For more information on delta-sigma modulation and the particular implementation inside these ADCs, see the references at the end of this data sheet. OCLKD/ L/R CMODE ICLKD ICLKA SCLK (kHz) (MHz) (MHz) (MHz) 32 low 8.192 4.096 2.048 32 high 12.288 4.096 2.048 44.1 low 11.2896 5.6448 2.8224 44.1 high 16.9344 5.6448 2.8224 48 low 12.288 6.144 3.072 48 high 18.432 6.144 3.072 Table 1. Common Clock Frequencies SYSTEM DESIGN Very few external components are required to support the ADC. Normal power supply decoupling components, voltage reference bypass capacitors and a single resistor and capacitor on each input for anti-aliasing are all that’s required, as shown in Figure 1. Master Clock Input The master input clock (ICLKD) into the ADC runs the digital filter, and is used to generate the modulator sampling clock. ICLKD frequency is determined by the desired Output Word Rate (OWR) and the setting of the CMODE pin. CMODE high will set the required ICLKD frequency to 384 X OWR, while CMODE low will set the required ICLKD frequency to 256 X OWR. Table 1 shows some common clock frequencies. The digital output clock (OCLKD) is always equal to 128 X OWR, which is always 2 X the input sample rate. OCLKD should be connected to ICLKA, which controls the input sample rate. The phase alignment between ICLKD and OCLKD is determined as follows: when CMODE is ICLKD Input DPD Input _ L/ R Input OCLKD Output _ L/ R Input OCLKD Output 1 1 2 2 * ** 0 1 2 3 4 5 6 7 *** * DPD low is recognized on the next ICLKD rising edge (#0) ** L/R rising before ICLKD rising #2 causes OCLKD -1 *** L/R rising after ICLKD rising #2 causes OCLKD - 2 Figure 2. ICLKD to OCLKD Timing with CMODE high (384 X OWR) DS23F1 3-45
Page 1 and 2: Semiconductor Corporation 16-Bit, S
Page 3 and 4: CS5336, CS5338, CS5339 DIGITAL FILT
Page 5: CS5336, CS5338, CS5339 t clkh t clk
Page 9 and 10: CS5336, CS5338, CS5339 * L/ R Input
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Page 21: CS5336, CS5338, CS5339 REFERENCES 1

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