Crystal - cs5336.pdf

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CS5336, CS5338, CS5339 SWITCHING CHARACTERISTICS (TA = 25 °C; VA+, VL+, VD+ = 5V ± 5%; VA- = -5V ± 5%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 20 pF) Parameter Symbol Min Typ Max Unit ICLKD Period (CMODE low) (Note 6) t clkw1 78 - 3906 ns ICLKD Low (CMODE low) t clkl1 31 - - ns ICLKD High (CMODE low) t clkh1 31 - - ns ICLKD rising to OCLKD rising (CMODE low) t io1 5 - 40 ns ICLKD Period (CMODE high) t clkw2 52 - 2604 ns ICLKD Low (CMODE high) t clkl2 20 - - ns ICLKD High (CMODE high) t clkh2 20 - - ns ICLKD rising or falling to OCLKD rising (CMODE high, Note 4) t io2 5 - 45 ns ICLKD rising to L/R edge (CMODE low, MASTER mode) t ilr1 5 - 50 ns ICLKD rising to FSYNC edge (CMODE low, MASTER mode) t ifs1 5 - 50 ns ICLKD rising to SCLK edge (CMODE low, MASTER mode) t isclk1 5 - 50 ns ICLKD falling to L/R edge (CMODE high, MASTER mode) t ilr2 5 - 50 ns ICLKD falling to FSYNC edge (CMODE high, MASTER mode) t ifs2 5 - 50 ns ICLKD falling to SCLK edge (CMODE high, MASTER mode) t isclk2 5 - 50 ns SCLK rising to SDATA valid (MASTER mode, Note 5) t sdo 0 - 50 ns SCLK duty cycle (MASTER mode) 40 50 60 % SCLK rising to L/R (MASTER mode, Note 5) t mslr -20 - 20 ns SCLK rising to FSYNC (MASTER mode, Note 5) t msfs -20 - 20 ns SCLK Period (SLAVE mode) t sclkw 155 - - ns SCLK Pulse Width Low (SLAVE mode) t sclkl 60 - - ns SCLK Pulse Width High (SLAVE mode) t sclkh 60 - - ns SCLK rising to SDATA valid (SLAVE mode, Note 5) t dss - - 50 ns L/R edge to MSB valid (SLAVE mode) t lrdss - - 50 ns Falling SCLK to L/R edge delay (SLAVE mode, Note 5) t slr1 30 - - ns L/R edge to falling SCLK setup time (SLAVE mode, Note 5) t slr2 30 - - ns Falling SCLK to rising FSYNC delay (SLAVE mode, Note 5) t sfs1 30 - - ns Rising FSYNC to falling SCLK setup time (SLAVE mode, Note 5) t sfs2 30 - - ns DPD pulse width t pdw 2 x tclkw - - ns DPD rising to DCAL rising t pcr - - 50 ns DPD falling to DCAL falling (OWR = Output Word Rate) t pcf - 4096 - 1/OWR Notes: 4. ICLKD rising or falling depends on DPD to L/R timing (see Figure 2). 5. SCLK is shown for CS5336, CS5338. SCLK is inverted for CS5339. 6. Specifies minimum output word rate (OWR) of 1 kHz. 3-42 DS23F1
CS5336, CS5338, CS5339 t clkh t clkl t clkh2 t clkl2 ICLKD ICLKD t clkw1 t clkw2 OCLKD (CMODE low) t io1 OCLKD (CMODE high) t io2 L/R output (MASTER mode) L/R output (MASTER mode) t ilr1 t ilr2 FSYNC output (MASTER mode) t ifs1 FSYNC output (MASTER mode) t ifs2 SCLK output (MASTER mode) SCLK output (MASTER mode) t isclk1 t isclk2 ICLKD to Outputs Propagation Delays (CMODE low) ICLKD to Outputs Propagation Delays (CMODE high) SCLK output (MASTER mode) t mslr L/ R output (MASTER mode) t pdw t pcf t sdo SDATA DPD t msfs t pcr FSYNC output (MASTER mode) SCLK to SDATA, L/R & FSYNC - MASTER Mode DCAL Power Down & Calibration Timing t slr1 t slr2 t sclkh t sclkl SCLK input (SLAVE mode) t sclkw L/R input (SLAVE mode) t lrdss t dss SDATA MSB MSB-1 MSB-2 SCLK to L/R & SDATA - SLAVE mode, FSYNC high t sfs1 t sfs2 SCLK input (SLAVE mode) FSYNC input (SLAVE mode) SDATA MSB MSB-1 MSB-2 FSYNC to SCLK - SLAVE Mode, FSYNC Controlled. DS23F1 3-43
Page 1 and 2: Semiconductor Corporation 16-Bit, S
Page 3: CS5336, CS5338, CS5339 DIGITAL FILT
Page 7 and 8: CS5336, CS5338, CS5339 GENERAL DESC
Page 9 and 10: CS5336, CS5338, CS5339 * L/ R Input
Page 11 and 12: CS5336, CS5338, CS5339 greater than
Page 13 and 14: CS5336, CS5338, CS5339 Signal Ampli
Page 15 and 16: CS5336, CS5338, CS5339 Magnitude (d
Page 17 and 18: CS5336, CS5338, CS5339 ZEROL, ZEROR
Page 19 and 20: CS5336, CS5338, CS5339 L/R - Left/R
Page 21: CS5336, CS5338, CS5339 REFERENCES 1

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