HLASM Language Reference

Examples of Coded Machine Instructions
When assembled, the object code for the instruction labeled DELTA1, in
hexadecimal, is:
BF3EA4
where:
BF is the operation code
3 is register R
E is mask M
A is base register B
4 is displacement D from base register B
RSI Format
The operand fields of RSI-format instructions designate two registers and a 16-bit
immediate operand.
┌────────┬────┬────┬─────────────────┐
│Op Code │ R │ R │ I │
└────────┴────┴────┴─────────────────┘
8 12 16 31
Symbols used to represent registers (See REG1 below) are assumed to be
equated to absolute values between 0 and 15.
The immediate value is treated as a signed binary integer representing the number
of halfwords to branch relative to the current location.
The branch target may be specified as a label in which case the assembler
calculates the immediate value and performs some checking of the value.
The branch target may also be specified as an absolute value in which case the
assembler issues a warning before it assembles the instruction.
Examples:
ALPHA1 BRXH REG1,REG3,BETA1
BETA1 BRXLE 1,2,ALPHA1
When assembled, the object code for the instruction labeled ALPHA1, in
hexadecimal, is
84132
where:
84 is the operation code
1 is register REG1
3 is register REG3
2 is the immediate data I2
RX Format
The operand fields of RX-format instructions designate one or two registers,
including an index register, and a virtual storage address (coded as an implicit
address or an explicit address), with the following exception:
In BC branching instructions, a 4-bit branching mask (see 7 and TEN in the
instructions labeled LAMBDAn below) with a value between 0 and 15,
replaces the first register specification.
Chapter 4. Machine Instruction Statements 95