HLASM Language Reference

Examples of Coded Machine Instructions
| If an offset is specified it may be specified as a relocatable expression or an
| absolute value. If the offset is specified as a relocatable expression, the assembler
| performs some checking and calculates the immediate value. If the offset is an
| absolute expression the assembler issues warning message ASMA056W.
| Examples:
| ALPHA1 BRAS 14,A-B+C+1 where A, B and C are external symbols
| ALPHA2 BRASL 14,A-B+C+1
| BETA1 BRC 15,A-B+C+1
| When assembled, the object code for the instruction labeled BETA1, in
| hexadecimal, is
| A7F45
| where:
| A7.4 is the operation code
| F is the condition code
| 5 is the immediate data I2; a value of 5 decimal.
| In addition GOFF Relocation Dictionary Data Items are generated for the external
| symbols A, B and C.
RR Format
The operand fields of RR-format instructions designate two registers, with the
following exceptions:
In BCR branching instructions, when a 4-bit branching mask replaces the first
register specification (see 8 in the instruction labeled GAMMA1 below)
In SVC instructions, where an immediate value (between 0 and 255) replaces
both registers (see 2 in the instruction labeled DELTA1 below)
┌────────┬────┬────┐
│Op Code │ R │ R │
└────────┴────┴────┘
8 12 15
Symbols used to represent registers in RR-format instructions (see INDEX and REG2
in the instruction labeled ALPHA2 below) are assumed to be equated to absolute
values between 0 and 15.
Symbols used to represent immediate values in SVC instructions (see TEN in the
instruction labeled DELTA2 below) are assumed to be equated to absolute values
between 0 and 255.
Examples:
ALPHA1 LR 1,2
ALPHA2 LR INDEX,REG2
GAMMA1 BCR 8,12
DELTA1 SVC 2
DELTA2 SVC TEN
When assembled, the object code of the instruction labeled ALPHA1, in
hexadecimal, is:
1812
Chapter 4. Machine Instruction Statements 93