HLASM Language Reference
HLASM Language Reference HLASM Language Reference
Examples of Coded Machine Instructions For most, the immediate value is treated as a signed binary integer (a value between −32768 and +32767). This value may be specified using self-defining terms or equated symbols. ┌────────┬────┬────┬─────────────────┐ │Op Code │ R │OpCd│ I │ └────────┴────┴────┴─────────────────┘ 8 12 16 31 For logical instructions such as TMH, the immediate field is a 16 bit mask. ┌────────┬────┬────┬─────────────────┐ │Op Code │ M │OpCd│ I │ └────────┴────┴────┴─────────────────┘ 8 12 16 31 Examples: ALPHA1 AHI REG1,2 ALPHA2 MHI 3,1234 BETA1 TMH 7,X'81' When assembled, the object code for the instruction labeled BETA1, in hexadecimal, is A7781 where: A7. is the operation code 7 is register R 81 is the immediate data I2 For branching RI-format instructions, the immediate value is treated as a signed binary integer representing the number of halfwords to branch relative to the current location. The branch target may be specified as a relocatable expression, in which case the assembler performs some checking, and calculates the immediate value. The branch target may also be specified as an absolute value in which case the assembler issues a warning before it assembles the instruction. Examples: ALPHA1 BRAS 1,BETA1 ALPHA2 BRC 3,ALPHA1 BETA1 BRCT 7,ALPHA1 When assembled, the object code for the instruction labeled BETA1, in hexadecimal, is A776FFFC where: A7.6 is the operation code 7 is register R FFFC is the immediate data I2; a value of −4 decimal | If the GOFF assembler option is active, then it is possible to specify the target | address as one or more external symbols (with or without offsets). 92 HLASM V1R5 Language Reference
Examples of Coded Machine Instructions | If an offset is specified it may be specified as a relocatable expression or an | absolute value. If the offset is specified as a relocatable expression, the assembler | performs some checking and calculates the immediate value. If the offset is an | absolute expression the assembler issues warning message ASMA056W. | Examples: | ALPHA1 BRAS 14,A-B+C+1 where A, B and C are external symbols | ALPHA2 BRASL 14,A-B+C+1 | BETA1 BRC 15,A-B+C+1 | When assembled, the object code for the instruction labeled BETA1, in | hexadecimal, is | A7F45 | where: | A7.4 is the operation code | F is the condition code | 5 is the immediate data I2; a value of 5 decimal. | In addition GOFF Relocation Dictionary Data Items are generated for the external | symbols A, B and C. RR Format The operand fields of RR-format instructions designate two registers, with the following exceptions: In BCR branching instructions, when a 4-bit branching mask replaces the first register specification (see 8 in the instruction labeled GAMMA1 below) In SVC instructions, where an immediate value (between 0 and 255) replaces both registers (see 2 in the instruction labeled DELTA1 below) ┌────────┬────┬────┐ │Op Code │ R │ R │ └────────┴────┴────┘ 8 12 15 Symbols used to represent registers in RR-format instructions (see INDEX and REG2 in the instruction labeled ALPHA2 below) are assumed to be equated to absolute values between 0 and 15. Symbols used to represent immediate values in SVC instructions (see TEN in the instruction labeled DELTA2 below) are assumed to be equated to absolute values between 0 and 255. Examples: ALPHA1 LR 1,2 ALPHA2 LR INDEX,REG2 GAMMA1 BCR 8,12 DELTA1 SVC 2 DELTA2 SVC TEN When assembled, the object code of the instruction labeled ALPHA1, in hexadecimal, is: 1812 Chapter 4. Machine Instruction Statements 93
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Examples of Coded Machine Instructions<br />
For most, the immediate value is treated as a signed binary integer (a value<br />
between −32768 and +32767). This value may be specified using self-defining<br />
terms or equated symbols.<br />
┌────────┬────┬────┬─────────────────┐<br />
│Op Code │ R │OpCd│ I │<br />
└────────┴────┴────┴─────────────────┘<br />
8 12 16 31<br />
For logical instructions such as TMH, the immediate field is a 16 bit mask.<br />
┌────────┬────┬────┬─────────────────┐<br />
│Op Code │ M │OpCd│ I │<br />
└────────┴────┴────┴─────────────────┘<br />
8 12 16 31<br />
Examples:<br />
ALPHA1 AHI REG1,2<br />
ALPHA2 MHI 3,1234<br />
BETA1 TMH 7,X'81'<br />
When assembled, the object code for the instruction labeled BETA1, in<br />
hexadecimal, is<br />
A7781<br />
where:<br />
A7. is the operation code<br />
7 is register R<br />
81 is the immediate data I2<br />
For branching RI-format instructions, the immediate value is treated as a signed<br />
binary integer representing the number of halfwords to branch relative to the current<br />
location.<br />
The branch target may be specified as a relocatable expression, in which case the<br />
assembler performs some checking, and calculates the immediate value.<br />
The branch target may also be specified as an absolute value in which case the<br />
assembler issues a warning before it assembles the instruction.<br />
Examples:<br />
ALPHA1 BRAS 1,BETA1<br />
ALPHA2 BRC 3,ALPHA1<br />
BETA1 BRCT 7,ALPHA1<br />
When assembled, the object code for the instruction labeled BETA1, in<br />
hexadecimal, is<br />
A776FFFC<br />
where:<br />
A7.6 is the operation code<br />
7 is register R<br />
FFFC is the immediate data I2; a value of −4 decimal<br />
| If the GOFF assembler option is active, then it is possible to specify the target<br />
| address as one or more external symbols (with or without offsets).<br />
92 <strong>HLASM</strong> V1R5 <strong>Language</strong> <strong>Reference</strong>