Chip Scale Review - July 2008

July 2008 

• Photolithography for WLP 

• Wafer Bumping

Visit us at SEMICON West, Booth 7834

CONTENTS 

July 2008 

Volume 12, Number 5 

The International Magazine of Chip-Scale Electronics, Flip-Chip Technology, 

Optoelectronics Interconnection and Wafer-Level Packaging 

THE COVER 

In July, some days are quite memorable: July 4, 

America’s Independence Day; the first use of fingerprints 

for identification in July 1858; and Amelia Earhart’s 111th 

birthday on July 24 (Happy Birthday to you, Amelia!). 

Other events are both memorable and inevitable: 

I’m referring, of course, to SEMICON West! 

Although it’s only June as we write this, we’re already 

tingling with excitement over the arrival of SEMICON 

West as the dog days of summer begin. We’ve almost gotten 

used to the trek to San Francisco from San Jose. 

(Almost, but not quite, since we’re still trying to figure out 

the traffic patterns amid the one-way streets.) 

Like Dorothy in Oz, however, we still wish that we could 

somehow click our heels and be transported back to days of 

yore when SEMICON West was in the Magic Kingdom of the 

San Mateo County Fairgrounds. Sure, we sweated in those 

humongous portable gray structures in the backlot as the 

July sun boiled outside. But it was a mystical time for us and 

for the semiconductor industry. A time of inspired youth: 

we and the industry; a time we will, sadly, never recapture. 

But enough nostalgia and on to the present. We’re presenting 

several vital topics in this, our largest issue of the year. 

Terry Thompson presents his annual look at wafer bumping. 

Who knew a decade ago that “bumping” would have 

become an essential part of the industry’s vocabulary Not 

us—or we would have trademarked it! Bumping is now 

beyond mainstream and a significant profit center for 

equipment and materials makers. 

FEATURE ARTICLES 

Wafer-Bumping Services: What’s the 32 

Best Yardstick for Vendor Selection 

Terrence E. Thompson, Senior Editor 

Wafer bumping volume has built dramatically over the past few years 

and has become commonplace. A decade ago, you could select from a 

handful of providers; today, you have dozens. This article will help you 

select possible candidates for your bumped wafers. 

WLP Photolithography: The Tool Makers Tell 42 

You Why Their Machine Is the Right Choice 

Ron Iscoff, Editor 

Which tool for wafer-level packaging lithography is best We ask 

(and partially answer) that question nearly every year at this time. 

This year, we ask the tool makers themselves to give it their best shot. 

International Directory of Lithography Tools 

for Wafer-Level Packaging 

Chip Scale Review Staff 

48 

Driven by ‘Smartphones,’ Package-on-Package 51 

Adoption and Technology Are Ready to Soar 

Lee Smith, Amkor Technology Inc. 

As an enabling technology, package-on-package greatly expands 

device options by simplifying the business logistics of stacking and 

helps manage the cost impacts that derive from consumers’ increasing 

demands for multimedia processing and more memory. 

CONTINUED >> 

Wafer-level photolithography ties rather nicely with wafer 

bumping. This time around we’re letting the principal WLP 

lithography tool makers have their say. Which, if history 

is any indication, it will be a contentious contest for 

who gets whose tool at a facility. 

We’ll see you in ‘Frisco. (They say, “Don’t call it ‘Frisco,’ but 

I was born there and I’m also in charge of filling this space 

and I can do what I want!) Enjoy the Big Show. 

(Illustration for Chip Scale Review by 

Design 2 Market) [design2marketinc.com] 

Chip Scale Review, at 7291 Coronado Dr., Suite 8, San Jose, CA 95129 

(ISSN 1526-1344), is published eight times a year, with issues in 

January-February, March, April, May-June, July, August-September, 

October and November-December. 

Periodical postage paid at San Jose, Calif., and additional offices. 

POSTMASTER: Send address changes to Chip Scale Review magazine, 

7291 Coronado Dr., Suite 8, San Jose, CA 95129. 

Chip Scale Review ■ July 2008 ■ [ChipScaleReview.com] 1

IC Assembly and Test 

Done Right and On Time 

Right: Expect high yields with the latest technology available. 

Above: The Signetics Paju, Korea, manufacturing facility 

Signetics has been exceeding customer expectations with 

on-time, cost-effective packaging solutions for 42 years! 

Since 1966, Signetics has been 

delivering assembly, packaging and 

test solutions that meet and exceed 

our customers’ requirements. 

From low-k 65nm wafers to stacked 

die and thermally enhanced packages, 

our expertise will help you stay at 

the leading edge. 

We’re especially proud of our capabilities in the 

assembly and test of logic and mixed-signal devices. 

Signetics is your BGA specialist! 

We’d like to demonstrate our proficiency 

in plastic packages—whether 

for ASIC, FPGA, memory or DSP applications. 

Please visit our web site at 

www.signetics.com to see our full 

line of QFP, FBGA/LGA, stacked die 

CSPs, PBGA, EPBGA and leadframe packages. 

Put us to the test! Contact your nearest Signetics 

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Contact: B.S. Yoon 

bsyoon@signetics.com 

Signetics High Technology Inc. 

200 Brown Road, Suite 300 

Fremont, CA 94539 

Tel: 408-907-0121 

Contact: Mike Stokman 

mstokman@signetics.com 

UNITED STATES 

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Contact: Christopher Zumba 

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CONTENTS 

FEATURE ARTICLES 

Case Study: Building a Two-Chip Stacked Package 58 

Fred Haring, John Jacobson, Chris Hoffarth, 

Syed Sajid Ahmad and Aaron Reinholz, NDSU 

Engineering a single package housing multiple 

chips stacked vertically one above the other is a 

common practice that results in smaller and more 

efficient packages for devices. This article describes 

a case history and the challenges faced in the 

design and manufacture of the package. 

International Directory of Wafer-Bumping Services 

Chip Scale Review Staff 

69 

Conventional IC Testing Can’t Keep Up with 75 

Today’s System-on-a-Chip Requirements 

Anthony Lum, Advantest America Inc. 

There’s only one way to meet the exploding demand for system-on-a-chip 

(SoC) testing, and that is by dramatically increasing throughput. In addition, 

packaging and test challenges were once 

considered from the vantage point of 

independent solutions, each addressing 

a unique problem set without reference to 

the other. We can no longer afford to be 

myopic regarding our test requirements. 

DEPARTMENTS 

Publishers’ Page Terrence E. Thompson 

Assembly Lines Ron Iscoff 

Test Patterns Paul M. Sakamoto 

Industry News 

Standards Mark S. Bird 

Product Showcase (Advertisement) 

My View Dave Loaney 

Industry Events 

Advertorial Section 

Socketology Mike Fedde 

What’s New! 

Inside Patents A. Jason Mirabito and Carol Peters 

Ad Index/More News/Sales Offices 

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PUBLISHERS’ PAGE 

SEMICON West Redux: 

Please Do Spare the Energy! 

By Terrence E. Thompson, Co-Publisher and Senior Editor 

[tethompson@aol.com] 

Once again it’s show time for the semiconductor industry’s largest U.S. trade 

show: SEMICON West 2008 [semi.org]. From July 14-18, 2008, exhibits, programs 

and visitors will dominate San Francisco’s Moscone Center and environs. 

Exhibits run July 15-17, and the focus of Chip Scale Review’s ongoing editorial coverage, 

test, assembly and packaging (TAP), will be located in West Hall levels 1 and 2. 

CSR’s booth is 7254 in the West Hall, Level 1. Please stop by and say hello. 

What do we know at press time TAP certainly is not alone this year in West Hall. 

SEMI has added a solar/photovoltaic (PV) show-in-a-show this year that will occupy 

much of the formerly barren third floor of the West building. Once again, SEMI organizers 

are looking at new markets in which SEMI members and show attendees can apply 

their IP and manufacturing skills to broaden customer bases and increase profitability. 

PV is part of SEMI’s expanded emphasis on nano-electronics applications and manufacturing 

which also includes: 

• Micro-electromechanical systems and microsystems (MEMS/MST) applications and 

manufacturing; 

• Energy technologies applications and manufacturing; 

• Fuel cells 

Major Change 

It certainly is a year of major change with sky-high energy costs forcing everyone to 

rethink what makes sense in the future. True, chipmakers and laboratories around the 

6 

Continued on page 30 >> 

Add JCET to Your IC Packaging Foundry List 

We inadvertently failed to list Jiangsu Changjiang Electronics Technology Co. 

(JCET), China, in our April-May listing of packaging foundries. 

Jiangsu Changjiang Electronics 

Technology Co. (JCET), division of Xinchao 

Group, 275 Binjiang Middle Rd., Jiangyin City, 

Jiangsu Province, China 214431 

Phone: +86.510.8685.4189 

Fax: +86.510.8685.4550 

Chairman and CEO: Xinchao Wang 

President: Xiekang Yu 

Founded: 1972 

Web URL: www.cj-elec.com 

Contact for more info: Dr. Bill Li, 

General Manager, North American Operations, 

bli@jcet-us.com Phone: 510.573.3612 

U.S. Office: JCET North America, 

41341 Joyce Ave., Fremont, CA 94539 

Chip Scale Review ■ July 2008 ■ [ChipScaleReview.com] 

Stock Symbol: Shanghai Stock Exchange, 600584 

Revenue CY 2007 (USD): $330 million 

Revenue CY 2006 (USD): $240 million 

Number of employees: 7,000 

Customers by region: China, 100 percent 

Packaging materials used: Plastic 

Wafer bumping: Yes, plating and ball drop 

Flip-Chip: Yes RFID: Yes MEMS: Yes 

Total manufacturing area in square meters: 120,000 

Total facilities: 5, all in Jiangsu City 

X-ray inspection offered: Yes 

Test offered: analog/mixed signal, fine leak, 

gross leak, logic, memory, opens/shorts, RF 

Quality audits: ISO9001, ISO14000 

Highest volume package family assembled 

in 2007: SOT/SOD 2006: Same 

VOLUME 12, NUMBER 5 

The International Magazine of Chip-Scale 

Electronics, Flip-Chip Technology, Optoelectronic 

Interconnection and Wafer-Level Packaging 

STAFF 

Gene Selven Publisher Emeritus, Special Projects Director 

7291 Coronado Dr., Ste. 8, San Jose, CA 95129 

b 408.996.7016 > 408.996.7871 

gselven@aol.com 

Kim Newman Co-Publisher/Sales Manager 


b 408.996.7016 > 408.996.7871 

csradv@aol.com 

Terrence Thompson Co-Publisher/Senior Editor 

2303 Randall Rd. #140, Carpentersville, IL 60110 

b 847.515.1255 

tethompson@aol.com 

Ron Iscoff Editor & Associate Publisher 

929 Ebbetts Ave., Manteca, CA 95337 

b 209.824.1289 > 209.644.7747 

chipscale@gmail.com 

Steve Berry Contributing Editor 

b 408.369.7000 > 408.369.8021 

saberry@electronictrendpubs.com 

Dr. Tom Di Stefano Contributing Editor 

b 408.321.8201 > 408.321.8701 

tom@centipedesystems.com 

Dr. Subash Khadpe Contributing Editor 

skhadpe@semitech.com 

Harvey S. Miller Contributing Editor-at-Large 

b 650.328.4550 > 650.327.2360 

h.miller@ieee.org 

Paul M. Sakamoto Contributing Editor–Test 

b 925.924.9110 x148 

paul.sakamoto@inovys.com 

Sandra Winkler Contributing Editor 

b 408.369.7000 > 408.369.8021 

slwinkler@electronictrendpubs.com 

The Official Publication of the WLCSP Forum 

SUBSCRIPTION INQUIRIES 

Judy Levin Chip Scale Review 


b 408.996.7016 > 408.996.7871 

csrsubs@chipscalereview.com 

ADVERTISING PRODUCTION 

INQUIRIES AND REPRINTS 

Kim Newman 


b 408.996.7016 > 408.996.7871 


ADVISORS 

Mark DiOrio MTBSolutions 

Dr. Tom Di Stefano Centipede Systems 

Charles R. Harper Technology Seminars Inc. 

Nick Langston Ardent Concepts Inc. 

Dr. Guna Selvaduray San Jose State University 

Dr. Thorsten Teutsch Pac Tech USA 

Dr. David Tuckerman Tessera Technologies 

Professor C.P. Wong Georgia Tech 

Copyright © 2008 by Gene Selven & Associates Inc. 

Chip Scale Review (ISSN 1526-1344) is a registered trademark 

of Gene Selven & Associates Inc. Publishing headquarters are 

located at 7291 Coronado Drive, Suite 8, San Jose, CA 95129. 

All rights reserved. 

Chip Scale Review is published eight times a year. 

Subscriptions in the U.S. are available without charge to 

qualified individuals in the electronics industry. Subscriptions 

outside the U.S. (eight issues) by airmail are $60 per year to 

Canada or $60 to other countries. In the U.S., subscriptions 

by first class mail are $40 per year.

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ASSEMBLY LINES 

Dealing with the Information Glut Era 

and a Few Other Worrisome Matters 

By Ron Iscoff, Editor [chipscale@gmail.com] 

Remember when your mother 

urged you (while you tried to 

hide that unfinished mass of 

spinach or beets), “Now finish your 

plate! There are children starving in 

Whatsanamia (or Brazinque or 

Tachydermyville”). 

Now, Finish Your Plate! 

I never figured out how eating a vegetable 

that didn’t appeal to me would 

help solve the plight of those starving 

children, but at least it’s now possible to 

really “finish your plate!” An ecologically 

motivated company in Taiwan has developed 

a plate made from wheat flour. The 

purpose, of course, is to consume it! 

You probably think of Taiwan as the 

home of the two largest wafer foundries, 

TSMC and UMC. While surfing the 

web recently, I learned that a group of 

clever Taiwanese student-researchers 

recently met a government-issued challenge 

to develop a product that can be 

used as both a mouthwash and a dishwashing 

soap. 

No question that the Internet provides 

an amazing entrée to the world of 

information. The problem is how to 

digest all of it—or at least that small 

portion that interests you. The Internet 

has not only opened an unlimited treasure 

box of data, it has also led us into 

the Information Glut Era. 

What we really need now is not more 


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Continued from page 9 >> 

information, but a thing to handle it. 

I’m thinking of an avatar or doppelganger 

(double walker) that can take 

over this chore. No doubt an AI lab 

somewhere is on top of this right now! 

Google’s Noble Library Project 

One of the most successful companies 

of the Information Glut Era is arguably 

Silicon Valley-based Google, the dominant 

search engine. The company’s two 

founders are multi-billionaires—not at 

Bill Gates’ level, yet—but only a few 

steps away. 

In December 2004, Google 

announced it would include in its 

search database the full text of books 

from five of the world’s largest research 

libraries and “snippets” from books covered 

by copyright. This is a massive job, 

and one that is now underway. 

Oxford, Harvard, Stanford, the 

University of Michigan and the New 

York Public Library are the participants. 

And while you may think this noble 

project would not be controversial, I’m 

afraid you would be wrong. 

The main controversy, which has also 

sparked several lawsuits, deals with fair 

use of copyrighted works. Many publishers, 

including McGraw-Hill, say they 

want a bite of Google’s “snippet” pie. 

When the project is completed, users 

will be able to scan the complete text of 

all public domain materials—and there 

are millions. For books covered by 

copyright, only a few sentences, under 

what’s known as the “Fair Use Doctrine” 

will be available. 

Good deal, right Well, maybe! 

The Google Boys, Larry Page (left) and Sergey Brin, 

are the fifth richest people in the world. (Google) 

Remember the old saw, “There is no 

free lunch” Google, which has an 

employee cafeteria at its headquarters 

said to rival many fine restaurants, 

remembers, and you are probably going 

to find ads on or with full-text public 

domain books. In other words, you 


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TEST PATTERNS 

Choices: Used Versus New Test Engineers 

By Paul M. Sakamoto, Contributing Editor–Test [paul_sakamoto@comcast.net] 

In my last column, I dispensed 

some advice on buying used test 

equipment. This time we’ll venture 

further into recession countermeasures 

by examining “how to buy 

used test engineers.” 

Test engineers (TEs) are the folks that 

make the programs and design the 

interface hardware for your ATE. 

There are a number of sources for 

these skilled men and women, as there 

are for other engineering disciplines. As 

in most marketplaces, the prime sources 

come down to the broad categories of 

“new” and “used.” 

These can be roughly translated into 

NCG (new college graduate) and VET 

(Very Experienced in Test). Some may 

argue that there are a lot of other 

shades, but these are the big ones today. 

Acquiring Talent 

Now, I will assume you all think you 

know when and how to acquire your 

own NCG talent. To review, you get 

NCGs when you work in a larger company 

that has an HR department, and 

you have a year to break them in. 

You understand that if you are going 

to make the NCG a TE, you are going to 

have to sell the candidate on that idea 

after a lot of explanation. This is stuff 

that doesn’t show up in 99 percent of 

engineering schools. After all this, you 

spend a year training them and hope 

for the best. 

12 

Chip Scale Review ■ July 2008 ■ [ChipScaleReview.com]

What you will likely end up with is 

someone who views the program and 

the computer screen of their workstation 

as reality, and the hardware, tester and 

chip as an abstraction. 

The NCG may or may not even know 

how to use an oscilloscope. As a plus, 

the NCG will quickly understand and 

interface well with the EDA infrastructure 

at your company and will believe in 

simulations. As an added bonus, they 

can explain cell phone text messaging to 

you, so you can deal with intercepted 

messages to and from your kids. 

Another Story 

The VETs are another story. There are 

many routes for our VETs to have 

arrived at their current status. Many 

used to be NCGs and just stayed in test 

after their indoctrination. Others were 

Do you see your next NCG test engineer in this newly minted group 

technicians and maintenance personnel 

who had a bent for electronics and programming. 

Still others have come from 

the military (real vets), aerospace, consumer 

electronics, you name it. 

The TE skill requirements from the 70s 

through the 90s principally centered on 


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INDUSTRY NEWS 

New Ph.D. Says GaN Transistors Could Replace Silicon 

Troy, N.Y.—Is the future dim for 

silicon to continue as the dominant 

material for semiconductors 

A newly minted Ph. D. at the 

Renssalaer Polytechnic Institute 

believes it may be. 

Even before Dr. Weixiao Huang 

received his doctorate from RPI, his 

new transistor captured the attention 

of some of the biggest American 

and Japanese automobile companies, 

according to the university. 

The 2008 graduate’s invention, 

says RPI, could replace the silicon 

transistor for high-power and 

high-temperature electronics. 

Dr. Weixiao Huang invented a GaN MOSFET that 

may replace silicon in high-power applications. 

Unisem’s Guilmart Resigns 

to ‘Pursue Other Interests’ 

Kuala Lumpur, 

Malaysia—Bruno 

Guilmart, 48, Unisem 

group’s chief executive 

officer and executive 

director, resigned in 

early June to “pursue 

other interests.” 

Bruno Guilmart C. H. Ang, Unisem 

group’s chief operating 

officer has taken over Guilmart’s tasks. 

According to the company’s official press 

release, Ang, 57, “will be leading Unisem moving 

forward. Unisem does not anticipate 


Humble Roots 

Dr. Huang, who comes from humble 

roots as the son of farmers in rural 

China, is the inventor of a new transistor 

that uses the compound material 

gallium nitride (GaN), which has 

remarkable material properties. 

The new GaN transistor could 

reduce the power consumption and 

improve the efficiency of power 

electronic systems in everything 

from motor drives and hybrid vehicles 

to home appliances and defense 

equipment. 

“Silicon has been the workhorse in 

the semiconductor industry for last 

two decades,” Dr. Huang observes. 


Intel, Samsung, TSMC Agree 

on 450mm Wafer Pilot Line 

San Jose—The two largest producers of 

semiconductor memory and the largest 

wafer foundry have agreed to collaborate 

on the transition to the next large wafer 

size, 450mm (18 inches) in diameter. 

Intel Corp., the memory leader, and 

Samsung Electronics, the second largest 

memory provider, with foundry Taiwan 

Semiconductor Manufacturing Co. (TSMC) 

have set a 2012 date for the larger wafers. 

SEMICON West Sojourners 

Thousands of interested industry folk will make the trip to Moscone Center to visit SEMICON West 

again this year. West Hall, in background, home of assembly, packaging and test, will be their 

destination. (Chip Scale Review) 

An Intel technician examines a 300mm wafer for 

defects. In 2012, the task will be literally and physically 

larger as 450mm wafers go online. (Intel Corp.) 


INSIDE NEWS 

• University Researchers: Quantum Computers 

May Become Practical page 96 


INDUSTRY NEWS 

Unisem Continued from page 11 >> 

any additional 

changes to the 

group’s organizational 

structure, nor 

will there be any disruptions 

to Unisem’s 

daily operations.” 

Guilmart, a 

C.H. Ang Parisian with master’s 

degrees in electronics 

and business, joined the company in 

November 2003, when it operated as 

Advanced Interconnect Technologies, 

headquartered in Batam, Indonesia. 

He replaced AIT founder Ralph 

Duceour, who founded the company as 

Advanced Microtronics Technology in 

1991. Duceour was also a founder of 

ASAT, Hong Kong. 

Earlier, Guilmart served as senior vice 

president of worldwide sales for Singaporebased 

Chartered Semiconductor, the world’s 

third largest wafer foundry. 

In October 1999, Hana Technologies 

Ltd., Hong Kong, a subsidiary of Thailand’s 

Hana Semiconductor; and AMT merged 

into AIT. At the time, the combined companies 

earned an estimated $300 million 

between the Batam and Hong Kong plants. 

About three years later, AIT closed its 

Hong Kong IC assembly and test facility. 

‘Crippled by Price Erosion’ 

“The phased closure of the Hong Kong 

facility comes in response to a particularly 

difficult array packaging sector that has 

been crippled by severe price erosion 

and ongoing overcapacity, coupled with 

low customer- and end-user demand,” 

Duceour said at the time. 

In July 2007, AIT was acquired for 

about $70 million by Malaysia-based 

Unisem Group. 

The acquisition gave Unisem IC 

assembly facilities in the U.K. (the former 

Atlantic Semiconductor, once ASAT’s 

A sea of bonders occupies the assembly floor at Unisem, 

Batam, the former AIT facility near Singapore. 

European packaging facility); Chengdu, 

China; Ipoh, Malaysia and Batam. 

After the acquisition, Unisem said the 

new Unisem group would boast a workforce 

of 8,800, about 300 test systems 

and 1500 wire bonders. 

The enlarged Unisem said it anticipated 

a combined revenue of $322 million for 

the fiscal year ended Dec. 31, 2006. In its 

2007 annual report, the group reported 

a profit of approximately $23 million 

(MYR 119,612,139). [unisemgroup.com] ■ 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16 


INDUSTRY NEWS 

PEOPLE IN THE NEWS 

‘Different Opinions’ Lead to Resignation of Infineon Chief 

Neibiberg, Germany—“Different opinions 

on the future strategic orientation of the 

company” have led to the resignation of 

Dr. Wolfgang Ziebart, 58, Infineon’s president 

and CEO. 

Peter Bauer,member 

of the semiconductor 

company’s 

management board, 

has been moved into 

the CEO post. 

During a late May 

board meeting, 

Peter Bauer according to an 

announcement from 

Infineon, the supervisory board “unanimously 

declared its vote of confidence 

for Chairman Max Dietrich Kley.” 

Dr. Ziebert became CEO four years 

ago. During his tenure, he formed a 

separate company, Qimonda, from the 

company’s memory business. 

With Dr. Ziebart’s departure, the 

management and supervisory boards 

said they will begin a new companywide 

program, IFX 10-Plus, which comprises 

three key points: margin 

improvement through consistent portfolio 

management; margin improvement 

through a strong cost-cutting in 

manufacturing; and margin improvement 

through increased organizational 

efficiency. 

Bauer, the new CEO, holds an engineering 

degree from the Technical 

University of Munich and began his 

professional career in the semiconductor 

division of Siemens AG. 

He became a member of the Infineon 

board in 1999 and has headed the automotive, 

industrial and multimarket 

business group. 

Hudgens Joins Corwil as 

Military/Aerospace Mgr. 

Milpitas, Calif.— 

Michael Hudgens 

has joined Corwil as 

business development 

manager-military/ 

aerospace from 

Kyocera America. He 

received a bachelor’s 

Michael Hudgens degree in mechanical 

engineering from 

Washington University and an MBA 

from the University of Phoenix. 

He is currently serving as vice president– 

membership for the Florida chapter of 

IMAPS. [corwil.com] 

The company, formerly part of 

Siemens AG, boasts about 43,000 

employees worldwide, including 13,500 

Quimonda employees. [infineon.com] 

18 


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INDUSTRY NEWS 

GaN Transistors Continued from page 15 >> 

“But as power electronics get more sophisticated 

and require higher-performing 

transistors, engineers have been seeking 

an alternative, like gallium nitride-based 

transistors, that can perform better than 

silicon and in extreme conditions.” 

Silicon-Based Electronics 

Each household today likely contains 

dozens of silicon-based electronics. An 

important component of each of those 

electronics is usually a silicon-based 

transistor know as a silicon metal/oxide 

semiconductor field-effect transistor 

(silicon MOSFET). 

The GaN MOSFET could reduce dependence on fossil fuels, says 

Dr. Huang. 

To convert the electric energy to other 

forms as required, the transistor acts as 

a switch, allowing or disallowing the flow 

of current through the device. 

Dr. Huang first developed a new 

process that demonstrates an excellent 

GaN MOS (metal/oxide/GaN) interface. 

Engineers have known that GaN and 

other gallium-based materials have some 

extremely good electrical properties, 

much better than silicon. 

However, no useful GaN MOS transistor 

had been developed. Dr. Huang’s innovation, 

the first GaN MOSFET of its kind in 

the world, has already shown world-record 

performance according to its inventor. 

In addition, Huang has shown that 

his innovation can integrate several 

important electronic functions onto one 

chip like never before. 

“This will significantly simplify entire 

electronic systems,” Dr. Huang said. He 

has also designed and experimentally 

demonstrated several new, novel highvoltage 

MOS-gated FETs, which have 

lower power consumption, smaller chip 

size and higher power density than silicon 

MOSFETs. 

Global Reduction in Fuel Consumption 

The new transistors can greatly reduce 

energy loss, making energy conversion 

more efficient. “If these new GaN transistors 

replaced many existing silicon 

MOSFETs in power electronics systems, 

there would be global 

reduction in fossil fuel consumption 

and pollution,” 

Dr. Huang contends. 

The new GaN transistors 

can also allow the electronics 

system to operate in 

extremely hot, harsh, and 

high-power environments— 

even those that produce 

radiation. “Because it is so 

resilient, the device could 

open up the field of electronic 

engineering in ways 

that were not previously possible due to 

the limitations imposed by less tolerant 

silicon transistors,” he said. 

Dr. Huang has published more than 

15 papers, while a doctoral student in 

the Department of Electrical, Computer, 

and Systems Engineering at Rensselaer. 

Despite obvious difficulties, his parents 

worked tirelessly to give Huang the best 

possible educational opportunities, the 

new Ph. D. reports. 

When school wasn’t enough, Dr. 

Huang’s father woke him up early every 

morning to practice mathematical calculations 

without a calculator, instilling 

in him a lifelong appreciation for basic, 

theoretical mathematics and sciences. 

[news.rpi.edu/] ■ 

20 


INDUSTRY NEWS 

MEMS Expert Added to 

Wednesday A.M. Panel 

San Jose—Dr. Eric 

Mounier, a worldclass 

expert on MEMS, 

has joined the 

International Wafer- 

Level Packaging 

Conference business 

and marketing panel 

Dr. Eric Mounier on Wednesday 

morning at 8:30. 

Dr. Mounier holds a Ph.D. in semiconductors, 

and is a co-founder of Yole 

Développement, a Lyon, France-based 

market research company. In addition 

to his market analysis of advanced packaging 

technologies, he is chief editor of 

Micronews, a monthly Yole publication 

devoted to micro- and nanotechnologies. 

Other panelists at this session are Dr. 

Dan Tracy of SEMI, Jan Vardaman of 

TechSearch International, and Jim Walker 

of the Gartner Group. 

The panel precedes Wednesday’s technical 

presentations and is free to all registrants 

and exhibitors. [iwlpc.org] 

Ruscev Succeeds Khandros 

as FormFactor’s Chief Exec 

Livermore, Calif.— 

FormFactor’s board 

has appointed Mario 

Ruscev, 51, currently 

president, as its next 

CEO, succeeding 

Igor Khandros, 53, 

who founded the 

Mario Ruscev company in 1993. 

Khandros will 

become executive 

chairman of the 

FormFactor board of 

directors, succeeding 

Jim Prestridge, 76, 

its current chairman, 

who will remain on 

Igor Khandros the FormFactor board 

of directors and 

become its lead independent director. 

Chip Cooling System Pipes H 2 O Between Stacks in 3D Packages 

IBM scientists say their new chip cooling method will improve computer performance while reducing the 

energy used to operate. (IBM Corp.) 

Zurich, Switzerland—IBM Labs in 

Zurich, and Berlin’s Fraunhofer Institute 

have jointly developed a prototype that 

integrates a cooling system into 3D 

chips by piping water directly between 

each layer in a chip stack. 

Used in computer chips, IBM says the 

development will advance Moore’s Law 

and “significantly reduce energy consumed 

by data centers.” 

“In order to exploit the potential of 

high-performance 3-D chip stacking, 

we need interlayer cooling,” explains 

Thomas Brunschwiler, project leader at 

IBM’s Zurich Research Lab. “Until now, 

nobody has demonstrated viable solutions 

to this problem. 

“As we package chips on top of each 

other to significantly speed a processor’s 

capability to process data, we have found 

that conventional coolers attached to 

the back of a chip don’t scale.” 

Typical 3D chip stacks would have an 

aggregate heat dissipation of nearly 

1Kw, 10x greater than the heat generated 

by a hotplate, with an area of 4cm 2 

and a thickness of about 1mm. 

Moreover, each layer poses an additional 

barrier to heat removal, IBM says. 

The researchers piped water into 

cooling structures as thin as a human 

hair (50 microns) between the individual 

chip layers to remove heat efficiently at 

the source. 

Because of the superior thermo-physical 

qualities of water, scientists were 

able to demonstrate a cooling performance 

of up to 180W/cm 2 per layer for a 

stack with a typical footprint of 4cm 2 . 

In the IBM experiments, scientists 

piped water through a 1 x 1cm test 

vehicle, which consisted of a cooling 

layer between two dies or heat sources. 

The cooling layer measures only about 

100 microns in height and is packed 

with 10,000 vertical interconnects per 

cm 2 . [ibm.com] 

Phoenix X-Ray Opening New 

West Coast Service Center 

Newark, Calif.—Phoenix X-Ray, acquired 

in October 2007 as part of GE’s Sensing & 

Inspection Technologies business, opened 

a new West Coast demo and customer 

service center here last month. 

The location features a fully equipped 

applications and demo lab with state-of 

the-art 2D and 3D x-ray and CT technology, 

as well as training facilities. [ge.com] 

Check out our digital edition at 

www.chipscalereview-digital.com 


21

INDUSTRY NEWS 

Dow Corning Opens Solar Center to Drive New Aps 

Freeland, Mich.—Dow 

Corning Corp. recently 

opened a $3 million Solar 

Solutions Application 

Center here to collaborate 

with customers in 

the development and 

evaluation of materials 

used to make solar panels. 

The 2,508-square 

meter Center includes a 

laboratory, pilot equipment 

and testing facilities. 

A team of engineers and scientists 

will staff the Center, which has been 

designed to be expanded as needed. 

The Center is the latest in a series of 

solar-related investments by Dow Corning. 

In May 2007, Dow Corning 

announced a major expansion at its 

The Center will develop materials for making solar panels. 

joint venture, Hemlock Semiconductor. 

In September 2006, the company introduced 

a solar-grade silicon, the industry’s 

first commercially available feedstock 

derived from metallurgical silicon using 

a large-scale manufacturing processes. 

[dowcorning.com] 

V-CAPS Gains Vietnamese Investment Certification 

This is the statue of Ho Chi Minh in the city that was formerly known 

as Saigon, but is now named after “Uncle Ho.” 

Hanoi, Vietnam—Vietnam- 

Chipscale Advanced Packaging 

Services (V-CAPS) 

says it has received its investment 

certificate from the 

Vietnamese government 

which recognizes the company 

as a 100% foreignowned 

high tech venture. 

The certificate allows 

V-CAPS to move forward 

with plans to set up a 35,000 

square-meter semiconductor 

assembly and test facility at 

the Hoa Lac Hi-Tech Park (HHTP), 

approximately 30 kilometers outside 

Hanoi in Ha Tay province. 

“We are very excited about completing 

this major milestone 

for V-CAPS,” said 

Harry Rozakis, 

V-CAPS’ CEO/president. 

We have 

known for some 

time that locating in 

Vietnam marks the 

Harry Rozakis next logical progression 

for the semiconductor assembly 

and test business as it migrates across 

the Asia-Pacific region.” 

On completion, V-CAPS says it will 

join Intel in having one of the most 

advanced high-tech manufacturing 

facilities in Vietnam. In addition V-CAPS 

will have one of the cost effective and 

“green” factories in the outsourced semiconductor 

assembly and test market. 

V-CAPS anticipates becoming operational 

before the end of 2009. 

[v-capssemi.com] 

What 

are 

your 

current 

burn-in 

sockets 

missing 


INDUSTRY NEWS 

450mm Wafers Continued from page 15 >> 

The three companies are 

among the top five users of 

wafers for semiconductors 

in the world. 

The companies say they 

will cooperate with the 

semiconductor industry to 

ensure that the “required 

components, infrastructure, 

and capability for a pilot 

wafer line are ready” by the 

target date, although no 

month has been released. 

The transition to larger 

wafers will enable continued 

growth of the semiconductor 

industry, they note, and 

will help maintain a reasonable 

cost structure for future 

integrated circuit manufacturing and 

applications. 

Double Si Surface Area 

The total silicon surface area of a 450mm 

wafer and the number of printed die is 

more than twice that of a 300mm wafer. 

The bigger wafers help lower the production 

cost per chip, the companies 

observe. Additionally, improved efficiency 

lowers the use of energy, water and other 

resources. 

For example, according to the companies’ 

announcement, the conversion from 

200mm wafers to 300mm wafers helped 

reduce aggregate emissions per chip of 

air pollution, global warming gasses and 

water. Further reduction is expected 

with a transition to 450mm wafers. 

Intel, Samsung and TSMC indicate 

that the semiconductor industry can 

San Jose—The adoption of 450mm 

wafers (18 inches) by the semiconductor 

industry—spearheaded by Intel, Samsung 

and TSMC—will bring a Pandora’s box 

filled with new challenges. 

300mm Wafer 

450mm Wafer 

The smaller circle represents a 300mm wafer’s size compared 

proportionately to the forthcoming 450mm wafer. 

improve its return on investment and 

substantially reduce 450mm research 

and development costs by applying 

aligned standards, rationalizing changes 

from 300mm infrastructure and 

automation, and by working toward a 

common timeline. 

The companies also agree that a 

cooperative approach will help minimize 

risk and transition costs. 

In the past, migration to the next 

larger wafer size traditionally began a 

decade after the last transition. 

For example, the industry began the 

transition to 300mm wafers in 2001, a 

decade after the initial 200mm fabs 

were introduced in 1991. Keeping in 

line with the historical pace of growth, 

Intel, Samsung and TSMC agree that 

2012 is an appropriate target to begin 

the 450mm transition. [intel.com] ■ 

Industry Adoption of Larger Wafers Brings New Questions 

By Ron Iscoff, Editor 

A position paper, Advantages and 

Challenges Associated with the Introduction 

of 450mm Wafers, published by the 

International Technology Roadmap for 


Increased 

Signal 

Speed 

More Power 

Low 

Inductance 

Stable 

Resistance 

Higher 

Temperatures 

Increased 

Stroke 

Replaceable 

Pins 


INDUSTRY NEWS 

Larger Wafers Continued from page 25 >> 

The 

Solution 

Intel Corp., is one of the trio that is pushing for a 2012 timeline for a 450mm wafer. This is a Pentium 

die. (Intel Corp.) 

Semiconductors [itrs.net], says in the 

past, chip makers have not been overly 

concerned about the effect of larger wafer 

sizes on wafer makers. 

“The change to 450mm wafers, however, 

may be significantly different 

because of the magnitude of the financial 

burden placed upon the wafer producers,” 

the ITRS says. 

The case for larger wafers, says the 

ITRS, is an economic one. “At some point 

along the growth curve for chip demand, 

it will become more economical for 

chip makers to build one 450mm chip 

factory than two 300mm chip factories.” 

If historical trends continue, says 

ITRS, silicon wafer consumption will 

reach about 12.5 billion in 2 /year by 

2013—presuming a “robust market 

environment exists at the time.” This 

will represent a doubling of actual silicon 

consumption in slightly under a decade. 

Is Bigger Better 

ITRS says it’s generally conceded that 

larger diameters offer the potential for 

manufacturing more chips/wafer, which 

lowers the cost. This, however, may be 

offset by the increased complexity in 

manufacturing and handling larger 

wafers, as well as the need to implement 

new toolsets. 

We asked a diverse group of about 40 

companies to respond to the forthcoming 

2012 date set by Intel, Samsung and 

TSMC. Only a handful responded. 

The Challenges 

Dr. Andy C. Mackie 

of the Indium Corp. 

[indium.com] says 

the challenge for 

wafer-bumping solder 

paste is with bumpheight 

consistency 

across the wafer, 

Dr. Andy C. Mackie which is affected by 

the rheological stability 

of the wafer-bumping paste. 

“With the increased exposure of the 

paste to air, the lifetime of the solder 

paste will be significantly reduced from 

its current 4-6 hours of working life. 

This is because of the ~50 percent 

increase in the width of paste on the 

squeegee, and the 40-50 percent 

increase in stroke length. 

“However, the means for extending 

the stencil life for these types of solder 

pastes are already known (for example 

EP1001667). For binary alloys, the 

industry will see an increased reliance 

on plating. For ternary and higher 


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INDUSTRY NEWS 


alloys, including ‘doped’ solder alloys, the increased wafer 

size paves the way for cutting-edge wafer-level chip-scale 

packaging processes. 

“These will include wafer-bumping with WLCSP flux and 

microspheres, a process which is now reportedly in massproduction 

at > 

28 


INDUSTRY NEWS 


environment it sees on the probe floor. 

Very High Development Costs 

ITC also notes, “the volume of 450mm 

tools for probe card testing will be low 

and the development costs very high. It 

will be very desirable if not absolutely 

necessary to partner with a major device 

manufacturer with a stake in the success 

of the 450mm conversion.” 

In addition, the cost of these 450mm 

tools will be much higher than present 

300mm units. “Companies must be prepared 

to pay this or they will drive out 

the only suppliers able to provide the 

systems.” [inttechcorp.com] ■ 

ITC 300mm probe card metrology tool 

and number of test channels. 

“Already the probe card PCBs for memory 

test platforms are increasing in size 

to enable the additional probes and test 

channels to be tracked out on the board,” 

says ITC. “A corresponding increase in 

the number of test channels, and therefore 

additional size and complexity, will 

need to be addressed on the probe card 

metrology tool.” 

Mechanically, according to ITC, the 

increase in probe count to a number in 

excess of 100,000 probes will dramatically 

increase the total probe force. The metrology 

tool will need to address this as the 

only true test of probe card planarity is 

to subject it to the same mechanical 

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PUBLISHERS’ PAGE 

SEMICON West Redux Continued from page 6 >> 

world are focusing on faster next-generation 

devices that will use less power and 

minimize waste heat given off during 

operation. 

Is a planet that is increasingly 

dependent on instant global telecommunications 

and computers enough 

though Probably not, but it is a start. 

copy & copyright promex industries 

The industry must really think outside 

the box for ways to keep the industry, 

and everyone who relies upon its innovations, 

to survive and thrive. 

For some reason, SEMICON and 

chipmaking made me recall a book 

review from CSR a few years ago 

(August-September 2006, page 78, 

Enabling our customers 

to take new products to market 

faster than by any other route 

Silicon Valley’s Packaging Foundry 

Tel. 408.496.0222 

24 hour Quick Turns 

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Production 

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Custom Package 

Development & Assembly 

- SiP’s, MEMS, QFN’s 

Molded plastic, ceramic and materialscentric 

custom package development & 

assembly services including SiPs, 

MEMS, MOEMS, MCM and LGAs. 

JEDEC standard and custom QFN/ 

DFNs available. PROMEX is a 

recognized leader in stacked die, thin 

molded, 2D, 3D, SMT and RoHS 

compliant packaging. Same day quick 

turns, development prototyping, “fast 

track” new product introductions and 

beta manufacturing through pre-Asia 

volume production. 

www.promex-ind.com 

“Engineer’s 

Bookcase,” 

Archibald Putt’s 

Putt’s Law and the 

Successful Technocrat: 

How to Win 

in the Information 

Age from Wiley- 

IEEE Press 

[wiley.com].) 

I wondered if Putt’s Law would dominate 

the future IC industry What, 

exactly, is Putt’s Law 

“Technology is dominated by two 

types of people: those who understand 

what they do not manage, and those 

who manage what they do not understand,” 

says the author, Archibald Putt 

(a pseudonym, of course). 

Timely Quote 

This quote is forever timely. In a world 

where technology is abused and misused, 

gathering way too many headlines 

along the way, one hopes that there might 

be an answer or two floating around. 

There is: This book reminds any reader 

who is in the technology business, of 

personal experiences, some of which we 

still try to forget. 

SEMICON West will address some of 

these challenges and stimulate attendees’ 

little gray cells as the fictional 

Hercule Poirot often mentions. 

The SEMICON West exposition this 

year will feature 1,000+ exhibitors— 

including Chip Scale Review. During the 

show, we’ll distribute extra copies of 

CSR to show visitors from our booth, 

7254 in West Hall, Level 1, and from 

racks in Moscone Center’s West Hall. 

As always, please contact me with any 

questions, comments, concerns or suggestions! 

i 

30 


Wafer-Bumping Services: What’s the 

Best Yardstick for Vendor Selection 

How do you measure the performance 

of potential wafer-bumping 

vendors This article will point you 

in the right direction. 

Left: Technicians at i2a Technology 

in Fremont, Calif., prepare to singulate 

bumped wafers. 

Wafer bumping volume has built dramatically over the past few years and 

has become commonplace. A decade ago, you could select from a handful 

of providers; today, you have dozens. This article will help you select 

possible candidates for your bumped wafers. 

By Terrence Thompson, 

Senior Editor 

[tethompson@aol.com] 

I 

s wafer bumping finally moving 

towards dominance Very likely, 

since it is indeed a cost-effective and 

reliable batch process for mass 

production of every IC, MEMS or 

photonic device on a wafer. In some 

applications, individual die are 

bumped, but that is not an affordable 

option for high-volume production. 

32 


Today, bumping is typically placed 

into one of two categories: regular bumping 

or redistribution layer bumping 

(RDL), which shifts wafer pad I/Os to 

patterns that match existing substrates. 

This article will help guide you 

through the labyrinth of wafer bumping. 

It reveals who’s got the “right stuff,” and 

provides a valuable yardstick for use in 

selecting the most suitable bumping 

house the first time out! 

Are Bumps Reliable Enough 

A few years ago, we reviewed bumping 

service providers, but were bothered by 

the nagging question, “Are bumps reliable 

enough” 

With a close look at the well-developed 

bumping infrastructure today, one thing 

is evident: There is no shortage of bumping 

service providers and technologies 

that produce very reliable bumps. The 

bumping infrastructure has matured and 

now offers a wide range of bumping 

options to match 

performance and 

budget targets. 

Another significant 

process has 

entered production 

big time: copper pillar 

bumps. Why the 

excitement Copper 

pillars retain their 

shape during solder 

reflow, allowing 

finer interconnect 

pitches with uniform 

standoff heights, 

with or without solder. 

Many foundries 

that offer wafer solder 

bumping can provide pillar bumping, 

too. 

The Package is the Product! 

At last, the package is finally being recognized 

as the gating process for ICs. 

UBM line for subsequent wafer bumping at Pac Tech USA 

Our friends at SEMI [semi.org] have 

decreed that SEMICON West 2008 will 

focus on what we’ve known for a long 

time: The package is the product! 

SEMI spokesman Tom Morrow says 

that the supply chain focus will soon 


evolve into a much more 

integrated, horizontal 

model supported by the 

long-term goal of updating 

Shibuya’s SBP660 high-throughput 

solder ball mounting system 

with vision alignment is for WLP 

volume production use. 

industry standards. The goal is to more 

fully integrate the wafer fab BEOL 

(back-end-of-line) to facilitate the real 

backend operations, including UBM, 

RDL, bumping and final wafer-level 

packaging. 

TSV, SoC, PiP and PoP 

With the explosive growth of the mobile 

electronics market, and new, more powerful 

microelectronic devices, IC makers 

are increasingly looking toward advances 

in assembly and packaging to solve present 

and emerging challenges in performance, 

productivity, and cost reduction. 

At SEMICON West 2008, the 

TechEXOT “Test Assembly & Packaging” 

on West Hall, Level 1, will address the 

packaging gamut from the current hot 

topics of 3D through-silicon via technology 

(TSV) to SoC, PiP and PoP 

applications and more. 

Solder bumps for flip-chip assembly 

are often deposited by electroplating on 

the I/O pads of the chips. The typical 

basic process steps for wafer bumping 

are sputtering of a seed layer (UBM), 

photolithography patterning a photoresist 

to determine bump size precisely, 

depositing the bump metal alloy; then, 

perhaps etching the seed layer followed 

by reflow to bond the solder and define 

the bump shape. Bumps are commonly 

comprised of Au, Cu, Ni, SnAg, SnCu, 

SnAu and PbSn, although other twoand 

three-metal alloys are used. 

Bumping’s Future 

Dr. Raj Pendse, vice president of flip 

chip and emerging products at STATS 

ChipPAC Ltd., Singapore, [statschippac. 

com] believes that “Wafer bumping 

technology is moving into a new realm. 

“Traditional area-array Sn/Pb solder 

bumps (and their associated interconnection 

to organic substrates) were 

widely adopted in the mid 90’s for 

microprocessors and later by the broader 

industry including fabless players for 

graphics chips and FPGAs. The purpose 

34 


was to address the need for higher I/O 

density and superior power/ground 

management.” 

Copper Pillar Bumps 

Pillar bumping permits cost-effective, 

fine-pitch bumping with very predictable 

stand-off distances for better underfilling 

while improving thermal and electrical 

performances compared to standard 

eutectic or high-lead solder bumps. 

Copper pillars retain their shape during 

solder reflow, allowing finer interconnect 

pitches with uniform stand-off 

heights. 

As pin counts, higher IC operating 

temperatures and interconnection densities 

increase, there is growing interest 

in copper pillar bumps for wafer-level 

packaging, since a need exists to 

increase interconnect performance, as 

well as to reduce interconnect costs. 

Advanpack Solutions Pte., Singapore, 

[advanpack.com] uses its pillar bump 

technology for standard pitches, typically 

a Cu post with a shape that is unaffected 

by subsequent post-reflow when 

capped with solder. Advanpack claims 

distinctive advantages including the Cu 

post’s repeatable stand-off height. In 

addition, the company says the controlled 

solder amount used allows for 

solder-maskless substrates. 

Wafer bumping has become commonplace 

throughout the industry. A technician holds a 

300mm CMOS wafer produced jointly by 

STMicroelectronics and IBM. (IBM Corp.) 

Pillars are suitable for use on bare Cu 

pads; thus, their rigid Cu post sidewalls 

simplify underfilling. Cu posts also permit 

better thermal and electrical performance 

and the post increases the selfattenuation 

distance of alpha particles 

offering better soft-error protection for 

solders containing lead. 

Copper pillar bumps were first used 

Contact Us At: 

CORWIL Technology Corporation 

1635 McCarthy Blvd. 

Milpitas, CA 95035 info@corwil.com 

Tel: 408-321-6404 www.corwil.com 

Fax: 408-321-6407 ISO 9001:2000 Registered 

by Intel Corp. in 2006 for its 65nm 

microprocessors [intel.com].Wafer 

bumping foundries and semiconductor 

manufacturers are evaluating and using 

this technology. 

Amkor Technology [amkor.com] also 

suggests Cu pillar bumps for appropriate 

applications and it is often used with 

TSV wafers. 

CORWIL is the leader in wafer backgrinding, wafer dicing and visual 

inspection to commercial, military and medical specs. CORWIL’s newest 

addition in dicing equipment is a fully automatic, latest state-of-the-art 

12 inch dicing saw that strengthens CORWIL’s technical leadership for 

chip-free and fast turn-around dicing. CORWIL dices Si, GaAs, Sapphire, 

SiGe, laminates and many other materials and CORWIL is unsurpassed 

in IC assembly in ceramic, BGA, flip-chip, and MLF/QFN type packages. 

➢ High Volume — Millions of dice per month 

➢ Automatic High-Speed Pick-and-Place 

➢ Automatic Vision Inspection Systems 

➢ Low K, MEMS and Optical/Imaging wafers processed 

➢ Experts in Multi-die Type Wafer dicing 

➢ Highest Quality and Best Service in the Industry 

Since 1990 CORWIL has built its reputation providing customers with: 

Excellent Quality and Superior Service 

DSCC QML Certification 

MIL-PRF-38535 

MIL-STD-883 


Cool It! 

A thermal copper pillar bump may act 

as a thermoelectric device made from 

the thin-film thermoelectric material 

embedded in flip-chip interconnects 

(the pillars) for use in electronics and 

optoelectronic packaging. 

Thermoelectric cooling (TEC) occurs 

when a current is passed through a Cu 

pillar bump. The thermal bump pulls 

heat from one side of the device and 

transfers it to the other as current is 

passed through the material. This is 

known as the Peltier Effect. 

This 300mm wafer at Taiwan Semiconductor Manufacturing Co. Ltd. will be bumped, a standard practice. 

Options and Tradeoffs 

Cost in wafer bumping is frequently a 

function of what you need. There are many 

options: preformed solder ball/sphere 

placement, stenciled solder paste, electroplating, 

electroless plating, jetted solder, 

physical vapor deposition. Also, stud bumping 

with modified wire bonders or copper 

pillars are common bump options. 

Highest Performance with Proven Reliability 

in BGA, CSP and FBGA Packages 

S.E.R. produces a wide range of IC test sockets, many which offer the advantage of being solderless. Our 

Mini-Probe and double Mini-Probe IC sockets offer superior performance with the highest contact reliability. 

www.serusa.com 

S.E.R. ELECTRONICS U.S.A. 

3478 BUSKIRK AVENUE, SUITE 1020 

PLEASANT HILL, CA 94523 

PHONE: (925) 746-7166 

FAX: (925) 746-7153 

E-mail: mtaira@serusa.com 

S.E.R. CORPORATION 

1-14-8, KITA-SHINAGAWA, SHINAGAWA-KU 

TOKYO, 140-0001 JAPAN 

PHONE: +(81)-3-5796-0330 

FAX: +(81)-3-5796-3210 

www.ser.co.jp E-mail: ser@ser.co.jp 

S.E.R. TAIWAN CORPORATION 

5F No. 9 LANE 126 HSUEH-F ROAD, SEC. 1 

TU-CHENG CITY, TAIPEI HSIEN, TAIWAN 

PHONE: +886-2-2273-8792 

FAX: +886-2-2273-8790 

E-mail: tojanice@ms35.hinet.net 

36 


Where applications require interconnects 

with electrical and thermal characteristics 

superior to solder, gold and 

plated bumps are a better choice. 2 

Wafer bumping with gold ball bumping 

provides performance advantages for 

high-frequency and low pad-pitch 

applications. 

Yet another option is the IBMdeveloped 

C4NP (C4 New Process) ball 

formation and placement method. 

Decades ago, IBM developed the industry 

standard 1 C4 process to which numerous 

bumped packages can trace their 

lineage. 

C4NP does not yet appear to be 

available at bump houses, so this may 

be a do-it-yourself choice if needed 

quickly. C4NP has now moved into 

volume production at IBM, however. 

UBM and RDL 

The wafer’s underbump metallization 

and redistribution layer, if needed, are 

important factors in the process. With 

copper wafer interconnects and pads 

and various high-tin Pb-free solders, a 

different metal alloy coating may be 

needed to avoid chip or board compatibility 

issues including tin whisker formation. 

The bumping vendors will gladly 

share their expertise if you thoroughly 

describe end-use conditions. 

Victor Batinovich, president and CEO 

of I2A Technologies in Fremont, Calif., 

[i2a-tech.com] says, “The greatest benefits 

of WLCSPs are the true chip-size 

product and the low relative cost of 

wafer-level processing. All devices are 

bumped and tested in wafer form and 

later singulated into individual chips. 

Like wafer fabrication, the cost of the 

WLCSP goes down as the wafer size 

increases and as the die sizes shrink.” 

WLP has sets of area array bonding 

pads on the wafer, or forms the sets of 

area array bonding pads by means of 

redistribution (RDL) of the peripheral 

bonding pads of each die in the wafer 

fabrication process. Moreover, the interconnect 

medium on the pad is built in 

various ways to enable direct chip attach. 

The Advocates 

We have certainly seen wafer-bumping 

consortiums and alliances come and go. 

What they share are goals for the future 

of device packaging, especially at the 

Launch your 

new flip-chip 

product in 

record time. 

assembly in BGA, ceramic, plastic, 

QFN, COB and MCM packages. 

In addition to flip-chip capability, 

CORWIL has outstanding wirebonding 

expertise for ultra-fine pitch applications 

in gold and aluminum wire. 

Contact Us At: 


1635 McCarthy Blvd. 

Milpitas, CA 95035 info@corwil.com 

Tel: 408-321-6404 www.corwil.com 

Fax: 408-321-6407 ISO 9001:2000 Registered 

wafer level including bumping with various 

technologies. 

SECAP (Semiconductor Equipment 

Consortium for Advanced Packaging), a 

dedicated group of WLP equipment 

advocates which used mask aligner 

lithography, is no more. 

Its members announced the successful 

completion of SECAP’s goals and 

COMPLEX FLIP-CHIP 

ASSEMBLY WITH 

SAME DAY TURN 

➢ Over 3200 bump/ball IO’s 

➢ Flexible Process Flows 

➢ Wide Material Selection 

➢ Gold Stud Bumping 

➢ Prototypes: as quick as 

8 hours! 

➢ Production: 1000’s of 

units per week 

CORWIL has developed into the premier 

U.S.-based packaging subcontractor with 

world-class wafer thinning, dicing, pick-andplace 

and visual 

inspection, plus 

state-of-the-art IC 

Since 1990 CORWIL has built its reputation providing customers with: 

Excellent Quality and Superior Service 

DSCC QML Certification 

MIL-PRF-38535 

MIL-STD-883 


international EMC3D consortium 

[emc3d]. 

The APiA Advanced Packaging and 

Interconnect Alliance (stepper lithography 

emphasis, unlike SECAP’s aligner 

focus) also wound down in 2005. Both 

were early advocates of advanced wafer 

bumping technologies. 

We also have the recently-formed (2006) 

WLCSP Forum [wlcspforum.org].Its 

goal is to promote the adoption of 

semiconductor devices using wafer level 

CSP (WLCSP), establish industry-sponsored 

best practices for their utilization 

and provide strategies for migration to 

finer pitch WLCSP products. 

Resist coaters and developers, such as this unit at IBM Microelectronics, are used in wafer bumping 

operations. 

disbanded in mid-2005. However, its 

increasingly relevant legacy continues. 

Not surprisingly, many of SECAP’s 

members are now very active in the 

On the Road Again 

The 3D integration of microelectronics 

is fueling the race to develop future 

products. 

Three companies have joined forces 

to promote the transition. They are 

SUSS MicroTec [suss.com],Surface 

38 


Technology Systems (STS) 

[stsystems.com] and NEXX Systems 

[nexxsystems.com] which are collaborating 

with Fraunhofer IZM [izm. 

fraunhofer.de] to demonstrate integrated 

process solutions for 3D wafer level 

packaging [3dintegration.org]. A key 

method for them to deliver their message 

has been technology roadshows. 

These roadshows provide a comprehensive 

overview of new developments 

in the field of TSV etching and filling, 

high aspect-ratio lithography, temporary 

bonding and materials associated 

with these technologies. 

Solder Ball Placement 

Tom Nakamura of Shibuya in Japan 

[shibuya.co.jp] says, “There are several 

options for bumping with ball placement, 

a viable alternative to stencil 

printing or electroplating systems. 

Ball placement is now widely accepted 

in the market and has joined the mainstream 

for spheres larger than 150µm 

with 60µm soon. Ball placement of 120µm 

is also in the mainstream because its 

process advantages including uniform 

bump height, flexibility of solder alloy 

selection, high yields and the bonus that 

solder balls are repairable/replaceable. 

Answers Abound at IWLPC 

The 5th annual International Wafer-Level 

Packaging Conference, with tracks on waferlevel, 

3D, stacked packaging, and chipscale 

devices in San Jose, October 13-16, 

2008, will answer bumping and related 

questions for attendees [iwlpc.org]. 

Sponsored jointly by the SMTA 

[smta.org] and Chip Scale Review magazine, 

the IWLPC explores cutting edge 

topics in wafer-level packaging and 

IC/MEMS/MOEMS packaging, including 

3D/Stacked/CSP/SiP/SoP and mixed 

technology packages. 

Conclusion 

New OEM and consumer electronicscentric 

product ideas pop up faster than 

weeds. The right product substrate and 

bumped chips can dramatically shorten 

your widget’s time to market. 

Wafer-bumping service providers can 

quickly show a wafer or IC’s proof of 

concept and production worthy status. 

If capital equipment costs are a concern, 

the bumping houses already have the 

tools in place to run production volumes 

too, including testing. Some chipmakers 

split bumping among service providers 

and their own in-house production lines. 

As we’ve said before, both business 

and technology trends in wafer bumping 

are being driven by one simple goal: the 

lowest possible cost. Today, low cost 

with high quality is available from many 

bumping vendors. 

Wafer bumping, along with through 

silicon via (TSV) technologies and wafer 

bonding combined with an incredible 

array of 3D stacking approaches will 

change the IC packaging norms in the 

C4NP (C4 New Process) creates prepatterned 

solder balls while a wafer 

is still in front-end manufacturing, 

potentially reducing cycle time significantly. 

Bumps can be inspected 

and deposited onto the wafer in one 

simple step using technology similar 

to wafer-level bonding. 

This process provides the simplicity 

of stenciled/screened solder paste and 

employs pure molten alloy to match 

the finer pitches of electroplating. 

Parallel processing allows increased 

efficiency and advanced quality control 

for wafer bumping. 

C4NP accommodates binary, ternary 

and quaternary alloys. It minimizes 

the costs of consumables, according 

to IBM, since only the solder balls are 

created and transferred to the wafer 

without waste. C4NP is not dependent 

on wafer size, enabling 200mm 

future. Bumping is needed for these 

applications. 

The high-volume bumping foundries 

are expanding their capabilities to offer 

one-stop bumping, grinding, testing, 

dicing, assembly, inspection and tapeand-reel 

packaging. Check out the bumping 

service options in the “International 

Directory Of Wafer-Bumping Service 

Providers,” beginning on page 69. One 

significant bonus not mentioned in the 

guide is support—an area where bumping 

service providers excel! i 

References 

1. Terrence Thompson, “As Wafer Bumping Moves 

to the Mainstream, Cost and Process Reliability 

Questions Remain,” Chip Scale Review, July 2005. 

2. Daniel D. Evans Jr., “How to Choose the Perfect 

Wafer-Bumping Method,” Chip Scale Review, 

July 2005. 

How IBM’s C4NP Process Works 

This side view of the IBM C4NP process shows the 

bump template filling with solder. (IBM Corp.) 

and 300mm wafers to be processed 

with similar efficiency. 

Additionally, C4NP has achieved 

technical capability well beyond the 

ITRS roadmap for packaging technology. 

The first C4NP line was installed 

at the Hudson Valley Research Park 

within IBM’s Microelectronics 

Division packaging operation. 

[ibm.com] 


STANDARDS 

Work in Progress for the Next PoP Generation 

By Mark Bird, Contributing Editor–Standards 

The Package-on-Package (PoP) 

family continues its rapid 

growth. There were over 2.6 

billion 3D packages shipped in 2006, 

and this number is expected to grow to 

4.9 billion by 2011 according to industry 

analysts Prismark Partners 

[prismark.com]. 

The 3D market continues to be driven 

by mobile applications. The technology 

integrates devices or packages in the 

vertical direction to achieve a reduction 

in size and cost of the functional solutions. 

The growth of PoPs is expected to 

increase over 8x by 2011 and to be more 

than 10 percent of the overall 3D packages 

shipped. The driving force behind 

PoP is the need to provide a cost-effective 

format for logic and memory stacking to 

address technical, business and logistics 

requirements. 

PoPs are in mass production and 

being shipped to all major mobile 

phone makers for use in higher-tier 

phones, but will soon migrate to midand 

lower-tier phone applications. 

PoPs are packages are overmolded PC 

board construction with balls on the 

bottom of the packages. The bottom 

package has balls on the bottom and 

lands on the top for the top-package 

mounting. 

The present PoP family has 

10x10mm, 11x11mm, 12x12mm, 

13x13mm, 14x14mm, and 15x15mm 

body sizes with the bottom package 

pitch at 0.50mm. 

Twelve Variations 

The ball diameter for the bottom package 

is a nominal 0.30mm. The bottom 

package ball count ranges from 305 to 

841 depending on the body size. There 

are 12 different variations active, which 

consist of six with a top package pitch 

of 0.65mm and six with a top package 

pitch of 0.50mm. 

The ball diameter for the top package 

is a nominal of 0.35mm for 0.50mm 

pitch and 0.45mm or 0.50mm for 0.65mm 

pitch, depending on the application. 

The ball counts for the top packages 

range from a low of 104 to a high of 

216, depending on the body size and 

pitch. 

An example of the current Package-on-Package 

The new FiPoP 

The details of the specifications can 

be found in JEDEC Publication 95 under 

the standard numbers shown below: 

• The lower and upper PoP Design 

Guide is 4.22 

• Lower PoP Package; Very Thin 

Profile; Square; Stackable Ball Grid 

0.50mm Ball Pitch Array is MO-266 

• Upper PoP package; Low Profile, 

Thin Profile and Very Thin Profile; 

Fine Pitch; Square; 065- and 0.50mm 

Ball Pitch Array Family MO-273 

This family of standards uses a fanout 

style of PoP ball population and will 


40 


WLP Photolithography: The Tool Makers Tell 

You Why Their Machine Is the Right Choice 

Jennifer Chu of IBM holds a Power microprocessor. At right, a 300mm IBM wafer reflects hundreds of microprocessors. Increasingly, photolithography 

methods are being employed in the packages of advanced microprocessors. (IBM Corp.) 

Which tool for wafer-level packaging lithography is best We ask 

(and partially answer) that question nearly every year at this time. This 

year, we ask the tool makers themselves to give it their best shot. 

By Ron Iscoff, Editor 

[chipscale@gmail.com] 

We have printed nearly 

verbatim—except for correcting 

grammar, spelling and so 

forth—responses to our questions 

from the four leading providers of 

photolithography tools for waferlevel 

packaging. 

We told the suppliers they could 

say anything they wished on behalf 

of their specific tools for wafer-level 

packaging and promised to print it 

unedited. 

The only surprise we encountered 

was that most of them supplied 

fewer than the 275 words per company 

we allowed. In the interests of 

balance, we also provide a more dispassionate 

view from Amkor 

Technology Inc., one of the major 

WLP providers. 

42 


EV Group [evgroup.com] 

EVG manufactures full-field contactand 

proximity aligners that enable a 

wide range of processes for wafer-level 

packaging. 

Front-side alignment, backside alignment, 

alignment of wafers bonded to 

transport carriers and alignment of thick 

resist layers (>100µm) are all possible 

with the EVG IQ Aligner for wafers up 

to 300mm. 

The EVG IQ Aligner utilizes the latest 

generation Cognex pattern recognition 

system as well as temperature-controlled 

chucks to control runout, ultimately allowing 

for submicron alignment results to 

be achieved. 

Inline optical or physical wedge error 

compensation (WEC) units are available. 

These inline units feed the WEC 

information forward to the aligner and 

can process 200mm and 300mm wafers 

without hardware configuration changes. 

The end result is that the photoresist 

surface does not need to contact 

the photomask for WEC, which 

increases mask life as well as 

the system throughput. 

The IQ Aligner is designed to 

handle 200mm to 300mm wafers 

automatically for all alignment 

modes with minimal crossover 

time between wafer sizes. 

The system can be configured 

with 1000W or 5000W 

lamps to minimize exposure 

times and maximize throughput. 

High uptime and low costof-ownership, 

combined with process 

flexibility, make the EVG IQ Aligner the 

system of choice for all wafer-level 

packaging applications. 

–Garrett Oakes, application engineer 

SUSS [suss.com] 

There’s a very simple reason why 

foundries and IDMs the world over are 

selecting SUSS proximity aligners for 

EV Group uses proximity alignment technology in its IQ 

Aligner systems. 

WLP: We meet the requirements at lower 

cost. That answer has several elements 

to it, so let’s look at each of them. 

The first requirement for WLP always 

involves resolution and overlay; if you 

can’t meet these, you can’t be considered. 

SUSS lithography tools incorporate a 

number of features to optimize the 

overlay, starting with the optics to 

image the mask and wafer targets. 

INTRODUCING 

A New Material Solution for Key 

Microprocessor Test Socket Applications 

Piper Plastics’ ceramic-filled VICTREX ® PEEK grade 

(EPM-2204U-W) offers excellent dimensional stability and 

tolerance control across a broad range of temperature and 

humidity conditions, making it ideal for high performance 

test socket components. Competitive advantages include: 

• Significantly lower moisture absorption 

• Very tight tolerance machining 

• Impact strength, stiffness and minimum creep levels 

• Half the weight of ceramics 

• Greater impact resistance and toughness compared to ceramics 

• Excellent processability and wear performance 

• Good dielectric properties for insulative applications 

• Clean white color 

For more information on ceramic-filled 

VICTREX PEEK-based materials for microprocessor 

test sockets, please visit Piper Plastics and 

Victrex USA at SEMICON West, booth #5415, North Hall. 

For more information contact 

Ryan Close at 

rclose@piperplastics.com 

(800) 526-2960 

www.piperplastics.com 


Meeting the requirements 

with a smaller, faster, flexible 

tool all adds up to one conclusion: 

lower cost of ownership. 

This has made SUSS the litho 

tool of choice for WLP. 

–Keith Cooper, business development 

manager–lithography 

SUSS MicroTec supplies proximity aligners for 

200mm- and 300mm wafers, including the 

MA300Plus (shown) and the MA200. 

We’ve developed innovative methods 

to view mask and wafer simultaneously 

(DirectAlign) plus a method to minimize 

the isometric magnification 

between the two by thermally stabilizing 

them (ThermAlign). Coupled together, 

we can provide a 1µm overlay on 

300mm wafers. 

We even offer a way to align through 

a dark-field mask, a feature critical to 

exposing bumps or contacts. And once 

the alignment is done, even thick resists 

are exposed at a comfortable proximity 

gap with high fidelity due to our highly 

renowned exposure optics. 

The next requirement is the rapid 

processing of your precious wafers at 

their point of maximum value. To 

accomplish this, we employ a fieldproven 

wafer handling system plus a 

high-intensity full-field exposure system, 

all integrated into a footprint which 

might fit several times into another tool’s 

floor space. 

Because the mask is full field, exposure 

of resist edge bead, edge die or even outrigger 

bumps is no problem. Throughput 

is also higher than competing technologies 

because the entire wafer is aligned 

and exposed in one shot. 

Tamarack Scientific 

[tamsci.com] 

Tamarack Scientific’s Model 

336 breaks through traditional 

tradeoffs between the high 

yield of a stepper and the high 

throughput of a proximity 

aligner to provide both of these highly 

desirable benefits. 

On a projection scanner, the mask 

and wafer are separated by 200mm and 

the mask image is projected through a 

lens onto the wafer, eliminating the 

need for mask-to-wafer contact, a major 

source of repeatable defects and contamination, 

thus producing a higher yield. 

With projection, the unique optical 

and mechanical design provides a large 

depth of focus, ideal for imaging in 

both thick and thin photoresists. 

This is also ideal for wafers with 

topography or wafer bow. Improved 

sidewall angle control and resolution is 

a direct result of a projection system’s 

ability to focus the projected artwork 

image selectively at the optimum depth 

within the photoresist. 

Another key benefit is the continuous 

scanning for high throughput. One fullfield 

mask contains the entire wafer layout, 

including the edge ring required for 

plate-up processes. The entire exposure 

takes place in one continuous step, surpassing 

the throughput performance of 

a stepper, resulting in reduced processing 

cost per chip, and lower cost-ofownership. 

Also, accurate alignment is provided 

by an advanced through-the-lens pattern 

recognition system enhanced by 

Tamfinder, a proven set of proprietary 

Tamarack Scientific uses projection scannning technology for 

its Model 366 system. 

search and best-fit algorithms. An 

optional off-axis system is available for 

dark-field mask applications. 

Tamarack’s Model 336 delivers new 

levels of performance, while providing 

high reliability and reduced processing 

cost and is backed by a world class 

manufacturing and service organization. 

–Matt Souter, vice president 

of sales and marketing 

Ultratech [ultratech.com] 

Ultratech dominates the thick resist 

exposure market for wafer-level packaging. 

Ultratech’s 1X broadband steppers 

have been optimized to address the key 

photolithography challenges, such as 

CD uniformity performance, sidewall 

profile requirements and overlay control 

for thick resists used in the 

advanced-packaging market segment. 

Since steppers illuminate a much 

smaller area during the photolithography 

process, they can provide tight illumination 

control resulting in improved 

CD uniformity and a more consistent 

resist sidewall profile. 

In addition, the use of multi-point, 

enhanced global alignment techniques— 

along with the ability to correct translation, 

rotation and orthogonality 

errors—results in superior product 

overlay performance. 

44 


PRODUCT SHOWCASE 

Underfill for Your Current 

and Future Requirements 

NAMICS is a leading source for high technology underfills, 

encapsulants, coatings and specialty adhesives used by producers 

of semiconductor devices. Headquartered in Niigata, Japan with 

subsidiaries in the USA, Europe, Singapore and China, NAMICS 

serves its worldwide customers with enabling products for leading 

edge applications. 

For more information visit our website 

www.namics.co.jp 

or call 408-516-4611 

SEMPAC’s Open-Pak technology, trademarked for its exclusive design 

features on the air cavity package, is the ideal solution for quick turn 

assembly, customer samples, integrated circuit die qualifications, 

device prototyping and small lot engineering and/or assembly build 

requirements. SEMPAC’s Open-Pak packages meet the latest JEDEC 

outline and footprint standards and are available in QFN, SOIC, SSOP 

and QFP architectures. 

568 E. Weddell Drive, Suite 5 • Sunnyvale, CA 94089 USA 

408-400-9002 ext. 106 • Fax: 408-400-9006 • www.sempac.com 

Guy Gaudenzi: guy.gaudenzi@sempac.com 

Add Quik-Pak to Your IC 

Packaging Foundry List 

We inadvertently failed to list Quik-Pak in our April-May 

listing of packaging foundries. 

Quik-Pak, division of Delphon Industries 

10987 Via Frontera, San Diego, CA 92127 

Phone: 858.674.4676 

Founded: 1994 

Web URL: www.icproto.com 

Contact for more info: Steve Swendrowski, General Manager, 

steves@icproto.com 

Services: Wafer bumping, flip chip packaging, MEMS and RFID 

manufacturing, x-ray inspection, analog/mixed signal test, fine and 

gross leak, logic test, opens/shorts, RF 

Total manufacturing area: 10,000 meters 2 

Quality audit: ISO9001 

46 


Ultratech employs 1:1 stepper technology in its AP300 system. 

Furthermore, the use of a 

Wynne-Dyson lens design 

with a low numerical aperture 

lens provides a large 

depth-of-focus for thick 

resist applications, broadband 

capability and high 

wafer-plane intensity. 

Aside from technical performance 

advantages, the 

use of 1X steppers not only 

eliminates yield loss during 

lithography processing, it 

also enables processing of 

multiple layers on the same reticle— 

thereby reducing recurring manufacturing 

costs. 

This is especially important for the 

cost-sensitive foundry market where 

recurring photomask costs are a significant 

portion of the overall manufacturing 

cost. As a result, the use of 1X steppers 

delivers a high economic value for 

wafer-level packaging applications and 

ensures the best cost-of-ownership for 

these devices. i 

–Manish Ranjan, director, product marketing 

for advanced packaging technology 

One Major Producer of WLPs Talks about Litho Tools Selection 

By Boyd Rogers, Amkor Technology Inc. [amkor.com] 

Avariety of exposure tools are 

used in the packaging industry 

to image the thick photoresists and 

photopolymers (5µm to 100µm) required 

for wafer-level packaging processes. 

These include full field proximity/ 

contact systems, scanners, and steppers. 

The selection of an appropriate exposure 

system depends upon the specific application 

requirements and should be chosen 

to provide the necessary resolution and 

alignment accuracy at the highest throughput 

and lowest overall cost. 

The Lowest Cost Solution 

Full-field proximity/contact systems 

constitute probably the lowest cost solution 

for performing wafer-level packaging 

photolithography. These systems can 

generally be used in applications requiring 

resolution greater than 10µm and alignment 

accuracy in the range of 1µm to 3µm. 

Proximity/contact systems are often 

equipped with high-power lamps to 

deliver high doses and high throughput. 

Edge exposure requirements to facilitate 

forming edge exclusion/contact zones 

for electroplating are easily handled 

with this type of system by appropriate 

accommodations to the mask design. 

These systems can be prone to some 

wafer-yield loss due to mask contamination. 

For this reason, attempts are 

often made to work at as large an exposure 

gap as possible between mask and 

wafer. A large gap, however, may limit 

the resolution achieved on the wafer. 

Scanners 

At a higher system price, scanners can 

provide higher resolution than proximity 

systems and offer other benefits, as well. 

These systems work by projecting an 

image of the mask on the wafer. Since the 

mask never comes in close proximity to 

the wafer, these systems do not generally 

suffer from mask contamination and its 

associated yield loss. Scanners can generally 

provide greater sidewall control and 

produce more vertical structures than 

proximity systems. Overall throughput 

is probably lower with these systems. 

Steppers at the High End 

Steppers are at the high end of the spectrum. 

These systems probably offer the 

highest resolution capability, allowing 

linewidths in the sub-5µm regime and 

Amkor Technology Inc., headquartered in Chandler, 

Arizona, with IC packaging facilities throughout 

Asia, is a user of WLP photolithography. 

the best alignment tolerance. 

They suffer from probably the lowest 

overall throughput, however, and the 

highest cost of ownership. Today’s packaging 

steppers facilitate extremely high 

exposure doses, multiple wavelengths for 

exposure, and special functions for handling 

edge-exclusion regions. 

The choice of exposure tool for packaging 

applications should match the 

capabilities desired. It’s not uncommon 

to find multiple systems in packaging 

houses, with product funneled through 

the system required to meet product 

requirements and maintain low costs. i 

Mr. Rogers is vice president–global 

R&D–WLP for Amkor. [broge@amkor.com] 


47

INTERNATIONAL DIRECTORY OF LITHOGRAPHY TOOLS FOR WAFER-LEVEL PACKAGING 

Company Name 

Address 

b Phone 

Year Founded 

Model Name and Number 

V Introduced 

✖ Level of Automation 

M=Manual; S=Semi-automatic 

A=Automatic 

M Maximum Wafer Size 

in mm 

w Wafer Throughput/Hour 

at x 

L Lithography Method 

e Exposure Source 

t Wavelength in mm 

1 Prinicipal Application 

2 Secondary Application 

N Alignment Accuracy in µm 

r Resolution in µm 

[web site] 

U.S. Office 

❉ Contact 

Notes: Information has been furnished by the respective manufacturers 

and is not all-inclusive. Issue advertisers are listed in boldface type. 

CM=Consult Manufacturer. 

Anvik Corp. 

6 Skyline Dr. 

Hawthorne, NY 10532 

b 914.345.2442 

CM CM [anvik.com] 

❉ info@anvik.com 

EV Group 

DI Erich Thallner Strasse 1 

4782 St. Florian, Innsbruck, Austria 

b +43.7712.5311.0 

1980 

EVG 1@ Aligner 

V July 2002 

✖ M, S, A 

M 300 

w >100/300mm, 

>110/200mm 

L Contact proximity mask alignment 

e Mercury short arc lamp 

t 365, 405, 436 

1 Wafer bumping 

2 MEMS 

N 0.5µm/3σ 

r >3-4µm 

[evgroup.com] 

EV Group Inc. 

7700 S. River Pkwy. 

Tempe, AZ 85284 

b 480.305.2400 

❉ Steven Dwyer, vice president and general manager– 

North America 

sales@evgroup.com 

❉ Alois Malzer, product manager 

iqaligner@evgroup.com 

SUSS MicroTec Inc. 

Lithography GmbH 

Division of SUSS MicroTec 

Schleissheimer Str. 90 

85748 Garching, Germany 

b +49.89.32007.0 

1949 

MA300Plus 


✖ A 

M 300 

w >100 

L Proximity mask alignment 


t 365, 405, 436 


2 Wafer redistribution 

N 0.5µm 

r Down to 3µm in proximity mode 

[suss.com] 

SUSS MicroTec Inc. 

228 Suss Dr. 

Waterbury Center, VT 05677 

b 480.305.2400 

❉ info@suss.com 

❉ Ralph Zoberbier, international product manager– 

mask aligner 

r.zoberbier@suss.de 

Tamarack Scientific Co. 

220 Klug Circle 

Corona, CA 92880 

b 951.817.3700 

1966 

Modul 336 

UV Projection Scanner 

V 2000 

✖ A 

M 300 

w 60@300mJ/cm 2 dose 

L Projection scanning, 

projection stepping 


t 350-450 

1 MEMS 


N CM 

r 4µm standard, 2µm optional 

[tamsci.com] 

❉ Matt Souter, vice president of sales and marketing 

sales01@tamsci.com 

Ultratech Inc. 

3050 Zanker Rd. 


b 408.321.8835 

1979 

Unity AP300 


✖ A 

M 300 

w 75@300mm 

L Projection stepping 

e Mercury arc lamp 

t 350-450 


2 Wafer redistribution 

N 500nm 

r 2µm 

[ultratech.com] 

❉ Belinda Kause, sales support manager 

bkause@ultratech.com 

48 


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www.chipscalereview.com

Driven by ‘Smartphones,’ Package-on-Package 

Adoption and Technology Are Ready to Soar 

As an enabling technology, package-onpackage 

greatly expands device options 

by simplifying the business logistics of 

stacking and helps manage the cost 

impacts that derive from consumers’ 

increasing demands for multimedia 

processing and more memory. 

By Lee Smith, 

Amkor Technology Inc. 

Chandler, Arizona 

[amkor.com] 

Package-on-package (PoP) technology 

is designed for products 

that need efficient memory architectures 

including multiple buses and increased 

memory density with performance, 

while reducing mounted area. 

PoP shipments more than doubled in 

2007, driven by the strong adoption of 

smartphone applications where high 

semiconductor content puts PWB area 

at a premium. Adoption rates indicate 

all major smartphone makers will be using 

PoP technology by the end of this year. 

Tear-down reports for high-performance 

smartphones, coupled with embedded 

memory forecasts, reveal a trend for the use 

of two PoP stacks. In use, the baseband 

modem and code memory are one stack, 

with the applications processor and operating 

system memory comprising the second. 

40 Percent Growth Forecast 

TechSearch International [techsearchinc. 

com] recently forecast 40 percent compound 

annual PoP growth through 

2012 1 as summarized in Figure 1, which 

shows shipment growth outlook from 

2007 through 2011. 

Strong demand for smartphones is 

being forecast by industry analysts with 

Smartphones, such as this Nokia e90 Communicator, are a key driver in the PoP market. (Nokia) 

an increasing number of business professionals 

and consumers demanding the 

high speed connectivity and multimedia 

content these feature-rich handsets provide. 

Today, the cellphone market has split 

into two major segments: The ultra-lowcost 

handset segment for emerging 

markets (or new subscribers) and the 

feature-rich smartphone segment for 

subscriber upgrades in mature markets. 

Market reports indicate there were 

over 3 billion mobile phone subscribers 

last year, with more than 1 billion using 

data services and more than 600 million 

multimedia users. 

With the lines blurring between “onthe-go” 

professional and personal 

lifestyles, the mobile phone is becoming 

our most personal computer, providing 

rich multimedia content with anywhere 

e-mail and Internet access. 

Tomi Ahonen of Ahonen Consulting 

[tomiahonen.com] said in 2005, “The 

mobile phone is still the only device 

that around 30% of the world’s population 

is carrying with them constantly.” 2 

Recently, Ahonen reported that last 

year some 30 percent of Internet access 

was exclusively from mobile phones, with 

mobile being the majority user access in 

Japan, South Korea and India. As emerging 

markets mature, the cost of new features 

and media services will decline. 

Feedback from designers indicates 

that PoP has become the 3D packaging 

platform of choice in feature-rich handsets. 

PoP has proven to provide the best 

solution to their challenges of increasing 

semiconductor content and design 

flexibility, while reducing cost, size, 

weight and time-to-market. 

Market Development Model 

To date, strong growth and high adoption 

in smartphones have outpaced 

expectations and overshadowed all 

other PoP applications. 

To understand future market and technical 

requirements better, I evaluated 

the history and outlook for PoP against 

the classic technology adoption and 

market development life-cycle model 3 


Figure 1. TechSearch International is forecasting a 

40 percent CAGR for PoP through 2012. 

as shown in Figure 2. (This model helps 

evaluate changes in the landscape of 

competitive advantages for a new technology 

and considers the innovation 

requirements as the technology and 

market matures.) 

The disruptive technology (represented 

by the light bulb) is the bottom (logic) 

packaging technology and the use of 

SMT processing to stack components in 

the PWB assembly flow of the handset 

manufacturing process. 

The bowling pins represents that PoP 

has crossed the chasm from niche to 

applications-based demand and is gaining 

acceptance across a series of adjacent 

applications that have the same set of 

requirements. 

The tornado represents PoP has withstood 

the pressure from competing 

technologies to provide high value and 

become a standard in the application, 

leading to strong revenue growth (represented 

by the stack of money) for the 

market leaders. 4 

Second Phase 

The second phase, characterized as the 

growth market, will be driven by both 

system and device designers who have 

realized PoP offers technical and logistics 

product advantages which can be 

applied to the processor and memory 

architecture requirements in other 

applications. 

With strong demand 

coming from system 

designers and the technology 

push coming from device 

suppliers, a global industry 

infrastructure with 

economies of scale has 

been established, enabling 

ease of adoption in new 

applications. 

One unexpected new 

application is for embedded 

processing—not to solve 

form factor requirements, 

but due to electrical performance and 

memory architecture flexibility. 

As PoP’s design, logistic and performance 

advantages are recognized in more 

applications; designers will drive PoP 

technology to higher density and performance 

requirements. 

Advanced Features 

This is already well underway in handsets, 

where advanced multimedia features 

are being demanded in both next-generation 

smartphones and a new class of 

computers known as ultra-mobile PCs. 

These advanced handheld systems 

demand high performance signal processing 

and memory architectures with 

high speed anytime/anywhere wireless 

connectivity that will require higher density 

next generation PoP technologies. 

The macro trends for PoP match those 

of handheld systems: smaller, thinner, 

and lighter, with higher performance at 

a lower total cost of ownership. But a 

clear understanding of the system and 

device drivers is required for selecting 

and developing a robust next-generation 

PoP technology platform. 

The system and device drivers shown 

in Figure 3 can be combined into the 

following set of key, next-generation 

PoP technology requirements: 

• High-density memory interface that 

will scale with memory architectures 

without requiring new stacking 

process development; 

Figure 2. This market development model evaluates changes in the 

PoP technology landscape. 

Macro Trends, System Drivers 

and Device Drivers 

System drivers: 

• Reduced PoP area footprint and stacked 

height. 

• Reduced component warpage for fine pitch 

SMT stacking using existing processes. 

• 3D graphics & high resolution video streaming, 

drive higher speed signal processors 

and may require integrating decoupling 

capacitors within the base package to manage 

high speed or noise sensitive signals. 

• More complex memory architectures with 

more capacity, wider bus and high data 

transfer rates. 

• Improved solder joint reliability without 

underfill 

Processor device drivers: 

• Dual core processors that integrate baseband 

modem and application processor blocks, 

drive increased interconnect densities. 

• Higher speed processor that can exceed 1GHz 

with more complex memory controllers, 

which drive tighter signal integrity and timing 

budgets. 

• Transition to 65nm and 45nm low power 

process nodes to enable higher CMOS integration 

and performance at lower cost. 

• Transition to flip chip interconnects for performance, 

I/O density and size requirements. 

• More dual die chipset components that integrate 

digital and analog devices, add new 

high speed modem capabilities or stack 

baseband with application processor chips. 

Memory device drivers: 

• Higher speed RAM—from SDRAM to low 

power DDR to low power DDR2. 

• Wider bus width from 16 to 32 bit and from 

shared to split, to 2 channel bus architectures 

that require higher pin counts. 

• Increased capacity for both RAM and Flash 

memory, drive larger die or more die in the 

stack. 

• Expanded memory architecture flexibility, 

so that a single memory interface supports 

a wider range of memory combinations. 

Figure 3. Macro trends, system drivers and device 

drivers for PoP 

52 


1. Bottom wirebonded, center gate mold package structure 

has warpage control, thickness, die size, dual or stacked 

die, passive integration and memory interface density 

limitations. 

2. Bottom flip chip, exposed die package structure has 

warpage control, underfill bleed, stacked die and 

handling limitations. 

Figure 4. This graphic illustrates limitations of current 

bottom PoP technologies. 

• Tighter warpage control for high 

stacking yields with fine-pitch components, 

without PoP thickness 

reduction limitations; 

• A bottom package platform that can 

support wirebond, flip chip, dual die, 

stacked die and passive integration 

requirements without expensive new 

tooling or process development. 

Figure 4 illustrates the current singlechip 

bottom logic package platforms in 

volume use today and their shortcomings 

in meeting the above next generation 

requirements. 

Wire bond designs dominate the 

current class of baseband or application 

processor devices, thus structure 1 

represents the bulk of 2007 PoP stacks. 

At 65nm there has been a strong transition 

to flip-chip designs, as shown in 

structure 2, to meet I/O density and 

electrical performance requirements. 

Cost and Technical Limitations 

Both of these bottom PoP structures 

have cost and technical limitations 

which would require major trade-off 

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Next-Generation Solutions 

• Extremely thin die (≤50µm) with thin die 

attach and ultra-low-loop wire bonds under 

very thin 0.2mm mold caps that can support 

0.5mm pitch stacking. However, redesign 

and retooling is required below 0.5mm pitch. 

• Build-up substrate technologies that provide 

a partial cavity structure for the die to recess 

below the memory interface stacking pads; 

but high cost, limited availability, design and 

material set restrictions limit this technology’s 

adoption. 

• Adding solder balls to the top lands of the 

bottom package to allow use of current mold 

caps for finer pitch or taller stacked interface 

applications (associated with stacked die in 

the bottom package); this effectively extends 

the range of the current technology but does 

not address all of the next-generation 

requirements. 

• Memory interface fan-in-like structures 

which apply technologies used in niche package-in-package 

structures, but have cost and 

stack-height restrictions; this may limit commodity 

memory and stack height requirements. 

It would also require a new class of 

extremely thin fan-in memory footprints 

which suppliers have to offer in addition to 

current MCP and top PoP components. 

• Embedding the processor device in an 

organic build up substrate or rebuilt/ redistributed 

wafer-level process technology-- 

each has serious cost, yield, infrastructure, 

new development, capital investment and 

cycle-time limitations. 

Figure 5. Next-generation PoP solutions 

concessions to enable the application of 

current technologies to the range of 

next-generation PoP requirements. 

Technical evaluations and feasibility 

studies have been conducted on a host 

of solutions proposed for next generation 

requirements, as shown in Figure 5. 

The current technologies can address 

a subset of the next-generation requirements 

but have limitations when applied 

across the range of requirements and 

future PoP applications. 

They also present risks in maintaining 

low unit, development and capital 

equipment cost structures. Thus, a new 

technology is required that leverages 

mainstream package platform roadmaps 

following lessons learned from initial 

PoP development, where we applied a 

disruptive but proven technology (center 

pin gate molding) on the base technologies 

from mass market fine-pitch 

54 


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Review is available in traditional 

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The industry leader again in 2008 in ad pages, ad revenue and original editorial!

14 x 14mm 6 net daisy chain next generation PoP test vehicle 

- Mold cap with molded underfill encasing 

• 7 x 7mm Flip Chip daisy chain die at 22μm bump pitch 

• 32 tiny 01005 size 0 ohm resistors (to represent decoupling caps) 

Cross Section View 

Top View 

200 Solder Lands 

@ 0.5mm pitch 

memory interface 

Bottom View 

620 BGAs @ 

0.4mm pitch 

TMV test vehicle reported ast ECTC 2008 

Figure 6. This is the high density, six-net daisy chain test vehicle reported at ECTC. 

BGA (FBGA) and stacked die platforms 

allowed the PoP (structure 1) to be 

released to production just 15 months 

after concept definition, as reported 

earlier. 5 

Next Generation PoP Solution 

Following years of evaluation, feasibility 

studies and customer collaboration 

projects, details of a new structure 

expected to provide scalability to meet 

next generation PoP requirements were 

reported this year. 6 

The disruptive, but proven technology 

applied here is laser ablation (referred to 

as through-mold via technology or TMV) 

to enable use of matrix-molded processing 

for the bottom package platform. 

Figure 6 shows the high density 6-net 

daisy chain test vehicle reported at ECTC, 

designed to test the next-generation 

upper limits of package through PWB 

assembly and reliability requirements. 

The benefits of TMV technology for 

next generation PoP requirements are: 

• TMV technology removes the pitchvs.-package-clearance 

bottlenecks to 

support future memory interface 

density requirements. Figure 7 illustrates 

the PoP size reduction benefits, 

as TMV enables the memory interface 

to scale with CSP pitch reduction trends. 

• TMV improves warpage control and 

bottom package thickness reduction 

Figure 7. Size reduction benefits of PoP 

requirements, by 

utilizing a balanced fully-molded References 

structure. 

1. Advanced Packaging Update: Market and 

• TMV provides an increased die to 

Technology Trends, Volume 4, March 2008; 

package size ratio. 

TechSearch International. 

• TMV supports wire bond, FC, 

2. Financial Times, Sept. 1, 2005, Tomi Ahonen. 

stacked die and passive integration 3. G. Moore, “Darwin and the Demon, 

requirements. 

Innovating Within Established Enterprises,” 

• The TMV structure leverages strong technology 

roadmaps and high volume scale, 4. Amkor PoPs Cork for Fast-Growing Package- 

Harvard Business Review, July-August 2004. 

from FBGA, stacked die, flip chip CSP, on-Package Solution, Amkor Technology press 

and SiP platforms. Integrates proven release, April 2007. 

laser ablation technology available from 5. L. Smith, “Package-on-Package: The Story 

a host of laser process equipment suppliers. Behind this Industry Hit,” Semiconductor 

• TMV trials have shown improved 

International, June 2007. 

board level reliability with fine pitch 6. J. Kim et al., “Application of Through Mold Via 

memory interfaces. 

(TMV) as PoP Base Package,” 58th Electronic 

Components and Technology Conference (ECTC), 

Summary 

The current generation of PoP technologies 

will continue to see strong growth 

and new applications. However, to meet 

the complex set of next-generation PoP 

requirements, a new higher density bottom 

package structure is needed. 

After evaluation, we determined that 

TMV technology provides the best set 

of cost-, performance- and scalability 

attributes. TMV technology for PoP 

applications has met smartphone stacking 

and board level reliability requirements, 

as demonstrated in joint work with a 

leading OEM. Final qualification work 

is currently underway. i 

Lake Buena Vista, Fla., May 27-30, 2008. 

Mr. Smith is a vice 

president of business 

development for 

Amkor Technology 

Inc., Chandler, Ariz. 

He has authored or 

co-authored numerous 

patents, technical 

papers and industry articles, including a 

chapter on stacked/3D packaging. With 

over 27 years of experience in 3D packaging, 

he is recognized for leading the definition, 

development and deployment of the current 

PoP technology. [lsmith@amkor.com] 

56 


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Case Study: Building a Two-Chip Stacked Package 

Engineering a single package housing 

multiple chips stacked vertically one 

above the other is a common practice 

that results in smaller and more 

efficient packages for devices. This 

article describes a case history and 

the challenges faced in the design 

and manufacture of the package. 

By Fred Haring, John Jacobson, 

Chris Hoffarth, Syed Sajid Ahmad, 

and Aaron Reinholz, 

Center for Nanoscale Science and 

Engineering, North Dakota State 

University, Fargo N.D. 

[ndsu.edu/csne] 

Stacking chips to reduce the volume 

of system electronics has 

played a significant role in the transition 

towards smaller, more efficient 

and faster systems in all applications. 

Die stacking makes it possible to combine 

the different functions of specific 

devices to make a hybrid with combined 

attributes. 1, 2 

The design of electronics and electronic 

components is driven to be multi-functional, 

space saving, smaller, lighter and 

faster to satisfy market dynamics. As an 

example, two or more processors packaged 

in one single package will result in 

an overall package size smaller than 

each individual package with the combined 

computing power of the two 

individual, integrated processors. 3, 4 

In this effort, the total volume of two 

off-the-shelf devices was reduced to less 

than one-fourth of their combined 

original volumes (Figure 1). A significant 

portion of the reduction in size 

came from stacking the dice and from 

the conversion to a ball grid array format 

from a leaded package. 

A CNSE technician evaluates assembled CSP components attached to a leadframe. 

Stacked-Dice Design Considerations 

Package size is the first parameter to 

determine (x, y, and z dimensions). The 

package dimensions will depend on: 

• The number and size of the chips to 

be packaged; 

• Thickness of the chips; 

• Substrate type; 

• Capabilities of the materials and 

equipment available for the assembly; 

• Number of I/Os to be routed; and 

• The interconnection style (chip-tosubstrate 

and substrate-to-system): a 

solder ball array, land grid array, or 

other type of printed circuit board 

interconnection style. (See the example 

in Figure 2.) 

The greatest space-saving planar design 

is a grid array. The extent of miniaturization 

will be dictated by the solder 

ball size, grid array pitch and signal line 

and spacing capabilities. 

When designing a solder-ball grid array, 

the designer will need to determine which 

array pitch and pad spacing will allow 

the maximum number of trace connections 

in the smallest space to keep the 

device footprint to the minimum size. 

The designer must also consider signal 

interference or cross-talk issues, limits 

of manufacturability tolerances, and the 

number of circuit layers that are desirable 

in the substrate material. 

Substrate Is the Limiting Factor 

The substrate is the limiting factor in determining 

x-y dimensions. To minimize x-y 

dimensions, second-bond pad size and 

location on the substrate must be optimized 

through a tighter radial pattern, or multiple 

radial patterns around the bottom die. 

This leads to stacking the dice strategically 

so that the second wire bond pads 

of each die can be staggered or placed 

so the wires fall between the pads of the 

lower die when the upper die is bonded. 

58 


Figure 1. The two-stack package is shown to the left of the two packages it replaced. The larger package 

is available in more than one version. All three packages are compared to a North Dakota Bison quarter to 

provide a size comparison. Considering various package configurations, combined volume is reduced 

anywhere from 74 to 82 percent. 

with appropriate die attach adhesive— 

conductive or non-conductive, as specified 

by die design. Wire bonds connect the 

die pad (first bond) to leads (second 

bonds) on the top of the substrate and 

peripherally around the die edge as 

shown in Figure 3. 

The bottom side of the substrate is 

made up of the solder ball pad array 

with exposed solder pads surrounded 

by solder mask (shown in Figure 4). 

The solder-ball pads may be metal 

defined or solder-mask defined depending 

on the design requirements (Figure 5). 

In this case they were solder-mask 

defined, SMD (Figure 4). SMD pads have 

lower solder ball contact areas to the 

substrate but result in more uniform 

height due to a more uniform pad size 

compared to non-solder-mask-defined 

(NSMD) pads. 

Figure 2. In this 3D rendering of the two-stack design, the bottom die is shown in blue while the top die 

is gold. Silver spheres under the substrate are the solder balls. Features on the chips, signal traces on the 

substrate, and the molded encapsulation are not shown. 

Wire loop height, flat length, style of 

loop, and bond length to the top of the 

package are all important considerations. 5 

To minimize the z dimension, all 

components must become thinner: 

thinner dice, thinner substrates, optimized 

ball size and optimized loop 

height for wirebonds. Smaller solder 

balls will reduce height and allow a 

smaller pitch. The thinnest allowable 

encapsulation material may also be used 

to reduce the z dimension. 

Thermal, mechanical, and electrical 

stability is critical. A design driven by 

guidelines resulting from the electrical 

and thermal modeling of the design can 

be validated after a pilot run of parts is 

built. A combination of functional and 

thermal tests may be performed in 

order to verify the integrity of package 

design. 

Stack Configuration 

The Center for Nanoscale Science and 

Engineering (CNSE) at North Dakota 

State University, Fargo, was tasked with 

combining two specific parts (designated 

“Chip A” and “Chip B”) into a smaller, 

thinner dual-processor package. 

For a two-die stack it is convenient to 

place the larger die at the bottom, face-up, 

Assembly Process 

The two-stack package was designed 

using a two-layer BT substrate. BT 

material was chosen for overmolding 

purposes due to cost and lead-free compatibility 

considerations (See Table). 

The package was designed to be 

1.4mm maximum thickness as a BGA 

utilizing 168 lead-free solder balls with 

outer lead bond grid dimensions set at 

650 x 650 micrometers, due to wire 

bond pad location. 

The outer lead bond solder mask 

diameter used was 450 micrometers to 

allow for a 300 micrometer metal-defined 

solder ball pad. The circuit trace width 

Figure 3. Front view of the substrate demonstrating how the dice are attached to this side. Each substrate 

has three groups of four packages each. 


Figure 4. The backside of the substrate: Solder 

balls will be attached to the grid arrays shown in 

the picture. The fiducials around the arrays serve 

as dicing guides. 

and spacing were set at 55 and 60 micrometers. 

This setting was found to be the 

maximum trace with the minimum space 

requirement for routing capabilities. 

Ball pitch was set at 0.65 mm. Vias of 

200 micrometers with 100 micrometer 

holes were used to bring traces from in 

place of to the top side of the substrate 

down to the solder ball pads on the bottom 

side of the substrate. 

The outer lead bond to package edge 

distance was 400 micrometers to allow 

for proper package separation at dicing. 

Vias were to be centered over pads. The 

dicing saw street width was set at 165 

micrometers, and bare copper on top of the 

substrate was eliminated where possible. 

Extra fiducials for dicing and laser 

marking allowed for easier alignment 

when processing the substrate. Two sets 

of fiducials were used in the die placement 

area. The innermost set was used for base 

die placement (Chip A), while another set 

of outer fiducials was used for top die 

(Chip B) placement and wire bonding. 

The substrate design incorporated a 

center grounding pad for grounding the 

Chip A die. Alignment marks on the 

substrates helped confirm correct dicing 

during singulation. (Figure 6) 

Process Documentation 

The assembly process began with a traveler 

which is a written assembly document 

that outlines and follows each step of 

the process and documents all processing 

data. The traveler is also used to determine 

and notate production yield. The 

process involves many steps. The main 

steps are shown in Figure 7. Die attach 

steps are repeated for the second die 

stacked on top of the first die. 

Both wafers for each die were thinned 

and polished to the desired design 

thickness prior to singulation. Selective 

60 


a b c 

Figure 5. 5a and 5b show two examples of non-solder mask defined (NSMD) or metal defined pads for 

solder balls. 5c is a solder-mask defined (SMD) pad for solder ball attachment with flux on the pad. 

die attach adhesives were used for each 

die. The base die needed to be electrically 

grounded to the underlying ground pad 

(Figure 6); therefore, a silver conductive 

epoxy was used. 

The top die had to be insulated from 

the Chip A circuitry and did not require 

a backside connection; therefore, a nonconductive 

epoxy was used. Dispense 

parameters were tuned by first using 

glass die sized to the functional die. 

Glass die (Figure 8) allowed for observation 

of any voiding under the die and 

also gave an idea of how much squeezeout 

occurred. 

Squeeze-out is the amount of excess 

adhesive that squeezes out between the 

Figure 6. Top view of a package site. The inner 

four cross marks locate the bottom die. The outer 

circle and cross are used to locate the top die and 

wire bonds. 

Important Properties of Select, Substrate-Related Materials 

Dielectric CTE, % Water 

Material Constant ppm/°C Tg, °C Absorption 

BCB 2.65 52 350 0.25 

Polyimide 3.5-4.2 10-14 250 0.35 

BT 4.3 15-16 180 0.05 

FR-4 4.8 13-18 125 0.1 

Cyanate Ester 3.6 8-10 230 0.08 

Finally, the choice for test socket 

materials is clear! 

Krefine ® ESD PEEK meets and exceeds all material needs for ESD 

applications and for uses simply requiring the best strength and 

dimensional stability. It provides consistent, reliable ESD properties 

combined with the outstanding mechanical and wear benefits of its 

base VICTREX ® PEEK polymer. 

From the static dissipative requirements of 

the disk drive industry to the anti-static grades 

used in the test socket industry, Krefine 

ESD PEEK stock shapes are available in 

the resistivity ranges shown in the graph. 

Krefine ESD PEEK makes conductive/insulative 

‘hot and cold’ spots a thing of the past. 

Now available “SS10” = “10 10 ” 

ESD Range (Ω/sq.) 

10 7 

10 9 

10 11 

Conductive 

Krefine 

EKH-SS07-PK 

(for disk drives) 

Dissipative 

Krefine 

EKH-SS09-PK 

(for test sockets) 

Anti-static 

Krefine 

EKH-SS11-PK 

(preferred for test 

sockets) 

Insulative 

The exclusive U.S. distributor of 

Krefine stock materials. 

(800) 526-2960 

(480) 926-8100 

www.piperplastics.com 

For more information on Krefine products for test socket applications, 

please visit Piper Plastics at SEMICON West, booth #5415, North Hall. 


Figure 7. This flowchart shows the many steps involved in the MCP assembly process. 

substrate and the die edge, or the 

amount of excess adhesive between the 

top die and the wire bond pads on the 

top of the bottom die and is necessary 

to ensure complete fill under the die. 

An incomplete fill can result in 

mechanical stresses during operation 

leading to device damage and ultimately 

functional failure. Preferred squeeze-out 

forms a nice fillet along all edges of the 

Figure 8. Use of glass die to optimize the adhesive dispensing 

process for void-free, controlled fill and squeezeout. 

The top picture shows the adhesive dispense pattern 

on the bottom die site. The bottom picture shows the 

placed glass die to view voids and filling characteristics. 

62 


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die. The proper amount of squeeze-out 

is needed for good void free and strong 

die attach yet the second bond pads on 

top of the substrate should not have any 

adhesive on them. 

Wire Bonding 

Wire bond length and loop height for 

the bottom die was kept as short and 

low as possible to provide ample room 

for the top die wires. The top die wire 

bonds used a taller flatter wire profile 

over the bottom die wires and reached 

pads that were strategically placed outside 

the bottom die pad groupings, yet 

not so far as to allow for a very long 

wire that would be prone to drooping 

or easy sweep when overmolding. 

Figure 9. The two stacked, wire-bonded dice on a 

package site 

Figure 10. Gold wires were locked in place with a 

thick material before overmolding to alleviate wire 

sweep. 

Grounds of both die were wired to 

one pad on the substrate. If power supply 

circuits were the same voltage, they 

were also wired to the same pad on the 

substrate. This strategy cut down on the 

total number of contact points needed, 

so one solder ball may have three 

grounds or power circuits attached to it. 

This scheme also provided good electrical 

connection between the dice. The 

top die wire bond loop height played a 

big role in determining overall package 

thickness, shown in Figure 9. 

X-ray inspection after overmolding 

illustrated whether the wires were being 

swept or not. The x-ray did show wire 

sweep even after process adjustments. 

The gold bonding wires were 

“locked” by dispensing a wire-locking 

material, similar to glob-topping, 

around the edges of the die and curing 

it, making a dam-like ring locking the 

wires in place (Figure 10). 

64 


Laser Marking and Ball Attach 

Package marking was accomplished by 

using a green marking laser that burned 

the required insignia, part number, logo 

and serial number into the overmold 

material. Laser marking is relatively 

quick with a machine that can step, 

repeat, and serialize. 

Clean surfaces and good flux printing 

help in the ball attach process. Plasma 

cleaning the substrates prior to flux 

application will give a clean surface for 

ball attach (Figure 5). Shorted balls may 

be caused by too much flux wetting the 

pads together and creating a path on 

which solder can flow (Figure 12). 

After reflow, the substrates are washed 

clean of flux in an aqueous cleaner if 

required. 

Lead-free solder balls were used to make 

the grid array. A nitrogen atmosphere 

was used during reflow. Subsequent ball 

shear measurements will indicate the solder 

ball adhesion quality quantitatively. 

Figure 11. Top side after encapsulation 

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Wafer Bumping Services 

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Singulation 

Package singulation was accomplished by 

using a dicing saw with a blade designed 

specifically to cut overmold material. 

The most important characteristics of 

the blade are the width, exposure and 

cutting purpose. 

Inspection and Testing 

After singulation by a dicing saw, parts 

were measured for correct sizing and then 

placed in a custom-designed test socket 

for electrical testing. Electrical test usually 

consists of testing for opens and shorts, 

resistance measurements and IC diode 

tests that assure interconnect to the dice. 

Other tests such as inductance and capacitance 

may be performed, if applicable. 

Quick-turn and 

mass-production 

Highly competitive, 

low-cost bumping 

technology 

Exceptional quality 

through high-level 

expertise 

Pac Tech GmbH 

Tel: +49 (0)3321/4495-100 

sales@pactech.de 

www.pactech.de 

Pac Tech USA 

Tel: 408-588-1925, ext. 202 

sales@pactech-usa.com 

www.pactech-usa.com 

Pac Tech Asia Sdn. Bhd. 

Tel: +60 (4) 6430 628 

sales@pactech-asia.com 

www.pactech-asia.com 

NAGASE & CO., LTD. 

Tel: +81-3-5640-2282 

takahiro.okumura@nagase.co.jp 

www.nagase.co.jp 

Available Processes 

Electroless Ni/Au under-bump metallization 

Ni/Au bump for ACF or NCP assembly 

Solder paste stencil printing 

Solder ball drop for wafer-level CSP 

Solder jet for micro-ball placement 

BGA and CSP reballing 

Wafer backside thinning and wafer dicing 

Special Features/Technologies 

Over 10 years experience 

U.S. Government Certified 

4- to 12-inch wafer capability 

Wafer pad metallization: Al and Cu 

Solder alloys: eutectic SnPb37, lead-free, 

low-alpha, and AuSn 

Fluxless and contactless bumping for MEMS 

and optoelectronics 

Ni/Au interface for wire-bond applications 

Figure 12. Bottom of the substrate before (left) 

and after (right) solder ball attach 

The leader in low-cost electroless wafer bumping. 


Figure 13. X-ray image of the assembly helps 

identify voids, wire sweep, etc. The picture also 

shows the wire bonds between the dice and the 

substrate, highlighting the complexity of design 

and manufacture. 

More advanced tests such as functional 

testing are completed by the customer 

for this particular package. Combining 

the electrical tests with X-ray imaging 

of the parts provided verification of the 

assembly processes (Figure 13). 

Representative samples were sectioned 

to make sure that all interfaces were adhering 

adequately, illustrated in Figure 14, 

without any delamination or voids at 

the interfaces. 

Conclusion 

Adequate up-front design and planning 

resulted in a quality, two-die stacked 

package saving a significant amount of 

much-contested real estate in the system. 

Multiple functional capabilities, faster 

processing speeds between dice, reduced 

number of contact points, a smaller 

footprint and a shorter package height 

are the hallmarks of the well thoughtout 

construction and design. 

Acknowledgments 

Technical support for this project was 

provided by Tessera Technologies. 

Numerous CNSE staff members also 

contributed significantly to this project, 

especially Linda Leick, Darci Hansen, 

Matt Sharpe and Meridith Bell. 

This material is based on research 

sponsored by the Defense Microelectronics 

Activity under agreement number 

H94003-06-2-0602. i 

References 

1. Charles A. Harper, ed., Electronic Packaging and 

Interconnection Handbook (New York: McGraw- 

Hill, 2004), pp. 8-73. 

2. Clyde F. Coombs, ed., Printed Circuits 

Handbook, 2d Edition (New York: McGraw- 

Hill, 2001), pp. 2-17. 

3. Eugene R. Hnatek, Practical Reliability of 

Electronic Equipment and Products, (Boca Raton, 

Fla.: CRC Press, 2003), pp. 232-233. 

4. Charles A. Harper and Charles Cohn, eds., 

Failure-Free Integrated Circuit Packages,(New 

York: McGraw-Hill, 2005), p. 55. 

5. Shankara K. Prasad, Advanced Wirebond 

Interconnection Technology, (Norwell, Mass.: 

Kluwer-Springer, 2004), pp. 637-8. 

Mr. Haring is a research 

technician at the Center. He 

earned a bachelor’s degree in 

archeology from Moorhead 

State University in Minnesota 

and earlier worked for the federal government. 

He later returned to college to 

study for an engineering degree while 

working for North Dakota State 

University’s Industrial Engineering Dept. 

[fred.haring@ndsu.edu] 

Mr. Hoffarth received his 

technical training and experience 

while serving in the 

electronics industry over the 

past 8-½ years. He is a graduate 

of the North Dakota State College of 

Science as an electronics technician. Before 

joining CNSE, he was an SMT technician 

for Vansco Electronics in Valley City, N.D. 

[chris.hoffarth@ndsu.edu] 

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66 


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Figure 14. Cross-section through the wire bonds on the bottom die is shown on the upper image. Wires 

going to the top die can be seen at the top. A section through the wire bonds on the top die is shown in 

the lower image. (All graphics provided by NDSU.) 

Mr. Jacobson received a 

bachelor’s degree in electronics 

technology from Arizona 

State University, Tempe. 

Before joining CNSE, he 

served at Micron Technology in Boise, 

Idaho, as a materials engineer. His 25 

years of industry experience includes 

posts at Motorola, Texas Instruments and 

the Microelectronics and Computer 

Technology Corp., Austin, Texas. 

[john.o.jacobson@ndsu.edu] 

Mr. Ahmad is the Center’s 

manager of engineering services. 

He received a master’s 

degree in experimental 

physics from Islamabad 

University, Pakistan. After graduation, he 

taught math and science in secondary 

schools in Ghana. He later worked at 

Intel Corp., where he contributed to quality 

and the reliability enhancement of 

assembly processes. His lengthy experience 

in the electronics industry includes positions 

at National Semiconductor, 

GigaBit/ TriQuint and Micron Technology. 

[syed.ahmad@ndsu.edu] 

Mr. Reinholz is the associate 

director for electronics technology 

at the Center. He 

received a bachelor’s degree 

in electrical engineering from 

NDSU, and was employed by Rockwell 

Collins in Cedar Rapids, Iowa, for 13 

years prior to joining NDSU. 

[aaron.reinholz@ndsu.edu] 

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68 


INTERNATIONAL DIRECTORY OF WAFER-BUMPING SERVICE PROVIDERS 

Notes: This list was compiled from data supplied by the respective providers and is not all-inclusive as to company or service offered. Advertisers in this issue are 

indicated by boldface listings. CM=Consult Manufacturer. 

Company Name 

Address 

b Phone 

> Fax 

Year Founded 

✪ Chairman ★ President 

✦ CEO ✩ COO ✧ Other Title 

sr Number of Employees 

✖ Maximum Wafer Size (mm) 

B Bump Pitches (µm) 

V Bumping Services 

★ Equipment 

A=Aligners, B=Stencil Printers, C=Steppers 

T Bumping Technologies 

J=Jetting, P=Plating, BP=Ball/loading 

placement, S=Sputtered, SP=Stencil printing, 

SB=Stud/ball bump, CP=Copper pillar, O=Other 

a Bump Alloys 

SAC=SnAgCu, Au=Gold, Eu=Eutectic, 

LF=Pb-free, HL=High lead, LA=Low alpha 

[web site] 

❉ Contact 

Additional Offices 

Amkor Technology Inc. 

1900 South Price Rd. 

Chandler, AZ 85286 

b 480.821.5000 

> 480.821.8276 

1968 

sr 5,000+ 

✖ 300 

B 60 to 300 

V 150-, 200- and 300mm 

wafer bumping/test/die 

processing 

★ A 

T BP, P (electroplating), S 

a Eu, LF, HL, LA 

[amkor.com] 

❉ Shellene Garner 

marketing@amkor.com 

❉ Bill Charuk, Director–Marketing/Planning 

b 919.459.1228 

ASPEN Technologies 

Colorado Springs, CO 

b 719.592.9100 

1995 

✦ Jack D. Harrison 

sr CM 

✖ CM 

B CM 

V CM 

★ CM 

T SB 

a Au 

[aspentechnologies.com] 

❉ Jack D. Harrison 

jharrison@aspentechnologies.com 

ASE Group 

Kaohsiung, Taiwan 811 

b +886.7.361.3094 

1984 

sr CM 

✖ 300 

B CM 

V CM 

★ CM 

T P, SP 

a CM 

[aseglobal.com] 

ASE (U.S.) Inc., Santa Clara, CA 95054 

❉ Patricia MacLeod, Marketing Communications Mgr. 

marketing@aseus.com 

b 408.986.6500 

Chip Supply 

Orlando, FL 32810 

b 407.298.7100 

1978 

sr CM 

✖ CM 

B CM 

V CM 

★ CM 

T CM 

a CM 

[chipsupply.com] 

❉ Britney Wolfe, Marketing Manager 

bwolfe@chipsupply.com 

Cirtek Electronics Corp. 

Laguna, Philippines 

b +63.49.541.2310 

1984 

sr CM 

✖ CM 

B CM 

V CM 

★ CM 

T CM 

a CM 

[cirtek-electronics.com] 

❉ Jorge Aguilar, EVP/GM 

jorge.aguilar@cirtek.com 

Cirtek Semiconductor, Belmont, CA 94002 

❉ Norman Chang 

norman.chang@cirtekelectronics.com 

b 650.637.8393 

CV Inc. 

850 S. Greenville, Suite 108 

Richardson, TX 75081 

b 214.557.1568 

2001 

★✦ Chris N. Angelucci 

sr CM 

✖ CM 

B CM 

V Partial wafer and complete 

wafer solder bumping 

★ CM 

T CM 

a CM 

[covinc.com] 

❉ tqcollier@covinc.com 



Company Name 

Address 

b Phone 

> Fax 

Year Founded 







★ Equipment 






a Bump Alloys 



[web site] 

❉ Contact 


FlipChip International 

Div. of Rose Street Labs 

3701 E. University Dr. 

Phoenix, AZ 85034 

b 602.431.6020 

1996 

sr CM 

✖ 200 

B 70 (R&D), 150+ (production) 

V Flip chip and wafer bumping, 

Ultra CSP, EliteCSP, copper 

pillars, thinning, plus backend 

to tape & reel or chip trays 

★ A, C 

T Sputtered UBM, electroless 

Ni/Au UBM, SP, BP alloys, CP 

a CM 

[flipchip.com] 

❉ Jay Hayes, Director of North American Sales 

jay.hayes@flipchip.com 

b 719.481.6444 

i2a Technologies 

399 West Warren Ave. 

Fremont, CA 94538 

b 510.770.0322 

1993 (formerly IPAC) 

sr CM 

✖ 200 (300 soon) 

B 50µm Au stud, 180µm solder 

bump, 400+ WLP 

V WL-CSP and flip chip ranges, 

bumped wafers, finished 

package (WLP and FC), die in 

tape & reel or waffle 

★ B 

T SP 

a Eu, LF, SnAgCu 

[i2a-tech.com] 

❉ Fredrick Solomon, Director of Engineering 

fredrick.solomon@ipac.com 

IC Interconnect 

1025 Elkton Dr. 

Colorado Springs, CO 80907 

b 719.533.1030 

1998 

sr 12 

✖ 200 

B 200µm+ 

V ENi/UBM combined with stencil 

printed solder, low cost wafer 

bumping 

★ CM 

T SP, BP 

a Eu, HL, electroless UBM, SAC 

[icinterconnect.com] 

❉ Leslie Killian, Sales Manager 

lkillian@icinterconnect.com 

Minami Co., Ltd. 

EMS Tsukuba Factory 

38-32, 5-Chome, Minami-Cho 

Fuchu-Shi, Tokyo 183-0026, Japan 

b +81.42.368.8311 

1980 

sr 30 

✖ 300 

B 80µm (45µm diameter) 

V Ball placement, reflow, 

washing, inspection, quick 

delivery, low cost, high 

quality 

★ SP 

T P, SP, BP 

a Solder paste and balls, 

SnAgCu 

[ho-minami.co.jp] 

Pacific Gate Technologies 

3697 Millplain Ct., San Jose, CA 95121 

❉ Danny Fields 

danny.fields@pacgate-us.com 

b 408.705.4721 

Pac Tech GmbH 

Division of Nagase & Co., Ltd. 

Am Schlangenhorst 7-9 & 15-17 

14641 Nauen, Germany 

b +49.3321.4495.100 

> +49.3321.4495.110 

1995 

sr 150 

✖ 300 

B UBM 40µm, bump pitch 

solder 80µm 

V Wafer bumping for Ni/Au UBM, 

Ni/Pd/Au and thick Au for wire 

bonding; wafer level solder 

bumping, BCB repassivation, 

wafer level redistribution, wafer 

thinning, wafer dicing, chip 

singulation, tape & reel 

★ A, SP 

T SP, BP, electroless UBM, J 

a UBM: NiAu, NiPdAu; Solder: 

SnAgCu, SnPb, AuSn 

[pactech.de] 

❉ Thomas Oppert, VP–Worldwide Marketing & Sales 

oppert@pactech.de 

Pac Tech USA Inc., 328 Martin Ave., Santa Clara, CA 95050 

b 408.588.1925 

❉ Dr. Thorsten Teutsch, teutsch@pactech-usa.com 

❉ Andrew Standjord, strandjord@pactech-usa.com 

Pac Tech Asia Sdn Bhd., Bayan Lepas Industrial Zone, 

11900 Bayan Lepas, Penang, Malaysia 

❉ Y.C. Ng, Sales Manager, yc.ng@pactech.com 

Premier Semiconductor 

Services LLC/LP 

2330 W. University Dr. 

Tempe, AZ 85281 

b 480.736.1970 

> 480.736.1971 

2001 

sr 150 

✖ 200 

B 500 

V Specialize in sphere attach 

only, therefore any size/ 

metallurgy is possible 

★ Custom 

T BP 

a Any specified by customer 

[premiers2.com] 

❉ Jody Mahaffey 

jody@e-reachcomm.com 

b 480.656.8315 

70 



Company Name 

Address 

b Phone 

> Fax 

Year Founded 







★ Equipment 






a Bump Alloys 



[web site] 

❉ Contact 


Promex Industries 

Santa Clara, CA 95051 

b 408.496.0222 

1974 

sr CM 

✖ CM 

B CM 

V Au stud bumping, low volume 

★ CM 

T CM 

a CM 

[promex-ind.com] 

❉ Chris Pugh 

pughc@promex-ind.com 

Siliconware Precision Industries Co. 

Tantzu, Taichung, 427 Taiwan 

b +886.4.25341525 

1984 

sr ~14,800 

✖ 300 

B 180 

V CM 

★ A, B, C 

T P, SP, BP, sputtered UBM 

a Sn63/Pb37, Sn5/Pb95, SnAgCu, 

SnAg, SnCu, Au bump 

[spilca.com.tw] 

Siliconware USA Inc., 1735 Technology Dr., 


b 888.215.8632 

❉ Wen Jui Hsiao, Marketing Analysis Dept. Mgr. 

wjhsiao@spil.com.tw 

STATS ChipPAC Ltd. 

Singapore 569059 

b +65.6824.7777 

1994 

sr 14,873 

✖ 300 

B CM 

V Printed, plated and ball drop 

bump, redistribution, flip chip 

interconnect and WLCSP 

★ A, B, C 


a Eu, ultra low alpha HL, LF 

[statschippac.com] 

STATS ChipPAC Inc., Fremont, CA 94538 

b 510.979.8000 

❉ Swami Prasad, Sales Director 

swami.prasad@statschippac.com 

Unisem Group 

Ipoh, Malaysia 

b +605.357.2800 

1989 

sr 9,500 

✖ 200 

B 35+ 

V Gold bumps, electroplated 

solder bumps, electroplated 

pillar bumps, larger solder 

bumps through ball drop 

process 

★ A, B, C, J 


a Au, Cu 

[unisemgroup.com] 

1284 Forgewood Ave., Sunnyvale, CA 94089 

❉ Mike Griffin, U.S. Region Head 

mgriffin@unisemgroup.com 

b 408.734.3222 

I see the semiconductor packaging 

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STANDARDS 


continue to play a major role in 3D 

packaging. 

The next generation of PoP packages 

is called Fan-In PoP (FiPoP). The new 

family is defined this way because it 

allows the package-to-package stacking 

or interconnects to be at the top center 

of the bottom package. 

The FiPoP interconnect is “fanned-in” 

to the top center of the bottom package as 

opposed to the “fanned-out” to the peripheral 

interconnect on the present standardized 

PoP family. The FiPoP was developed 

to address the following challenges: 

• The top memory package size is no 

longer controlled by the bottom 

package size 

• The bottom package can be smaller 

than the present PoP family 

• A thinner over all stacked height can 

be achieved 

• Lower cost may be possible due to the 

smaller stacked PoP footprint 

The FiPoP, like today’s PoPs, leverages 

the existing assembly infrastructure and 

equipment using processes already 

proven in high volume manufacturing. 

The FiPoP has more flexibility to 

integrate 3D system applications into a 

smaller form factor. The FiPoP standardization 

effort will be worked on in 

JEDEC Committees JC-11 and JC-63. 

JEDEC JC-63, the Stacked Package 

Product Committee that standardized 

the present PoP family’s pin outs and 

functionality, will begin its work on 

FiPoP late this year or early next year. 

JEDEC JC-11, the packaging committee, 

will be responsible for creating the 

following three standards: 

• Lower and upper FiPoP Design Guide 

4.XX 

• Lower PoP MO-XXX 

• Upper PoP MO-XXX 

The design guide proposal was presented 

at an April JC-11 meeting and was 

approved for balloting. Package outlines 

will follow when the design guide is 

approved. 

The JC-11 design guide and package 

outlines will be published next year. 

Infrastructure 

In the world of PoP, standardization is 

extremely important to stimulate the 

needed infrastructure. 

Infrastructure is defined from a package 

viewpoint as the shipping tubes, shipping 

trays, test carriers, test sockets, burn-in 

sockets, tape/reel, assembly/ test services 

and the raw materials needed to support 

AT PRESSTIME 

new configurations. 

The most important part of the infrastructure 

is the end customer, without 

them there is no package success. 

Nothing would be worse than to create 

a new PoP configuration and learn no 

infrastructure exists to support its introduction. 

i 

Mr. Bird is a member of the executive staff 

of NeoKinetics Inc. [www.neokinetics.us], 

Tempe, Ariz., a consulting firm focused on 

new product introduction, product engineering/management 

and other services 

in the semiconductor, assembly, packaging 

and associated technologies market space. 

[mark.bird@neokinetics.us] 

RTI Buys Manufacturing, and Sales Rights for UTI 

Morgan Hill, Calif.—Robson Technologies Inc. (RTI),a 

supplier of test sockets and test fixtures, has purchased the 

exclusive manufacturing and sales right for UltraTest 

International’s curve trace test systems, San Jose. 

The acquisition includes UTI’s complete product line, which 

includes the MegaTrace, AutoTrace and MultiTrace units. 

“This purchase makes RTI the only company that can supply 

a turnkey solution for an integrated digital curve trace system, 

Bill Robson dc parametric analyzer and latch-up test system, as well as all 

the required DUT boards, FA test sockets, remote test heads, cable 

and other required fixtures,” according to Bill Robson, RTI founder and president. 

UTI, said Robson, has been a leading supplier of curve trace test systems for 

more than 15 years with systems located worldwide. 

Chris O’Connor, previously UTI vice president, has joined RTI and will continue 

to provide technical support for the test systems. The UTI manufacturing 

and applications support team has also joined RTI. [testfixtures.com] 

Indium Corp. Promotes Hayes to Southeastern Sales Manager 

Clinton, N.Y.—Indium Corp. of America has promoted Greg Hayes to 

Southeastern USA regional sales manager. He has been involved in soldering 

material sales for the past 15 years. 

The Southeastern region includes Alabama, the Dominican Republic, Florida, 

Georgia, Kentucky, Mississippi, Puerto Rico and North and S. Carolina. [indium.com] 


MY VIEW 

Real or Fake The Counterfeit Chip Conundrum 

By Dave Loaney, Guest Contributor, Premier Semiconductor Services [email@premiers2.com] 

Counterfeiting is clearly a 

growing problem in many 

industries, including electronics, 

around the world. 

As the financial impact of counterfeiting 

has grown over the years, so has the 

attention that has been devoted to it by 

everyone from packaging, assembly, and 

test engineers to procurement and quality 

personnel. Today, many feel that counterfeiting 

is the number one issue that 

threatens the electronics supply chain. 

Combating Counterfeiting 

The threat of counterfeit has become so 

great that many governments around 

the world are taking a much more active 

role in combating it; however, finding 

counterfeit electronic components at 

the macro level is not an easy or quick 

process. 

Furthermore, most companies that 

receive counterfeit components many 

times hide or simply do not publicize 

this fact fearing it will alarm their customers. 

So they end up working in more 

of a reactionary mode to deal with 

counterfeit problems as they come up. 

In addition, many companies lack the 

resources and internal experience to 

effectively define and detect fakes. 

Possibly the biggest issue in attacking 

counterfeiting is the large amount of 

misinformation in the marketplace and 

the lack of credible information within 

many areas of the supply chain. 

Customers throughout the chain are 

looking for that “magic piece of paper” 

that says the parts 

they are buying 

are okay. The 

problem is, the 

procedures 

and/or tests done 

in connection 

with this “magic 

piece of paper” 

may not really 

provide them the 

comfort they or 

their customer 

really wants. 

Detection 

Decapsulation, 

x-ray, investigative 

visual inspection, 

and functional 

testing are some 

of the methods 

used to detect 

counterfeits. What do each of them 

really tell you in regard to counterfeit 

detection and how much comfort 

should each give you 

Some suppliers state that a sample 

number of their parts were x-rayed. As 

a result they guarantee that their parts 

were clear of any counterfeits when 

shipped. 

The reality is that if a part is x-rayed, 

one can only determine that there is a 

die in the encapsulation and that it is 

bonded-out. There are many more 

things that are not answered if x-ray is 

the only testing done. 

Until a few years ago, we were used to seeing counterfeit activity in money, 

unauthorized copies of movies and Rolex knock-offs. Today counterfeiting of 

chips has become a major industry ill. 

For example, is this the correct die Is 

there a known good part with which to 

compare it Will it function as it is supposed 

to based on datasheet specs Is it 

even electrically sound 

There are many questions, yet there is 

no single, systematic approach or universal 

standard that everyone has agreed 

on as it relates to counterfeit testing. 

Customers are forced to rely on the 

credibility of various internal and external 

test facilities in providing data and 

testing that they can count on. Some of 

these facilities are better than others. 


74 


Conventional IC Testing Can’t Keep Up with 

Today’s System-on-a-Chip Requirements 

There’s only one way to meet the 

exploding demand for system-on-a-chip 

(SoC) testing, and that is by dramatically 

increasing throughput. In addition, 

packaging and test challenges were 

once considered from the vantage 

point of independent solutions, each 

addressing a unique problem set 

without reference to the other. We 

can no longer afford to be myopic 

regarding our test requirements. 

By Anthony Lum, 

Advantest America Inc., 

San Jose, Calif. [advantest.com] 

In the past, a typical wireless system 

was built primarily from a range 

of components and subcomponents. 

Yesterday’s design practices featured 

functional blocks made up of transistors 

used for amplifiers. Moreover, 

mixers and discrete elements—such as 

matching circuits, filters and resonators— 

populated the system. 

As a result, the physical size of the 

early wireless systems and packaged 

subcomponents was comparatively 

bulky, cumbersome and less usable. 

Integrated RF Evolution 

Clearly, the situation has continued to 

evolve rapidly. Around the mid-1990s, 

an integration of the functional blocks 

was realized, paving the way for the RF 

system-on-a-chip (Figure 1). As RF SoC 

complexities increased, along with higher 

levels of integration, wireless systems 

such as cell phones and WiFi became 

more viable and more ubiquitous in the 

home and workplace. 

As consumer demand increased, however, 

so did pricing pressures on SoC 

manufacturers. The market began to 

This is a fully integrated SoC test cell unit designed to test devices used in consumer products. 

insist on lower-cost product and delivery 

of the solution in smaller packages with 

more complexity. The challenges associated 

with providing more capable test 

solutions with lower cost-of-test are the 

subject of this paper. 

Cost Pressures 

The expanded capabilities of today’s RF 

devices map directly into longer test times. 

To address the need for lower costs and 

the fact that test times are being reduced 

to a theoretical minimum, multi-deviceunder-test 

(MultiDUT) solutions are 

required. 

MultiDUT is an attempt to bridge the 

price-performance divide by testing a 

number of devices in parallel. In essence, 

multiDUT aims to balance the physical 

limits of testing with the need to conserve 

capital resources and reduce the cost-oftest 

with higher throughput (Figure 2). 

MultiDUT, however, presents a number 

of other challenges: 

• RF Instrument Density 

• Loadboard Layout 

• Test Challenge 

• Processing and Packaging Challenge 

• Dimensional Challenge and Handler 

Mechanics 

Let’s look at each of these challenges in 

more detail. 

RF Instrument Density 

RF test solutions have evolved over recent 

years, just as the cell phone has evolved. 

In the past, RF testers were typically 

“rack-and-stack” systems assembled 

from components to address a specific 

testing need. 

The test industry, however, has also 

moved to higher levels of integration 

consolidating resources in the testhead, 

rather than in a big rack of equipment 

(Figure 3). 

The first RF systems, a little more 

than a decade ago, had only 12 ports 

built from several boxed, stand-alone 

instruments. Today, by contrast, it seems 


Figure 1. This is a typical block diagram for a wireless application. In the 

early 1990s, discrete components were used. By the late 1990s the RX 

and TX were integrated into an RFIC, as denoted by the circles. 

that just about every instrument has been 

integrated into a monolithic module. 

Density, which describes the number 

of instruments in a single module, has 

increased, thus allowing the assignment 

of dedicated RF resources to every device 

pin in a multi-DUT configuration. For 

example, some current RF test systems 

include as a minimum: 

• 32 RF ports 

• 4 Vector SG 

• 4 Receivers, and 

• 4 CW Stimuli 

Multiple instances of this capability can 

support up to 128 RF ports in a single 

test system. In the past it would have 

required a room full of racks to provide 

this type of capability. Today it is simply 

a few slots in the test head. 

Of course, RF density is a plus from 

the standpoint of delivering lots of testing 

options in one package. However, 

ATE RF density alone does not solve the 

multiDUT challenge. System vendors 

need to extend their solution to beyond 

the boundaries of ATE resources. 

Loadboard Challenges 

The next major DUT challenge is the 

layout of the loadboard. In fact, this 

may be the single 

biggest challenge in 

enabling effective 

multiDUT. 

Historically, test 

resources have been 

provided in focused 

areas (RF resources 

in one corner, digital 

resources in another, 

mixed-signal 

resources in yet a 

third, etc.). Having a 

performance board 

environment that provides 

all necessary 

resources adjacent to 

all the DUTs in a 

multiDUT setup is very beneficial; not 

only does this simplify the layout, it 

greatly improves measurement performance 

resulting in faster test times 

and improved yields. 

For example, in a quad solution with 

four devices under test, it is preferable 

to have all required resources readily available, 

adjacent to each DUT to minimize 

coupling and achieve better isolation. 

As noted, having dedicated resources 

for each DUT is critical. The alternative 

is to add switches or multiplexers on the 

loadboard, which also adds unnecessary 

complexity. The result is increased test 

time, reduced dynamic range, which 

also results in limiting yield. Furthermore, 

test program generation and checkout 

will become much more complex. 

The very nature of RF testing is changing, 

which also presents other new challenges. 

The days of measuring traditional 

parametrics and trying to correlate electronic 

characteristics to ultimate system 

performance are waning. 

Issues such as gain, noise figure, 

third-order intercept point (TOI) and 

black-box scattering parameters are still 

important, but they are no longer the 

main focus. 

Today, what really matters in the market 

is that the system-on-a-device (SoD) 

Figure 2. As test times continue to decrease, the 

added throughput from multiDUT solutions is the 

only alternative to lower cost. 

actually performs as it is designed: 

functionally. In the past, tests such as 

gain and noise were performed on RF 

devices; now the focus is simply on 

whether the cell phone functions as 

intended. 

For instance, if you have a device that 

will go into a cell phone, what you most 

want to know is that it won’t drop a 

call. That implies that first and foremost 

you need to test functional aspects of 

the circuit such as bit error rate (BER) 

and all the other things that fall under 

functional parameters. In essence, testing 

has become more closely aligned with 

the end product. 

As things continue to evolve there 

will be more and more functional tests 

and, necessarily, more emphasis among 

device makers on design for test (DFT) 

and built-in-self-test (BIST). 

MIMO Techniques 

Further complicating the test challenge, 

Multiple In, Multiple Out (MIMO) 

techniques, which allow antennae to 

process many incoming and outgoing 

signals simultaneously with development 

of true duplex functional radio tests, 

Figure 3. RF resources that were once built on a 

large rack are now integrated into a testhead-resident 

monolithic module. 

76 


Figure 4. Variety of socket layout for multiDUT 

solutions 

need to be tested by the tester in the 

way that they are actually used in the 

end product (i.e., functionally). 

At a minimum, functional tests from 

now on will likely include hybrid system 

level tests like: 

• adjacent channel power ratio 

(ACPR), sometimes called adjacent 

channel leakage ratio (ACLR)— 

defined as the ratio of the transmitted 

power to the power in the adjacent 

radio channel; 

• bit error rate (BER), and; 

• error vector magnitude (EVM) testing 

Challenges 

When it comes to packaging, the great 

benefit of Moore’s Law is that we can now 

integrate much more functionality onto 

a single die. However, higher levels of 

integration also create other challenges. 

For instance, you can’t isolate key system 

components from one another. 

Therefore, if you have a transmitter 

running at full output, the receiver 

“next door” still has to remain sensitive. 

In response, engineers have developed 

solutions such as system-in-package 

(SiP). To deliver a solution, you need 

those multiple chips in a single package 

using a variety of interconnective technology 

to ensure functionality. 

Still, this is by no means the end of 

testing challenges. For instance. pitch 

dimensions—currently hovering around 

0.4mm—are continuing to get smaller. 

With such a small space between contacts, 

the possibility of short circuits has 

never been greater. In addition, the 

reduced use of metals, such as lead in 

packaging, has led to what is sometimes 

called “gumminess”- packages 

are softer, stickier and more prone to 

poor electrical performance that needs 

be verified through tests. 

Handler Mechanics 

The evolution of packaging translates 

into tremendous dimensional challenges. 

Early on, we had the large SOIC 

(small outline IC); the familiar plastic, 

rectangular, surface-mount chip package 

with gullwing-style pins. Now, package 

sizes are being driven by the wide 

range of form factors and configurations 

present in the market. 

Needless to say, some package types 

are particularly challenging for test. The 

big issue is the limited space on the performance 

boards and the ever-increasing 

drive for higher levels of test parallelism. 

For instance, LCC and QFN were 

great in terms of providing more 

options for electronic design solutions, 

but were much tougher for multiDUT 

applications. 

Robotic handlers in high-volume 

applications involving LCC and QF had 

difficulty meeting volume requirements. 

Also, while the smaller package took-up 

less space on the load board, it also created 

a much bigger challenge in terms 

of signal routing. As signals converged, 

electrical isolation problems emerged. 

Pick-and-place handlers were also 

facing difficulties, especially with regard 

to x-y axis pitch lengths and pin-one 

rotation issues. 

The open area on the guide plate is 

the fundamental limitation. Today we 

are dealing with 1x4 and 2x2 quad-DUT 

configurations. In the near future, however, 

we will need 8x2 and 16x1. 

What was really needed were handlers 

that could space out parts more to help 

solve the load board issues. That’s part 

of the current challenge. 

Reality Testing 

Our industry can no longer afford to be 

Figure 5. Examples of parametric component tests 

myopic with regard to our testing challenges. 

The practical limits described here 

are real. Business as usual won’t work. 

We must recognize the limits 

imposed by RF instrument density, 

loadboard layout issues, processing and 

packaging problems, test challenges, and 

the difficulties posed by package dimensions 

and the mechanical capabilities of 

handlers. 

We believe the solution lies in broadening 

the focus of the test cell. It’s time 

to look at the test cell as a whole system, 

including aspects of device design, so 

that we can begin to view the complicated 

interrelationship among all these 

elements in terms of a system and a 

testing solution. 

Only with this kind of thinking can 

the electronics industry hope to meeting 

the demands for quality and productivity 

that are inevitable and necessary. i 

Mr. Lum joined 

Advantest in 2006 as 

an SoC product engineer. 

After receiving 

a BSEE from Arizona 

State University, he 

joined Texas Instruments, 

where he 

developed microwave wafer and module 

test systems for military applications. He 

later helped launch TI’s RF/wireless business. 

After TI, he joined HP/Agilent as an 

applications engineer and became an 

applications engineer district manager. 

[a.lum@advantest.com] 


TEST PATTERNS 


knowledge of hardware and electronics 

with just enough programming and 

EDA skills (once EDA had been invented) 

to make it work at all. 

Many of these folk have intimate relationships 

with their oscilloscopes, know 

what TDR stands for, and can always 

tell when an NCG has tried to use a soldering 

iron on a load board. 

We VETs believe that if we needed 

text messaging, we wouldn’t have 

invented laptops and e-mail. 

So how do you choose between NCGs 

and VETs The VET understands the 

issues involved in bringing a device out 

of the design lab and onto the test floor. 

The NCG may actually understand the 

EDA-to-test program portion well, due 

to freshly minted skills in data management 

and software tool usage. 

Get both of them, but hire more 

VETs than NCGs. For high-performance 

analog or mixed signal test, it may 

be difficult to find an NCG with the 

right hardware background (“Uh, which 

one is the oscilloscope”). 

Is your budget challenged If so, the 

VET is still your choice and you may 

want to consider hiring that VET as a 

consultant instead of a full time 

employee. In digital designs, however, 

you can get by with a greater number of 

NCGs relative to VETs since these tend 

to be all about the EDA. i 

Mr. Sakamoto is a VET in test with more 

than three decades in the industry since 

he was a NCG. He was most recently 

CEO of Inovys. 

Are you the next 

Ernest Hemingway 

or John Steinbeck 

Chip Scale Review is looking for 

industry experts who like to write! 

If you’re a budding Hemingway or 

Steinbeck, please consult the 

Suwanee Review or the New Yorker. 

However, if you will share your 

expertise in semiconductor packaging 

or test with other readers, 

we would like to see an abstract! 

Please contact the editor at 

chipscale@gmail.com for details. 

78 


SA N JOSE, CALIFO R NIA 

O C T O B E R 1 3-1 6, 2 0 0 8 

INDUSTRY EVENTS 

DATE EVENT WEB SITE LOCATION 

July 15-17 SEMICON West semi.org San Francisco 

Aug. 18-22 IEEE EMC Symposium emc2008.org Detroit, Mich. 

Aug. 19-20 SMTA International smta.org Orlando, Fla. 

Sept. 2-5 ElectronicIndia http://global-electronics.net Bangalore, India 

Sept. 8-9 KGD Packaging Workshop napakgd.com Napa, Calif. 

Sept. 8-10 EOS/ESD Symposium esd.org Tucson, Ariz. 

Sept. 9-11 MedTec China medtechchina.com Shanghai, China 

Sept. 9-11 SEMICON Taiwan semicontaiwan.org Taipei, Taiwan 

Sept. 9-11 Int’l. IC-Taiwan Expo english.taiwan.iicexpo.com Taipei, Taiwan 

Sept. 9-12 GlobalTRONICS globaltronics.com.sg Singapore 

Sept. 10-11 Orange County Electronics Show oceshow.com Costa Mesa, Calif. 

Sept. 10-12 Elcomp India elcompindia.com New Delhi, India 

Sept. 15-19 PCB West pcbwest.com Santa Clara 

Sept. 17-18 RF and Microwave Packaging—IMAPS imaps.org San Diego 

Sept. 17-19 China Int’l. IC Industry Exhibition ic-china.org Shenzhen, China 

Sept. 23-25 Assembly Tech Expo atexpo.com Rosemont, Ill. 

Sept. 24-25 MedTec Ireland medtecireland.com Galway, Ireland 

Sept. 24-27 Philtronics globallinkph.com Manila, Philippines 

Sept. 24-25 IPC Midwest Conference & Expo ipcmidwestshow.org Schaumburg, Ill. 

Sept. 30-Oct. 4 CEATEC ceatec.com Makuhari, Japan 

Oct. 1-2 NanoTx nanotx.biz Dallas, Texas 

Oct. 7-11 Taitronics Components taipeitradeshows.com.tw Taipei, Taiwan 

Oct. 7-9 SEMICON Europe semiconeuropa.semi.org Stuttgart, Germany 

Oct. 12-17 China Hi-Tech Fair ELEXCON elexcon.com Shenzhen, China 

Oct. 13-16 Electronic Asia electronicasia.com Hong Kong, China 

Oct. 13-16 Int’l. Wafer Level Packaging Conference iwlpc.org San Jose 

Oct. 14-18 Korea Electronics Show kes.org Seoul, Korea 

Oct. 21-23 Mexitronica Expo mexitronica.com Guadalajara, Mexico 

Oct. 22-23 Medical Design & Manufacturing memminn.com Minneapolis, Minn. 

Nov. 2-6 ISTFA—Testing Failure Analysis edfas.org Portland, Ore. 

Nov. 2-6 IMAPS 2008 Symposium imaps.org Providence, R.I. 

Nov. 4-6 China SMT Forum—Intex chinasmtforum.com Shanghai, China 

Nov. 4-8 Factory Automation ASIA factory-automation-asia.com Shanghai, China 

Nov. 5-8 MEMS Executive Congress memsindustrygroup.org Monterey, Calif. 

Nov. 10-12 Bohai Electronics Week bohaielectronics.com Tianjin, China 

Nov. 11-14 Electronica electronica.de Munich, Germany 

Nov. 19-21 Embedded Technology Japan embeddedtech.net Yokohama, Japan 

Dec. 2-5 Printed Electronics USA printedelectronics.idtechex.com San Jose 

Dec. 3-5 Int’l. PCB & Electronics Fair hkpca-ipc-show.org Dongguan, China 

Dec. 3-5 SEMICON Japan semiconjapan.org Makuhari, Japan 


ADVERTORIAL 

Introducing FC M BGA (Flip Chip Molded BGA) 

Amkor’s Evolutionary Packaging Technology 

Amkor Technology Inc.’s 

FC M BGA is the evolution of the 

SuperFC ® high performance flip 

chip solution. The FC M BGA 

packaging process has been 

simplified from the SuperFC ® 

process by eliminating the capillary 

underfill process (CUF) and 

utilizing a molded underfill (MUF). 

There are several advantages 

that can be realized as a result of 

this transition. These include a 

simplified process flow, reduced 

body size, improved electrical performance, 

improved reliability, and 

better warpage control. 

By eliminating CUF from the 

package construction process, 

keep-out areas required for CUF 

are eliminated. As a result, 

FC M BGA allows reduced body 

size and improved board real 

estate use, by allowing closer 

spacing between passives and the 

flip chip die. 

One of the more substantial 

benefits of the new process is 

better electrical performance. The 

improvement is due to the ability 

to move passive components 

(such as capacitors) closer to the 

flip chip die. This benefit also 

makes FC M BGA well-suited for 

multi-chip packages with high 

levels of integration. 

Warpage control is another key 

improvement driven by the MUF 

process. Increased electrical 

requirements are pushing substrate 

technology into thinner 

cores while increased I/O density 

is driving larger substrate sizes. 

Warpage control for thin, large 

substrates is challenging. 

FC M BGA provides a more rigid 

structure for thin core substrates. 

This allows for better final package 

coplanarity. FC M BGA also 

extends the die size range for 

bare die packages, which typically 

need a stiffener and/or lid to meet 

JEDEC coplanarity requirements. 

As IC fabrication nodes continue 

to decrease in size, fabrication 

layers become more fragile. 

Traditional CUF packages are 

reaching reliability limits. FC M BGA 

allows the use of MUF materials 

where historically CUF materials 

were required. MUFs are higher 

filler content and lower moisture 

absorption than CUFs. Coupled 

with finer filler particles these 

materials will allow FCBGA packaging 

for ultra low k nodes. 

FC M BGA is produced in an 

exposed die configuration. 

Advanced molding techniques 

coupled with next generation 

mold compounds are used to produce 

FC M BGA. The exposed die 

configuration not only maintains 

the excellent thermal performance 

of bare die FCBGA, but it 

enhances as well, by providing a 

support surface around the die for 

direct heat sink attach. 

For small to medium die sizes, 

8-14mm, FC M BGA provides excellent 

coplanarity without the need 

for a stiffener/lid or formed lid 

configurations. For larger die 

sizes, FC M BGA offers the flexibility 

of attaching a lid. This provides 

transparency for SuperFC ® customers. 

The flexibility of this new IC 

packaging technology makes it 

applicable to a wide array of 

devices including ASIC / FPGA, 

GPU and CPUs. FC M BGA provides 

the package solution for networking 

and storage, gaming, broadband 

communications, computer, 

multimedia markets, etc. 

The combined impact of the 

benefits mentioned here would 

suggest that FC M BGA will have a 

significant impact on packaging 

technology in the years to come. 

www.amkor.com 

VISIT AMKOR TECHNOLOGY ONLINE 

FOR LOCATIONS AND TO VIEW THE MOST 

CURRENT PRODUCT INFORMATION. 

Visit us at SEMICON West 2008, Booth 7352, 

West Hall, Level 1, to learn more about FC M BGA. 

80 


FC M BGA 

Flip Chip Molded BGA 

INTRODUCING 

FC M BGA 

Amkor’s Evolutionary Packaging Technology 

IMPROVED use of board real estate 

IMPROVED warpage control 

IMPROVED reliability 

Amkor’s FC M BGA is the evolution of the SuperFC ® high performance flip chip solution. The packaging 

process has been simplified by replacing capillary underfill with molded underfill, thus allowing: 

 

 

 

FC M BGA is applicable to a wide range of chip and body sizes and backwards compatible with SuperFC ® , 

FCLBGA and FCBGA. 

Visit us at 

CURRENT 

Bare Die 

Single Piece Lid 

2 Piece Lid 

FC M BGA 

or 

Booth 7352 

West Hall 

Level 1 

to learn more 

about FC M BGA 

and our new 

breakthrough 

leadframe 

package 

FusionQuad 

VISIT AMKOR TECHNOLOGY ONLINE FOR LOCATIONS AND 

TO VIEW THE MOST CURRENT PRODUCT INFORMATION. 

ENABLING A MICROELECTRONIC WORLD ® 

www.amkor.com

ADVERTORIAL 

Aries Electronics, An Industry Leader 

in Interconnection Products 

Founded in 1972, Aries 

Electronics Inc. has introduced 

a wide range of highly 

innovative interconnection 

products and has made major 

technology inroads in the 

high-temperature socket and 

flexible cable markets. 

With the recent relocation of 

its corporate headquarters from 

Frenchtown N.J. to a new 

50,000-square-foot facility in 

Bristol, Pa., Aries remains a U.S. 

manufacturing company, ensuring 

quality control and costeffective 

products. 

Products 

Aries has developed and 

patented several concepts for state-of-the art test 

sockets available in standard (up to 1 GHz rating) 

and high frequency rated versions (rated up to 18 

GHz) ideal for CSP devices. 

Aries provides ZIF test sockets for DIP, PGA, PLCC, 

SOIC and other devices; high frequency test and 

burn-in sockets; DIP, SIP and special purpose sockets, 

headers and covers; programmable devices; jumper 

and cable assemblies; flexible cable products; and 

specialty electronic connectors. 

The company has revolutionized the connector 

industry with its Correct-A-Chip line of “intelligent 

connectors” that incorporate both passive and 

active components as well as adapters that allow the 

use of one termination style on a board designed for 

a different termination style. 

Aries’ sockets currently achieve pitches as low as 

0.40 mm, and this year the company will release a 

new spring probe test socket technology that 

enables sockets to achieve pin pitches as low as 

0.30 mm. In addition, Aries is planning the production 

of a 0.20 mm spring probe test socket that reaches a 

frequency rating as high as 18 GHz, slated for launch 

in 2009. 

Customer Service 

With a strong focus on customer service, Aries maintains 

a comprehensive guide on its website that 

includes a “check stock” feature complete with current 

pricing, so customers can easily verify if a part is 

available for purchase. 

82 


ADVERTORIAL 


The Leading Provider of IC Assembly & Test Services in the U.S. 

CORWIL was founded in 1990 to provide high 

quality and responsive IC assembly and test services 

to the semiconductor, OEM electronics, military, 

aerospace, and medical industries, and has served 

over 1000 customers. Excellent quality, superior 

service, and technical capability have been the 

hallmarks of its success. 

CORWIL has emerged as the premier and most 

diversified US-based provider of IC assembly and 

test services, including wafer thinning and dicing, 

optical inspection, and complex module assembly. 

To support growth, CORWIL recently designed and 

constructed a new facility in the heart of Silicon 

Valley, California. 

CORWIL Technology Corporation.’s headquarters in Milpitas, Calif. 

CORWIL’s IC assembly capabilities range from 

QFN’s to complex BGA’s and multi-chip-modules. 

CORWIL also assembles and tests ceramic packages 

including full mil-spec process flows and environmental 

screening. CORWIL is certified QML for mil-spec 

(Level Q) and space (Level V) IC assembly and test, 

and is ISO 9001:2000 registered. CORWIL is the 

manufacturer of choice in high cost of failure and 

high reliability market segments, and is fully integrated 

into its customers’ manufacturing operations. 

CORWIL is the highest volume subcontractor of 

wafer dicing, visual inspection, and die pick & place 

services in the U.S. And to address the growing 

need for exotic wafer materials, such as sapphire, 

gallium nitride, gallium arsenide, and silicon germanium; 

CORWIL has developed proprietary processes to 

efficiently process these materials while achieving 

high quality and production yields. 

For prototyping and new product development, 

where time-to-market is of utmost importance, 

CORWIL delivers as fast as 4 hours. CORWIL is 

unsurpassed in producing highly complex products 

such as Flip-Chip, wire-bonded BGA, and chip-scale 

devices with thousands of bumps or wire bonds. 

CORWIL is the sole source provider of prototyping 

services for many fabless companies, integrated 

device manufacturers with wafer fabs, and OEM’s. 

CORWIL’s technical leadership has made it the first 

subcontractor in the U.S. in many technologies such as 

BGA assembly, ultra-fine pitch wire bonding, 12 inch 

wafer dicing, and assembly of complex RF modules 

and multi-chip-modules such as SIP (system-in-package). 

Long recognized as the industry technical leader in 

high volume, chip-free and fast turn-around wafer 

dicing, CORWIL’s proprietary Dice-Before-Grind 

(DBG) process produces the highest quality die in 

the world, particularly for ultra-thin wafers. 

To remain best-in-class, CORWIL’s engineering 

experts focus on specific processes such as wire 

bonding, flip-chip assembly, plastic molding, wafer 

thinning and dicing, and vision inspection, so CORWIL 

continues to provide the leading edge services its 

customers expect. 

1635 McCarthy Boulevard 

Milpitas, CA 95035 

Phone: 408-321-6404 • Fax: 408-321-6407 

info@corwil.com • www.corwil.com 


ADVERTORIAL 

Manufacturer’s Rep Pacific Gate Technologies 

Provides Superior Service from Silicon Valley 

Pacific Gate Technologies was founded 

in 2006 to fill the large void of personal 

service in technical sales representation. 

Located in the heart of Silicon Valley, 

but with nationwide sales and service, 

Pacific Gate represents a diversified group 

of companies. 

Pacific Gate is headed by Danny R. Fields, 

a 30-year veteran of the semiconductor 

assembly and packaging industry. 

Prior to founding Pacific Gate, Mr. Fields 

was sales director for i2a Technologies/IPAC 

in San Jose. Earlier, he held increasingly 

responsible posts at Amkor Technology Inc. 

and Pantronix. 

Danny Fields (left) with Manoj Nachnani, ESI president. 

The Products and Services We Represent 

Christel, Singapore 

Christel provides the entire 

Christel 

spectrum of activities 

required to develop a complete product of the 

finest quality. These include: mechanical-, electronics 

and software design and development. 

Minami Co., Ltd. Japan 

Minami is a world-class 

developer and manufacturer 

of screen printers, reflow ovens and inspection 

equipment for the PWB and semiconductor 

communities. 

Enabling Solutions 

Enabling Solutions, San 

Jose, is a “best-in-class” 

engineering company recognized for one-stop 

solutions for SiP and high-speed signalintegrity 

design-related services. 

PTA 

Packaging Foundry 

PTA, Malaysia 

PTA is a diversified 

manufacturer providing 

EMS, assembly of chipon- board, chip-on-film, 

system-in-package and boxbuild. 

3697 Millplain Court, San Jose, CA 95121 

Phone: 408/705-4721 Cell: 408/393-3615 

Fax: 408/705-4737 

www.pacgate-us.com 

e-mail: danny.fields@pacgate-us.com 

84 


What Are Your Current Burn-In Sockets Missing 

Plastronics answers burn-in and system level socket limitations with 

its new H-Pin ® socket technology. 

What Are Your Burn-In 

Sockets Missing 

Burn-in and OEM sockets historically 

utilize single-piece stamping 

inserted into an injection molded 

socket. This requires a large initial 

capital expense for the tools, but 

provides a high volume, economical 

solution for large quantity purchases. 

Myriad issues, however, 

are on the horizon that singlepiece 

stamping cannot solve. 

These include: 

1. An increased need for contact 

travel to 0.7mm for large warped 

array packages, while maintaining 

a flat or near flat spring rate 

(force) 

2. Excellent electrical characteristics 

for higher frequency devices 

3. Greater current carrying 

capacity for power devices and 

processors 

4. Ability to withstand temperatures 

up to 200°C for under the 

hood applications 

ADVERTORIAL 

H-Pin ® Technology 

The H-Pin ® is a forward thinking 

concept invented as a high volume 

solution with exceptional mechanical 

and electrical performance. 

Utilizing high volume CuBe 

stamping technology, combined 

with a SS spring for mechanical 

travel, the H-Pin ® has a working 

range up to 0.7mm with a flat 

spring rate, can be utilized up to 

15GHz with -1dB loss, carry up to 

4amps of current, and can withstand 

temperatures up to 200°C. 

Automation was developed to 

completely assemble the contact 

pin onto a stamped lead frame, 

which then can either be singulated 

for hand loading or left on 

the lead frame reel and put into an 

automated loading system. When 

left on the lead frame reel, the entire 

process from raw material to 

finished socket requires no human 

contact to the H-Pin ® . 

Maximized Performance Made 

Affordable 

Increased signal speed: 

0.5mm pitch 15.7 GHz @ -1dB 

1.0mm pitch 10.5 GHz @ -1dB 

More Power: 

0.5mm pitch 

1.0mm pitch 

2.9 amps free-air 

4.0 amps free-air 

Low Inductance: 

0.5mm pitch 0.88nH self inductance 

1.0mm pitch 0.93nH self inductance 

Stable Resistance: 

 

 

A typical 10,000 cycle burn-in 

socket has 0.25mm of contact 

travel, a -1dB loss around 500 

MHz, can carry about 0.5amps 

with a 30°C temperature rise, 

and, if using CuBe contact metal, 

has a temperature rating of 

150°C. 

OEM sockets typically have the 

same contact travel with improved 

electrical characteristics 

of 1amp+ and 5 GHz frequencies, 

but are typically rated for only 25 

cycles and have a temperature 

rating of 100°C or less. 

www.PlastronicsUSA.comm 

US Patent #7025602 

Visit us at SEMICON West 2008 

West Hall, Level 1, Booth #7437 

to learn more. 

Higher Temperatures: 

180+°C 

Increased Stroke: 

0.5mm pitch 0.43mm of travel 

1.0mm pitch 0.80mm of travel 

Replaceable Pins: 

Repair - Replace - Reuse 

You Asked. We Listened. 

The H-Pin ® . 

Often companies introduce new 

ideas based as a monolithic concept; 

technology, cost or manufacturing. 

The H-Pin ® is a market 

driven technology based on customer 

inputs carrying wide opinions 

of the entire market and thus 

is an idea that impacts technology, 

cost, and manufacturing. 


ADVERTORIAL 

RoHS Exemption... A Blessing or A Curse 

RoHS exempt high reliability OEMs 

breathed a sign of relief for not 

having to go through the grind of 

revising their processes and material 

to be RoHS compliant. However, this 

was short lived because of supply 

chain disconnects in the availability 

of non-RoHS devices. Consumption, 

in terms of unit volume for Sn/Pb, is 

small compared to the volume going 

into the builds of consumer and 

commercial product.This situation 

creates an opportunity for component 

manufacturers looking to 

increase profits by streamlining their 

cost and production operations by 

discontinuing the Sn/Pb option of a 

part number (P/N) when unit 

volumes fall below a preset ratio of 

the total volume. Bills of materials are 

being transitioned to obsolete and 

legacy parts outside the control of 

the OEMs and at a rapid pace. 

In today's market, most signs point to one 

destination...the Pb-free route. 

Premier provides you other avenues. 

Premier Semiconductor Services gives device manufacturers and 

high reliability users real alternatives. 

Pb-Free to Sn/Pb Conversion - for RoHS exempt applications 

Sn/Pb to Pb-Free Conversion - for legacy products/RoHS compliance 

Sn/Pb Sphere Attach - for LGA‘s 

Device removal & refurbishment – for revisions and PWBA rework 

Premier has developed a proprietary process for stripping Pb-free 

BGAs mitigating inter-metallic layers, as well as emerging as a 

best-in-class provider of solder dip, automated inspection, XRF 

testing, programming, electrical testing, baking, marking, and tape 

& reel services. Premier's process capabilities include most packages 

including BGA microprocessors and wafer-level, chip scale 

packaging for ball sphere sizes from 200 microns and up. 

Premier is a trusted partner to high reliability telecommunications, 

military and medical industries by providing this turnkey solution. 

For more information about this and all our services, visit www.PremierS2.com 

The life cycle for a military product 

generally takes over two years for 

the design and initial deployment, 

followed by a production life cycle of 

over 10 years and a repair/warranty 

cycle of 20 plus years. A redesign to 

include an alternate part number is 

no easy task due to redesign review, 

validation and reliability testing. 

In addition, exempt OEMs are 

exposed to other problems caused 

by some manufacturers not changing 

P/Ns once the Sn/Pb is obsolete.The 

end result too often is mixed reels of 

RoHS and non-RoHS product. 

Unfortunately, exempt OEMs are 

many times left with only one choice 

and that is Pb-free components.This 

is clearly not optimal due to some 

of the reliability concerns associated 

with Pb-free components. Reflow 

profiles, thermal stress, MSL, tin 

whiskers, tin pests, brittleness, voids 

and thermal mismatch are some of 

the reliability problems that can’t 

be ignored and can’t be managed 

in the absence of the specific Sn/Pb 

component. Premier Semiconductor 

Services bridges this gap and gives 

the exempt OEMs back their freedom 

to choose and their ability to put the 

Sn/Pb proven reliability back in their 

builds. 

Solder joint converted from SAC405 to SnPb, 

utilizing Premier’s proprietary reball process 

showing proper joint structure. 

86 

PREMIER SEMICONDUCTOR SERVICES, LLC/LP 

US HEADQUARTERS TEL 480-736-1970 

EMAIL: sales@PremierS2.com 

www.PremierS2.com www.PremierTest.com 

Value-add Solutions in Final Manufacturing and Test 


For more information about Premier’s 

Sn/Pb conversion services, please 

send email to: sales@PremierS2.com 

or call 480-736-1970.

SOCKETOLOGY 

What’s Next for Socket Technology 

By Mike Fedde, Guest Contributor, Ironwood Electronics [ironwoodelectronics.com] 

What’s on the horizon for 

burn-in and test sockets 

That’s a question that 

every user and provider of sockets 

must ask themselves repeatedly. 

The next technologies will be both 

extensions and improvements on the 

technologies and techniques used today, 

as well as lithographic techniques that 

result in a contactor partially originated 

with technologies used in PWB and IC 

masking. 

Contactors embedded in (or with) 

elastomer will also improve in quality 

and density. Spring pins have been 

improved to below 0.4mm pitch, and 

the bending beam sockets handle very 

low pitches as well. 

Lithographic Technologies 

The lithographic technologies, which 

are being implemented with PWB technologies, 

use polyimide film along with 

secondary processing, adding contactor 

elements in an assembly. 

Anisotropic connection methods 

embedded in elastomer also are improving 

with the embedded contactors getting 

both smaller and denser. New functions 

added to the socket are emerging in 

what some call “Smart Sockets” with 

features over and above providing just 

a contact mechanism between chip and 

PWB. 

The inevitable difference in electrical 

characteristics will result in a segmentation 

of contactor type by application. 

The bending beam used in most of 

This high-performance LGA socket operates at bandwidths up to 40GHz. 

today’s burn-in sockets will continue to 

dominate that field. 

Spring pins will dominate production 

test, while lithographic and elastomerbased 

contactor sockets will make inroads 

in both of these applications, as well as 

providing platforms in applications above 

10GHz to 40GHz. 

‘Smart Sockets’ 

The “Smart Sockets” will provide capabilities 

such as directly heating and 

cooling ICs as part of the test cycle 

instead of using ovens. Other functions 

will be incorporated into sockets to 

eliminate other, extra equipment in the 

test environment. 

The spring pin sockets will have strong 

competition from thin-film based interposers 

such as diamond particle interconnects 

and silver-filled elastomer. As 

the demand for these sockets increases, 

the film-based interposer sockets will be 

more affordable and less expensive than 

spring pin technology. 

You will also see more test sockets 

made from film-based interposers 

because of the higher speed (40GHz), 

maximum operating temperature above 

burn-in temperature and the other 

excellent electric interposer properties. 

The maximum operating temperature 

requirement has steadily increased over 

the years with some applications demanding 

up to 260°C. 

Material Properties 

Higher temperature requirements will 

put pressure on socket- and interposer 

materials to improve on material properties 

including dimensional stability, 

low moisture absorption, and TCE mismatch. 



MY VIEW 


Furthermore, some of the external test 

facilities do not provide certain information 

as to the actual tests performed, 

equipment used, etc., stating that they 

cannot provide this information 

because it is proprietary. This creates 

even more uncertainty for the customers. 

Time Consuming and Expensive 

Detecting counterfeit components is a 

tough process that can be time consuming 

and expensive. However, if someone 

puts in the time and effort, there are 

many things that can be done to help 

minimize counterfeit product. 

First, educate yourself. There are various 

resources like the IDEA-STD-1010-A 

for inspection of electronic components 

that can be used as a reference guide. A 

good test house can also be invaluable 

to help set up a strategy for counterfeit 

detection for your company. 

In an effort to find a good test house, 

don’t be afraid to ask a lot of questions 

and take the time to visit. A credible test 

house should allow you to tour their 

facility and be willing to share testing 

and equipment information with you. 

If you get a quote that seems too 

good to be true for one of those “magic 

pieces of paper,” it probably is. In the 

same vein, in selecting sourcing partners, 

do your homework by visiting 

them. There are some extremely good 

independent distributors that have 

taken very credible steps to eliminate 

counterfeit product. Have them explain 

and show you what strategy they have 

implemented. 

Look in the Right Places 

It is ironic that one of the main benefits 

of sending product manufacturing 

overseas was the reduction in product 

cost. This is also the same set of circumstances 

that results in a significant offset 

to that price reduction in the form of 

additional counterfeit-related costs to 

the marketplace. 

People are looking for answers to this 

difficult issue. There is help out there if 

you look in the right places. i 

Mr. Loaney is CEO of Premier Semiconductor 

Services. [premiers2.com] 

Did You Know Chip Scale Review 

is now offered in a digital format with 

a powerful search engine! 

Expertise in Electronics and 

Semiconductor Industries 

The Law Firm of Mintz Levin Announces the Opening of its New Offices 

in Palo Alto and San Diego to Better Serve its Clients 

Intellectual Property Law | Licensing Law 

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88 


SOCKETOLOGY 


There will also be a demand for new 

performance materials, such as plastics, 

to be used in sockets at higher temperatures. 

Spring pin manufactures will 

have to increase the maximum operating 

temperature and reduce the total 

height on the probes. 

Currently, the number of contacts 

on film-based interposers for BGA 

sockets is limited because of co-planarity 

requirement. There will be 

improvements in those interposers, 

which will eventually be used in high 

temperature burn-in sockets for all 

BGA chips, including higher pincount 

BGAs. 

Next-generation test sockets will 

have to handle multiple chips horizontally 

in an array (DDR RAM), or 

vertically with stacked 

interposers/contact elements (packageon-package 

memory chips). 

Currently, the number of contacts on film-based interposers for BGA 

sockets is limited because of co-planarity requirement. 

The socket will have to be open top 

or will have to have a hole in the middle 

that will allow probing of die or direct 

injection of heat or cold air 

Tiny Pads 

Some optical device manufactures 

want to use tiny LGA pads (0.08mm 

diameter) on fine pitch (0.38mm to 

0.5mm). These sockets will have to guide 

the optical devices very precisely to 

ensure good contact with the tiny pads. 

Socket manufactures will face new 

challenges with the requirements for 

finer-pitch applications, smaller ball 

diameters, smaller pad sizes, minimum 

and maximum operating temperatures, 

higher number of insertions, 

less maintenance/cleaning, better 

electrical properties, and higher 

speed requirements. i 

Mr. Fedde is president and CEO of 

Ironwood Electronics. Contact him at 

mikef@ironwoodelectronics.com. Ranjit 

Patil, Ironwood’s R&D director, contributed 

to this article. 




could find an ad for Lyon’s ham and egg 

breakfast special on a page of Hamlet! 

Not to be left standing in the dust, 

Microsoft and Yahoo, Google’s main 

competitors, also plan to go into the 

book-scanning business. 

Scanning these books is not a cheap 

nor easy task. Jonathan Band [plagiary. 

org] estimates it will cost Google a minimum 

of $750 million to scan 30 million 

books, and could cost much more. 

Google has not released any cost figures, 

but Microsoft, according to Band, 

says it will spend $2.5 million to scan 

100,000 books in the British Library. 

By the time the Google project goes 

online, there could be a few more “gotchas.” 

Supersize Me! 

It’s really (almost) here—the fabled 

450mm (18-inch) wafer, the 

next leap in the evolution of 

semiconductor wafer sizes. 

With three of the largest 

companies in the semiconductor 

industry putting their 

stamp of approval on a 2012 

timeline for this monster size, 

the path of progress is 

inevitable. 

The larger size will bring its 

share of benefits—economically—but 

it will also require 

human and machine handlers 

that are bulked-up. If you 

make containers for wafer 

shipping and storage, however, 

you’ve got to be a happy 

camper! Is 450mm the outer limit of 

wafer size We’ll have to wait and see. 

This is a 450mm (18-inch) wafer populated with memory devices, 

the next step in the supersize sweepstakes, (Of course it’s really a 

pizza; we we didn’t have any wafer photos immediately available). 

Is 900mm (36-inches) the next frontier Check with us later! 

Meanwhile, jump to our news pages to 

read more about it. i 

SRO – Solder 

Reflow Ovens 

Perfect reflow soldering 

Rapid thermal annealing under 

controlled atmosphere, vacuum 

and pressure 

Perfect solder joints, no voids 

Also available 

PEO –Semiconductor 

Process Furnaces 

U.S. and Canada 

Representative: 

Please contact atv@pactech-usa.com or call 

408-588-1925 

www.pactech.de 

90 


Centipede Systems Develops Socket for Camera Chip ICs 

San Jose—Centipede Systems has developed 

a new optical socket suitable for testing current 

and next-generation chips used in wafer-level 

camera modules. 

The initial optical socket entry is part of 

Centipede’s Centurion product line. It is 

offered in a clamshell configuration for an 

individual IC. Currently, Centipede’s optical 

sockets with a grid pitch as small as 0.4mm 

are available. 

Testing camera chips requires that the surface 

of the device be held accurately in the optical 

plane without deviation or deflection caused 

by contactor forces, Centipede observes. 

To ensure accuracy, Centipede’s optical 

sockets align a datum plane on the chip’s surface 

to the lens or optical system with minimal 

stress on the chip. 

“Most existing test socket technology is 

about a half century old and incapable of 

testing complex optical chips,” notes Dr. Thomas 

H. Di Stefano, president of Centipede Systems. 

“Although our initial optical sockets are for 

testing single camera chips, sockets for testing 

arrays of camera chips are under development 

in the Centipede Labs,” he added. 

[centipedesystems.com] 

Lens (Optional) 

Gimbaled Baffle 

Clamshell 

Camera Chip 

Low Force Contactor 

This schematic illustrates the construction of the 

Centipede Systems optical socket. 

Vacuum Instruments Intros 

Production Leak Detector 

Ronkonkoma, 

N.Y.—Vacuum 

Instrument Corp. 

has added the MS-50 

UFT,a fully automated, 

high-production 

He leak detector 

for testing the hermeticity 

of sealed The MS-50 UFT He leak 

microelectronics. detector 

The unit features 

an integrated flush-mounted test cup, which 

initiates an automated test cycle sequence 

when closed by the operator. Unique UFT 

recipes allow for specific configuration of test 

parameters. 


Keyence Color 3D Microscope Simplifies Surface Analysis 

MX100IR – Automatic 

Desktop Wafer Inspection 

Woodcliff Lake, N.J.—Keyence has introduced 

the VK-9700 color 3D laser-scanning confocal 

microscope, which the company says combines 

the capabilities of SEMs and non-contact 

profilometry with the simplicity of a conventional 

microscope. 

Major features include an 18,000x magnification 

and 0.001µm precision, 3D imaging 

and “superior color performance with operational 

simplicity.” 

The instrument performs a variety of noncontact 

3D measurements that include surface 

profile, roughness, 3D and comparative 

measurements. 

The system’s 3D display operates with the virtual 

trackball method and the use of a computer 

mouse to control the viewing angle, lighting 

angle, zoom level and z-axis height. Three-dimensional 

images may be illuminated with pseudolight 

when displayed on the screen. [keyence.com] 

High accuracy inspection 

of bare wafers and MEMS 

Viscom’s new desktop system 

MX100IR with its patented Si-Thru TM 

technology inspects bare wafers, 

chips, MEMS, wafer bonds, SOIs 

and FlipChips. The wafers can 

be composed of silicon, gallium 

arsenide, III-V compounds or other 

semiconductor materials which are 

transparent to the wavelength in 

the near infrared range generated 

by the highly efficient scalable 

Si-Thru TM illumination. Combined 

with the very high camera resolution 

and advanced software algorithms 

the MX100IR provides unique defect 

detection capabilities of surface defects 

as well as embedded defects. 

See us at Semicon West, July 15-17 

West Hall - Level 1, Booth No. 7347 

Keyence’s VK-9700 microscope offers 18,000x 

magnification. 

CAD Design Software 

Claims Design Time Win 

San Jose—CAD Design Software says a special 

LTCC design and Gerber package prepared 

for a prime defense contractor has reduced 

tooling generation time for complex ceramic 

designs from 40-80 hours to 2-8 hours. 

The LTCC automation functionality, part of 

CDS’ Electronic Package Designer software suite, 

is now available in CDS’ Master PCB, Master 

IC Packaging Suite,and the Hybrid/MCM 

Design Suite. [cad-design.com] 

Nextreme, Princeton Lightwave 

Work on Next-Generation Sensors 

Durham, N.C.—Nextreme Thermal 

Solutions and Princeton Lightwave, 

Cranbury, N.J., have agreed to jointly develop 

a SWIR focal plane sensor using “extremely 

efficient” thermoelectric cooling. 

[nextreme.com] 

92 


Viscom’s MX100IR Inspection System Fits on Your Desktop 

Atlanta, Ga.—Viscom has extended its 

product portfolio to include inspection equipment 

for semiconductors with the introduction 

of the desktop MX100IR for reliable and 

flexible inspection of smaller lot sizes. 

The MX100IR, Viscom says, is the ideal 

solution for inspection of bare wafers, chips, 

MEMS, wafer bonds, SOIs and flip chips. It 

can also be used for applications in the photovoltaic 

sector. 

The wafers may be composed of Si, GaAs 

or III-V compounds. 

The core of Viscom’s patented Si-Thru 

technology is its light sources, which generate 

a highly efficient light in the near-infrared 

range. Silicon, with almost all dopings, is 

transparent to this wavelength, so even subsurface 

defects can be inspected with ease. 

[viscom.com] 

The Viscom MX100IR desktop unit is for precision 

wafer inspection. 

The NEW STATE of Flux 

Honeywell VERTEX Detects 

Semiconductor Gas Leaks 

Lincolnshire, Ill.—Honeywell Analytics’ 

new VERTEX scientific multi-point, toxic gas 

monitoring system provides sensitive, costeffective, 

and reliable low-level detection of 

semiconductor gas, backed by physical evidence 

of an actual gas release. 

The VERTEX provides 8 to 72 points of 

continuous gas monitoring, yet has one of the 

smallest footprints used for instrumentation 

of this kind designed specifically for the 

semiconductor industry. 

The system can monitor 

large areas, and sampling 

points can be placed up to 

400 feet (120 meters) from 

the system. [honeywell.com] 

The VERTEX can be placed up 

to 120 meters from the central 

system. 

New designs. More resources. Increased yields. 

The ultimate in flux meets the ultimate in customized support. 

Your resources just got bigger. Heraeus offers unrivaled technical 

support, plus an expanded product line—the most comprehensive 

in the industry—including high-performance fluxes for ball 

and chip attach in No Clean, Solvent Clean and Water Soluble 

versions—all with outstanding print and dispense capabilities 

for maximum yields. The ultimate fluxes. Customized support. 

Global reach. Heraeus—the new state of flux. 

Get your free sample. 

Email us at techservice.hcd@heraeus.com 

and tell us about your application. 

24 Union Hill Road ■ West Conshohoken, PA ■ 19428 

Tel: +1 610-825-6050 

Email: techservice.hcd@heraeus.com 

Web: www.4cmd.com 

Heraeus 

TF Series Fluxes 

Booth #8411 

West Hall 

Visit us at SEMICON West 


Ironwood Electronics Introduces High-Performance Socket 

Burnsville, Minn.—Ironwood Electronics 

has introduced a high-performance BGA socket 

for 0.8mm SDRAMs. 

The SG-BGA-6252 is designed for a 9mm x 

11mm 0.8mm pitch, 60-pin BGA package, 

while the SG-BGA-6253 model has been 

developed for a 9mm x 13mm 0.8mm pitch, 

84-pin BGA format package. 

The sockets will dissipate up to several 

watts without extra heat-sinking and can dissipate 

more heat with a custom heat sink. 

The new Ironwood Electronics BGA socket offers a 

pin inductance of 0.28nH. 

Flanders, N.J.—Rudolph Technologies has 

released the new WS 3840,the latest addition 

to its wafer scanner product family for 

inspection and metrology of backend semiconductor 

manufacturing processes, including 

bumping, probing, sawing and dicing. 

The first order for the WS 3840 has already 

been received and is scheduled for Q3 shipment. 

Following its January announcement about 

the purchase of intellectual property and 

selected assets of RVSI Inspection LLC, 

Rudolph moved quickly to integrate the wafer 

scanner into its Inspection Business Unit 

operations based in Bloomington, Minn. 

“The wafer scanner is the industry standard 

The contact resistance is typically 25milliΩ 

per contact. 

The sockets are constructed from a highperformance, 

low-inductance elastomer with 

an operating temperature range of -35 to 

+100°C. [ironwoodelectronics.com] 

Rudolph Technologies Releases New Scanner 

for bump inspection,” said Rajiv Roy, 

Rudolph’s marketing director for backend 

inspection systems. 

The Rudolph inspection platform, with 

200mm and 300mm wafer-handling capability, 

combines fast robots and intelligent 

scheduling capabilities to maximize handling 

throughput. 

The WS 3840 integrates Rudolph’s laser 

triangulation technology for 3D bump 

metrology and sensitive 2D image-based 

macro-defect inspection on the same wafer 

handler platform that is used by all of the 

company’s advanced inspection and metrology 

tools. [rudolphtech.com] 

94 


INSIDE PATENTS 

Worldwide Protection of Intellectual 

Property Takes a 1-2 Punch Approach 

By A. Jason Mirabito [jmirabito@mintz.com] and 

Carol Peters [cpeters@mintz.com], Contributing Legal Editors, 

Mintz Levin Cohn Ferris Glovsky and Popeo P.C., Boston [mintz.com] 

S 

ince this issue coincides with 

SEMICON West, we offer our 

views on the April 2008 paper 

from SEMI, Intellection Property (IP) 

Challenges and Concerns of the Semiconductor 

Equipment and Materials 

Industry. 

The paper (downloadable free at 

semi.org) notes that legal processes for 

IP protection are slow, expensive, and 

unpredictable. The report focuses largely 

on IP rights violations in the emerging 

Asian markets. 

No ‘International Patent’ 

As an “international patent” does not 

exist, companies must file in individual 

countries or geographic regions, such as 

Europe, for patent protection. If a company 

wants patent protection in Taiwan 

and China, for example, individual applications 

must be filed in these countries. 

Companies that did not file patent applications 

in China 5-10 years ago may regret 

their inaction. As Asian countries—and 

China in particular—grow economically 

and become net exporters of technology, 

such countries will adopt stronger IP protection, 

if for nothing more than self-interest. 

Exactly how can a company obtain 

IP protection in the U.S. and abroad 

Our view is that companies should file 

applications in the U.S. and file national 

applications in each country in which IP 

violations have occurred (or may occur). 

Why file for patent protection where 

IP protection is not strong The simple 

answer is times have changed and 

protection in the country of origin 

and the U.S.—what we call a “onetwo 

punch”—is important. 

For example, if a Taiwan manufacturer 

infringes your patents, you 

can take action against that manufacturer 

in Taiwan. In addition, since 

some 50-60 percent of electronics 

ultimately enter the U.S, attacking 

an infringer here is possible. 

While many Federal district 

courts are slow and expensive, however, 

two courts provide efficient 

litigation: First, the Eastern District 

of Texas is a district in which judges 

are very familiar with patent cases 

and sometimes with the peculiar 

tenets of patent law. 

Cases brought there are resolved for 

trial quickly without the usual delays 

that occur in other courts. 

Infringers frequently attempt to place 

patents into re-examination at the U.S. 

Patent Office and to have the court stay 

the litigation pending the re-examination 

outcome. Many months and perhaps 

even years may lapse before such outcome 

occurs, so hope for a swift resolution before 

the courts is frustrated. 

Due to the relative slowness of the reexamination 

process, some judges in the 

Eastern District of Texas will not stay a 

case pending the re-examination outcome. 

The U.S. International Trade 

Commission (ITC) is another forum 

that has become popular again. 

Global intellectual property protection demands a “onetwo 

punch” approach. 

§337, the Ultimate Sanction 

The ITC is authorized to undertake an 

investigation under Section 337, with 

the ultimate sanction the exclusion of 

infringing goods from the U.S. 

Semiconductor companies are very 

familiar with the ITC and even some 

foreign companies have availed themselves 

of the ITC to prevent foreign 

companies from importing their semiconductors 

and other products into the 

U.S. The ITC is not likely to halt a proceeding 

in the event of reexamination. 

Thus, while many statements in the 

SEMI report are dismaying, two forums 

exist of which U.S. companies can avail 

themselves to receive swift action in 

stopping infringing goods from entering 

the U.S. i 


INDUSTRY NEWS 

University Researchers: Quantum Computers May Become Practical 

Palo Alto, Calif.—Researchers at 

Stanford University, here, and the 

University of California at Santa 

Barbara, say computers based on the 

powerful properties of quantum 

mechanics may revolutionize information 

technology and security. 

Writing recently in the scholarly 

journal Science, the researchers discuss 

an essential component of quantum 

computers, a “logic gate” that enables 

interaction between just two particles 

of light. 

The key advance is a solid state device 

that can produce an interaction between 

photons, according to the team led by 

Jelena Vuckovic, a Stanford assistant 

professor of electrical engineering. 

According to the paper, the team nestled 

a tiny ball of indium arsenide molecules, 

termed a “quantum dot,” within a cavity on 

a photonic crystal—a chip of semiconducting 

GaAs which had been precisely drilled 

with holes to enable it to trap photons 

so they interact with the quantum dot. 

From left, Jelena Vuckovic, doctoral students Ilya 

Fushman, Dirk Englund and Andrei Faraon have demonstrated 

the practicality of computers based on quantum 

physics. (Stanford University) 

Prior work that led to strong interactions 

between individual photons has 

only been done with systems that 

required complex atom-trapping techniques 

that are not as practical as the 

GaAs semiconductor implementation. 

Unlike the “atom-trapping” work, the 

new process employs materials and 

technology that are often used in semiconductor 

manufacturing. 

[stanford.edu] 

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ADVERTISER INDEX 

For more information about any of these advertisers and their products, visit www.chipscalereview.com 

or click on their link in the digital edition at www.chipscalereview.com-digital.com. 

Aceris aceris-3d.ca . . . . . . . . . . . . . . . . . . . . . . . . 22, 64 

Aehr Test aehr.com . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 

Amkor Technology Inc. amkor.com . . . . . . . . . . . . . 80, 81 

Antares Advanced Test Technologies antares-att.com . . . . 1 

Ardent Concepts ardentconcepts.com . . . . . . . . . . . . . . 94 

Aries Electronics arieselec.com . . . . . . . . . . . . . . . . 11, 82 

Artwork Conversion artwork.com . . . . . . . . . . . . . . . . . 46 

ASM Technology Singapore Pte Ltd asmpacific.com . . . . 17 

ATV atv-tech.de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 

Carsem carsem.com . . . . . . . . . . . . . . . Inside Back Cover 

Chip Scale Review chipscalereview.com . . . . . . . 50, 55, 71 

CORWIL corwil.com . . . . . . . . . . . . . . . . . . . . . 35, 37, 83 

Design 2 Market design2marketinc.com . . . . . . . . . . . . . 94 

DL Technology dltechnology.com . . . . . . . . . . . . . . . . . 29 

Dynamic Test Solutions dynamic-test.com . . . . . . . . . . . 91 

ECD ecd.com/cs20 . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 

E-tec Interconnect Ltd. e-tec.com . . . . . . . . . . . . . . . . . 46 

EV Group evgroup.com . . . . . . . . . . . . . . . . . . . . . . . . 34 

F&K Delvotec fkdelvotec.com . . . . . . . . . . . . . . . . . . . . 66 

Hanmi Semiconductor hanmisemi.com . . . . . . . . . . . . . 14 

HCD Corp. hcdcorp.com . . . . . . . . . . . . . . . . . . . . . . . 13 

HDI Solutions hdi-s.com . . . . . . . . . . . . . . . . . . . . . . . 60 

Heraeus 4cmd.com . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 

ICOS Vision Systems icos.be . . . . . . . . . . . . . . . . . . . . 16 

IMI imi-corp.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 

Indium Corp. of America indium.com . . . Inside Front Cover 

Ironwood Electronics ironwoodelectronics.com . . . . . . . . 20 

IWLPC iwlpc.org . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 

JCET jcet-us.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 

Johnstech International johnstech.com/SemiconWest . . . 54 

Keteca keteca.com . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 

KYEC kyec.com.tw . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 

Kyocera kyocera.com . . . . . . . . . . . . . . . . . . . . . . . . . 12 

Micro Control Co. microcontrol.com . . . . . . . . . . . . . . . 89 

Mintz Levin Law Offices mintz.com . . . . . . . . . . . . . . . . 88 

Mühlbauer muhlbauer.com . . . . . . . . . . . . . . . . . . . . . . 9 

Namics namics.co.jp . . . . . . . . . . . . . . . . . . . . . . . . . . 46 

NTK Technologies ntktech.com . . . . . . . . . . . . . . . . . . . 49 

Oerlikon ESEC oerlikon.com . . . . . . . . . . . . . . . . . . . . . 19 

Pac Tech pactech-usa.com . . . . . . . . . . 65, 90, Back Cover 

Pacific Gate Technologies pacgate-us.com . . . . . . . . . 9, 84 

Panasonic Factory Automation panasonicfa.com . . . . . . . 57 

Paricon Technologies paricon-tech.com . . . . . . . . . . . . . 18 

Piper Plastics piperplastics.com . . . . . . . . . . . . . . . 43, 61 

Plasma Etch plasmaetch.com . . . . . . . . . . . . . . . . . . . . 78 

Plastronics Socket Co. plastronicsusa.com . . 23, 25, 27, 85 

Premier Semiconductor premiers2.com . . . . . . . . . . . . . 86 

Promex Industries Inc. promex-ind.com . . . . . . . . . . . . . 30 

Quik-Pak icproto.com . . . . . . . . . . . . . . . . . . . . . . . . . 33 

Robson Technologies Inc. testfixtures.com . . . . . . . . . . . 3 

Rudolph Technologies rudolphtech.com . . . . . . . . . . . . . 24 

SEMI semi.org . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 

SEMPAC sempac.com . . . . . . . . . . . . . . . . . . . . . . . . . 46 

Senju Comtek senjucomtek.com . . . . . . . . . . . . . . . . . . 10 

SER USA serusa.com . . . . . . . . . . . . . . . . . . . . . . . . . 36 

Shibuya Kogyo Co., Ltd shibuya.co.jp . . . . . . . . . . . . . . . 31 

Signetics signetics.com . . . . . . . . . . . . . . . . . . . . . . . . . 2 

Sikama International sikama.com/cs . . . . . . . . . . . . . . . 68 

SSEC ssecusa.com . . . . . . . . . . . . . . . . . . . . . . . . . . 4, 5 

Surface Technology Systems stsystems.com . . . . . . . . . 53 

Synergetix (IDI) synergetix.com . . . . . . . . . . . . . . . . . . 26 

Test Tooling Group tts-group.com . . . . . . . . . . . . . . . . . 41 

Umicore microbond.eu . . . . . . . . . . . . . . . . . . . . . . . . . 7 

Viscom viscom.com . . . . . . . . . . . . . . . . . . . . . . . . . . 92 

Westbond westbond.com . . . . . . . . . . . . . . . . . . . . 12, 46 

YESTech yestechinc.com . . . . . . . . . . . . . . . . . . . . . . . 90 

This index is provided as a service to advertisers and readers. 

Chip Scale Review does not assume any liability for errors or 

omissions in the listings. 

96 


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How many air miles do your wafers have

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