DS335 Synthesized Function Generator

Circuitry 5-3
System DAC and S/H's (DS335M3)
There are four analog voltages which may be set by the CPU. These four voltages control the output square
wave symmetry, square wave amplitude, output offset, and waveform amplitude.
These analog voltages are on sample and hold amplifiers which are maintained by a 12 bit system DAC
(U303, an AD7845). The DAC can output voltages from -5.00 to +5.00V with input values from 0 to 4095.
To refresh a particular sample and hold, the analog multiplexer (U304, a 74HC4051) is inhibited by writing a
'one' to the MSB (Q8) of the DAC_MPX latch (U305, a 74HC273). Next, the address of the desired S/H is
written to bits Q5, Q6 and Q7 of the DAC_MPX latch, along with the four LSB's of the desired 12 bit DAC
value to Q1-4. Then the 8 MSB's of the 12 bit DAC value is written along with the port strobe -DAC_STB to
load the 12 bit value into the DAC. Finally, the inhibit to the DAC multiplexer is removed by writing a zero to
the MSB (Q8) of the DAC_MPX latch.
A different sample and hold is refreshed with each new RTI. The refresh interval is two milliseconds.
The square wave symmetry control voltage may be set over +/-5V with zero being nominal. This voltage
controls the duty cycle of the SYNC and square wave outputs, and varies with frequency to maintain the
output at 50% duty cycle per the contents of a calibration table.
The square wave amplitude control voltage may be set over +/-5V. The actual output square wave amplitude
is linear in the DAC value, and zero when the DAC value is zero. This voltage is set to -5V if a square wave is
not selected in order to reduce cross-talk in the function select relay.
The output offset control voltage may be set over the range of -10.5 to +10.5V. The higher output levels are
due to the gain of x2.1 of the sample and hold amplifier for this control voltage. The front panel function output
will have an dc offset equal to this control voltage. Calibration values will offset and gain-correct this control
voltage so that the actual output offset equals that set from the front panel.
The waveform amplitude control sample and hold output is level shifted and attenuated to a +3 to +5 Vdc
range. This control voltage is used as a reference to the 8-bit amplitude leveling DAC, which is controlled by
the ASIC during frequency sweeps. The the weighted sum of the leveling DAC output and amplitude control
voltage is scaled to the range of -.75 to -1.25 for the nominal leveling DAC value of 128.
DDS ASIC (DS335M4)
Waveforms are generated in the DS335 by updating a 12 bit DAC at a rate of 10 million samples per second.
The waveform (sine, ramp, saw, or noise) is stored in ROM, and the ROM is addressed by a 'phase
accumulator' which is implemented in a CMOS ASIC.
The ASIC's phase accumulator is a 48 bit adder, with the top 15 bits of the accumulated result serving as the
address to the ROM. The frequency of the output waveform is proportional to the rate at which ROM
addresses change, so, the larger the number added to the phase accumulator the higher the frequency. The
48 bit number resides in six 8-bit registers in the ASIC. This 48-bit number is called the 'phase increment
register', or PIR.
To facilitate seamless frequency changes, there are two phase increment registers, PIRA and PIRB. The
adder will use one of the PIR's while the host processor (or modulation RAM) is writing to the other, and the
adder can shift between the two PIR's without missing a single add cycle.
In addition to the PIR's, there are lots of other registers in the ASIC. The other registers are used for mode
control, setting prescalers, and setting modulation (sweep) addresses. Three of these registers, are located
off the ASIC: strobes are generated which will allow modulation data to be latched into external devices. This
allows amplitude leveling during sweeps, etc., by the modulation program. The FSK BNC input goes directly
to the ASIC and allows the user to select between PIRA and PIRB by changing the input level.
DS335 Synthesized Function Generator