DS335 Synthesized Function Generator

2-2 Introduction
DDS gives the DS335 greater flexibility and power than conventional
synthesizers without the drawbacks inherent in PLL designs.
DS335 Description
Figure 2: DS335 Block Diagram
A block diagram of the DS335 is shown in Figure 2. The heart of the DS335
is a 10 MHz crystal clock. The 10 MHz clock controls the DDS ASIC,
waveform ROM, and high-speed 12bit DAC. Sampling theory limits the
frequency of the waveform output from the DAC to about 40% of 10 MHz, or
3 MHz. The 48 bit length of the ASIC's PIR's sets the frequency resolution to
about 36 nHz. These parameters and the DAC's 12 bit resolution define the
performance limits of the DS335.
The reconstruction filter is key to accurately reproducing a waveform in a
sampled data system. The DS335 contains two separate filters. For sine
wave generation the output of the DAC goes through a 7 th order Cauer filter,
while ramps, and triangles pass instead through a 3.5 MHz 5 th order Bessel
filter. The Cauer filter has a cutoff frequency of 3.4 MHz and a stopband
attenuation of 86 dB, and includes a peaking circuit to correct for the
sin(x)/x amplitude response characteristic of a sampled system. This filter
eliminates any alias frequencies from the waveform output and allows
generation of extremely pure sine waves. However, the Cauer filter has very
poor time response and is only useful for CW waveforms. Therefore, the
Bessel filter was chosen for its ideal time response, eliminating rings and
overshoots from stepped waveform outputs.
The output from the filter passes through pre-amplifier attenuators with a 0 to
14 dB range. The attenuators are followed with a wide bandwidth power
amplifier that outputs a 10 V peak-to-peak into a 50 ohm load with a rise time
of less than 15 ns. The output of the power amplifier passes through a series
of four step attenuators (2, 4, 8, and 16 dB) that set the DS335's final output
DS335 Synthesized Function Generator