Design and Applications of Delay Locked Loop
Design and Applications of Delay Locked Loop
Design and Applications of Delay Locked Loop
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University <strong>of</strong> Niš<br />
Faculty <strong>of</strong> Electronic Engineering<br />
Department <strong>of</strong> Electronic<br />
Goran Jovanović<br />
<strong>Design</strong> <strong>and</strong> <strong>Applications</strong> <strong>of</strong><br />
<strong>Delay</strong> <strong>Locked</strong> <strong>Loop</strong><br />
DAAD Workshop "Embedded System <strong>Design</strong>"<br />
Niš, , Serbia, 5-95<br />
9 July 2010.
<strong>Delay</strong> elements <strong>and</strong> delay lines<br />
Architecture <strong>and</strong> properties <strong>of</strong> DLL<br />
circuits, comparison with PLL<br />
Linearization <strong>of</strong> analog delay<br />
element, three solutions<br />
Application with delay elements <strong>and</strong><br />
DLL circuits
wide regulation range<br />
linear delay regulation<br />
characteristic<br />
low power consumption<br />
discrete characteristic<br />
coarse regulation<br />
high jitter level<br />
Continual &<br />
fine delay regulation<br />
simple realization<br />
resistant to interference<br />
narrow regulation range<br />
nonlinear delay<br />
regulation<br />
larger power<br />
consumption<br />
wide regulation<br />
range,<br />
fine regulation<br />
complex<br />
realization<br />
complicated<br />
control<br />
larger power<br />
consumption
Digital delay lines are realized as chain <strong>of</strong><br />
elements with fixed delay value.<br />
The number <strong>of</strong> elements in a chain<br />
determines the amount <strong>of</strong> the delay.
Digital delay lines<br />
are controlled with:<br />
multiplexer,<br />
shift register <strong>and</strong><br />
CMOS switch
V P bias<br />
V dd<br />
M 4<br />
M 2<br />
V 0<br />
M 1<br />
i d3<br />
W 4 /L 4<br />
i d4<br />
V ctrl<br />
in<br />
out<br />
C L<br />
V N bias<br />
M 3<br />
W 3 /L 3<br />
CLK ref<br />
1 2 3 4 5<br />
CLK ref<br />
EK 1 EK 2 EK 3 EK 4 EK 5<br />
CLK out<br />
(a)<br />
Simple circuits with<br />
structure <strong>of</strong> inverter or<br />
buffer.<br />
Control voltage<br />
change:<br />
DC operate point,<br />
impedance value in<br />
critical circuit’s node<br />
1<br />
2<br />
3<br />
4<br />
5<br />
CLK out<br />
(b)
It consists <strong>of</strong>:<br />
two inverters stage<br />
bias circuit<br />
2200<br />
Transistors M 3<br />
& M 4<br />
limited<br />
charging/ discharging current<br />
<strong>of</strong> parasite output capacitance.<br />
1800<br />
1400<br />
t<br />
d<br />
=<br />
C<br />
⋅V<br />
L dd<br />
2 ⋅ i d 3<br />
1000<br />
600<br />
2.6 2.8 3 3.2 3.4 3.6 3.8 4<br />
Voltage V c [V]
It consists <strong>of</strong>:<br />
inverter stage<br />
variable capacitive load<br />
840<br />
800<br />
Inverter with variable capacitive output<br />
impedance (transistor M 4 & M 8 )<br />
Bias circuit is not necessary.<br />
Control voltage V ctrl polarize gates<br />
transistors M 3 & M 7 which work in linear<br />
mode (like resistors) <strong>and</strong> determine<br />
output impedance.<br />
kašnjenje td [ps]<br />
760<br />
720<br />
680<br />
640<br />
600<br />
560<br />
3 3.5 4 4.5 5<br />
napon V ctrl [V]
V dd<br />
M<br />
V<br />
5<br />
ctrl<br />
V dd<br />
out A<br />
in A<br />
M 3 M 4<br />
M 1 M 2<br />
V dd<br />
M 6<br />
out B<br />
in B<br />
<strong>Delay</strong> elements with<br />
differential input/output<br />
latch structure<br />
good resistance on interference<br />
<strong>and</strong> compliance <strong>of</strong> rising <strong>and</strong><br />
falling edge delay<br />
Differential delay elements use limited<br />
charge/discharge current <strong>and</strong> parasite<br />
output capacitance to obtain delay<br />
very fine delay<br />
regulation <strong>and</strong> good<br />
resistance to noise<br />
complex realization,<br />
large power<br />
consumption, small<br />
output voltage level
Current starved delay<br />
element has the best<br />
features :<br />
the wider range <strong>of</strong><br />
delay regulation,<br />
simple realization,<br />
low-power<br />
consumption
DLL circuits is used for control delay elements <strong>and</strong> lines.<br />
Ensures that the output clock signal to synchronize with a<br />
reference clock.<br />
DLL architectures is classified into<br />
three types:<br />
analog<br />
digital<br />
hybrid (with double loop)<br />
If exist, phase error<br />
between referent <strong>and</strong><br />
output signalsa,<br />
negative feedback<br />
loop corrected delay<br />
value.
digital DLL<br />
analog DLL
<strong>Delay</strong> td<br />
digital DLL<br />
TIME RASPONSE<br />
analog DLL
the wider range <strong>of</strong><br />
delay regulation<br />
fine regulation<br />
complex realization<br />
complex control<br />
larger power<br />
consumption
DL<br />
CP<br />
PD<br />
DL<br />
CP<br />
PD<br />
DL<br />
CP<br />
PD<br />
I<br />
k<br />
k<br />
k<br />
C<br />
s<br />
k<br />
sC<br />
k<br />
k<br />
k<br />
sC<br />
k<br />
k<br />
s<br />
D<br />
s<br />
D<br />
⋅<br />
⋅<br />
⋅<br />
+<br />
=<br />
⋅<br />
⋅<br />
+<br />
⋅<br />
⋅<br />
=<br />
1<br />
1<br />
1<br />
)<br />
(<br />
)<br />
0 (<br />
C<br />
k<br />
I<br />
f<br />
C<br />
k<br />
k<br />
k<br />
DL<br />
CP<br />
ref<br />
DL<br />
CP<br />
PD<br />
N<br />
⋅<br />
⋅<br />
=<br />
⋅<br />
⋅<br />
=<br />
ω<br />
N<br />
DL<br />
CP<br />
ref<br />
I<br />
DLL<br />
s<br />
k<br />
I<br />
f<br />
C<br />
s<br />
s<br />
D<br />
s<br />
D<br />
s<br />
H<br />
ω<br />
+<br />
=<br />
⋅<br />
⋅<br />
⋅<br />
+<br />
=<br />
=<br />
1<br />
1<br />
1<br />
1<br />
)<br />
(<br />
)<br />
(<br />
)<br />
(<br />
0<br />
first order system,<br />
absolute stable
θ ( s)<br />
= θ<br />
⋅ F(<br />
s)<br />
second order system,<br />
0<br />
PD CP VCO<br />
H PLL( s)<br />
=<br />
potential unstable ( s)<br />
s + K ⋅ K ⋅ K ⋅ F(<br />
s)<br />
i<br />
K<br />
⋅ K<br />
PD<br />
⋅ K<br />
CP<br />
VCO<br />
Nisko-<br />
Frekventni<br />
Fltar<br />
f ref<br />
Naponski Kontrolisani Oscilator<br />
VCO<br />
Strujna<br />
Pumpa<br />
UP<br />
Fazni<br />
Detektor<br />
NFF<br />
SP<br />
FD<br />
V ctrl<br />
DOWN<br />
f out<br />
ξ<br />
H ( s)<br />
=<br />
1<br />
ω n τ z<br />
2<br />
θ0(<br />
s)<br />
θ ( s)<br />
i<br />
=<br />
s<br />
2<br />
2<br />
n<br />
2⋅ξ<br />
⋅ωn<br />
⋅ s + ω<br />
+ 2⋅ξ<br />
⋅ω<br />
⋅ s + ω<br />
= ωn<br />
= K PD ⋅ KCP<br />
⋅ KVCO<br />
⋅ K F<br />
n<br />
2<br />
n
Characteristic DLL PLL<br />
Frequency<br />
multiplying<br />
No<br />
yes<br />
Architecture simple complex<br />
transfer function firs order second order<br />
stabile absolute conditional<br />
locking time short long<br />
delay range <strong>of</strong><br />
regulation<br />
limited<br />
unlimited<br />
tracking jitter small large<br />
PLL<br />
2<br />
, DLL<br />
2<br />
∆t ∆t<br />
∆t<br />
α ≅<br />
ω<br />
2ω<br />
ref<br />
2<br />
2<br />
2<br />
PLL = α ⋅ ∆t VCO<br />
PLL<br />
∆t<br />
2<br />
= N ⋅ ∆<br />
DLL t d<br />
2
The proposed three solutions to the<br />
analog voltage controlled lines with<br />
linear regulation <strong>of</strong> the delay as a<br />
function <strong>of</strong> control voltage :<br />
with control threshold voltage<br />
current starved delay element<br />
with symmetrical load<br />
current starved element with<br />
nonlinear bias circuit<br />
Proposed solutions is<br />
differ in:<br />
method <strong>of</strong><br />
implementation<br />
is useful for different<br />
range <strong>of</strong> delay<br />
regulation
<strong>Delay</strong> is determined by:<br />
charge/discharge current<br />
output impedance (capacitance)<br />
threshold voltage (hysteresis)<br />
C<br />
C<br />
td LH = ( VH<br />
+ −V−<br />
) td<br />
HL = ( V+ −VH<br />
−)<br />
I<br />
I<br />
1<br />
2<br />
CLKin<br />
τ=t dLH<br />
= t dHL<br />
τ =<br />
C ∆ V<br />
I<br />
V L<br />
∆V=V H+<br />
-V -<br />
= V +<br />
-V H-<br />
I 1<br />
=I 2<br />
=I<br />
CLKout
<strong>Delay</strong> is proportional:<br />
output capacity <strong>and</strong><br />
threshold voltage (hysteresis)<br />
<strong>and</strong> reciprocal:<br />
charge/discharge output<br />
current<br />
CLK in I 2,i i=1,..,5<br />
+V H<br />
histerezis<br />
I 1,i i=1,..,5<br />
t<br />
CLK out<br />
t dLH T/2 t dHL T/2 t<br />
-V H<br />
V L<br />
CLKout<br />
voltage controlled<br />
capacitance can not<br />
be implemented in<br />
linear <strong>and</strong> suitable<br />
manner
It consist <strong>of</strong> :<br />
integrator (IN)<br />
threshold voltage generator<br />
(GH)<br />
comparator (K)<br />
threshold voltage V H<br />
has<br />
opposite value for raisin<br />
<strong>and</strong> falling clock edge, to<br />
avoid changes in pulse<br />
width.
V +<br />
V+<br />
V +<br />
V B<br />
M 7<br />
M 5<br />
M 6<br />
V bp<br />
V bn<br />
M 4<br />
M 3<br />
M 2<br />
M 1<br />
I 1<br />
SW 1<br />
I 2<br />
IN<br />
V L<br />
C=1pF<br />
V H<br />
CLK out<br />
hysteresis<br />
voltage<br />
generator with<br />
characteristic<br />
V +<br />
M 2<br />
M 3<br />
V ctrl<br />
SW 2<br />
M 12<br />
V H+<br />
M 9<br />
M 10<br />
CLK in<br />
M 8<br />
V H<br />
V ctrl<br />
V H+<br />
V H-<br />
M 1<br />
M 11<br />
V H-<br />
scheme <strong>of</strong> delay line with hysteresis<br />
voltage regulation
6.0V<br />
4.0V<br />
2.0V<br />
0V<br />
5.0V<br />
4.0V<br />
2.0V<br />
0V<br />
30ns<br />
CLK in<br />
V H+<br />
V H-<br />
V H+ V H-<br />
3.6V 1.4V<br />
3.4V 1.6V<br />
3.2V 1.8V<br />
3.0V 2.0V<br />
0s 0.2us 0.4us 0.6us 0.8us 1.0us<br />
t<br />
5.0V<br />
4.0V<br />
2.0V<br />
0V<br />
60ns 530ns<br />
t<br />
t<br />
560ns<br />
delay in<br />
function <strong>of</strong><br />
control<br />
voltage<br />
delay<br />
linearity<br />
error in<br />
function <strong>of</strong><br />
control<br />
voltage<br />
[ns]<br />
dτ<br />
τ<br />
52<br />
50<br />
48<br />
46<br />
44<br />
42<br />
40<br />
38<br />
2.6 2.8 3 3.2 3.4 3.6 3.8 4<br />
1.5<br />
1<br />
0.5<br />
0<br />
-0.5<br />
10 ns<br />
x 10 -3<br />
1 V<br />
V ctrl [V]<br />
-1<br />
2.6 2.8 3 3.2 3.4 3.6 3.8 4<br />
V ctrl [V]
The modification is made by<br />
adding a transistors M 5<br />
& M 6<br />
They present symmetrical<br />
load.<br />
Symmetrical load increase the current<br />
charging/discharging the output capacitance<br />
<strong>and</strong> change shape <strong>of</strong> regulation characteristic.<br />
Current is a variable <strong>and</strong> it value depends<br />
from output voltage.<br />
Symmetrical load provide negative feedback<br />
which gives linear regulation characteristic.
current starved<br />
delay element<br />
with symmetrical load<br />
⎛W<br />
⎜<br />
⎝ L<br />
⎛W<br />
⎜<br />
⎝ L<br />
3<br />
3<br />
5<br />
5<br />
⎞<br />
⎟<br />
⎠<br />
⎞<br />
⎟<br />
⎠<br />
delay linearity error in function <strong>of</strong><br />
control voltage<br />
<strong>Delay</strong> in function <strong>of</strong> control<br />
voltage<br />
⎛W<br />
⎜<br />
⎝ L<br />
⎛W<br />
⎜<br />
⎝ L<br />
3<br />
3<br />
5<br />
5<br />
⎞<br />
⎟<br />
⎠<br />
⎞<br />
⎟<br />
⎠
<strong>Delay</strong> tp [ps]<br />
−<br />
dV<br />
0<br />
C L = id<br />
3 +<br />
dt<br />
i<br />
d 5<br />
t<br />
p1<br />
=<br />
k<br />
k<br />
1<br />
2<br />
τ<br />
( V − V )<br />
g<br />
t<br />
⋅ arctan<br />
k<br />
k<br />
1<br />
2<br />
( V − V )<br />
2 ⎛Vdd<br />
⎞<br />
( V − V ) + ⎜ − V ⎟ ⋅ ( V −V<br />
)<br />
g<br />
V<br />
2<br />
t<br />
dd<br />
⋅<br />
⎝<br />
k<br />
k<br />
1<br />
2<br />
2<br />
g<br />
t<br />
⎠<br />
t<br />
dd<br />
t
Bias circuit control<br />
charging/discharging<br />
current I cp<br />
<strong>of</strong> output<br />
C load<br />
capacitance.<br />
Interconnection <strong>of</strong> BIAS circuit <strong>and</strong> current<br />
starved element<br />
The delay is<br />
determined by the<br />
equation:<br />
t<br />
d<br />
=<br />
C<br />
load<br />
2 ⋅<br />
⋅V<br />
I<br />
cp<br />
dd<br />
Typical, current I cp<br />
in<br />
a linear way depends<br />
on the control<br />
voltageV ctrl<br />
.
V ctrl<br />
R<br />
Nonlinear bias circuits use<br />
square characteristics <strong>of</strong> MOS<br />
transistor in saturation.<br />
Bias circuit is designed to<br />
provide reciprocal relation<br />
between current <strong>and</strong> voltage.
28<br />
26<br />
22<br />
L A =10 m<br />
L A =12 m<br />
L A =14 m<br />
18<br />
14<br />
-0.8 -0.4 0 0.4 0.8 1<br />
V ctrl [V]<br />
0.08<br />
0.07<br />
0.06<br />
0.05<br />
0.04<br />
0.035<br />
-0.8 -0.4 0 0.4 0.8 1<br />
V ctrl [V]<br />
2<br />
1<br />
0<br />
-1<br />
-2<br />
-3<br />
L A =10 m<br />
L A =12 m<br />
L A =14 m<br />
L A =10 m<br />
L A =12 m<br />
L A =14 m<br />
a)<br />
b)<br />
-4<br />
-0.8 -0.4 0 0.4 0.8 1<br />
V ctrl [V]<br />
c)<br />
Simulation<br />
<strong>of</strong>:<br />
bias circuit<br />
<strong>and</strong><br />
current<br />
starved<br />
delay<br />
element<br />
BIAS circuit<br />
simulation<br />
60<br />
50<br />
40<br />
30<br />
25<br />
-0.8 -0.4 0 0.4 0.8 1<br />
V ctrl [V]<br />
a)<br />
3000<br />
2500<br />
2000<br />
1500<br />
1000<br />
500<br />
0<br />
-500<br />
-1000<br />
-0.8 - 0.4 0 0.4 0.8 1<br />
V ctrl [V]<br />
b)
Bias circuit<br />
I<br />
LPF1<br />
LPF2<br />
four-stages delay line with nonlinear<br />
bias circuit<br />
UP<br />
DOWN<br />
DOWN<br />
UP<br />
CP1<br />
CP2<br />
I<br />
DLL with two current pump.<br />
It provides differential<br />
control voltage.
Simulation<br />
<strong>of</strong> DLL with<br />
two charge<br />
pump<br />
<strong>and</strong><br />
nonlinear<br />
bias circuit
DLL <strong>and</strong> delay lines include wide area<br />
<strong>of</strong> applications :<br />
fast RAM memory,<br />
serial USB2 i IEEE 1394 interfaces<br />
FPGA chips,<br />
telecommunication,<br />
circuits for PN coda tracking<br />
spread spectrum systems<br />
measuring <strong>and</strong> processing<br />
equipment...<br />
Some suggested<br />
applications:<br />
multi-frequencies <strong>and</strong><br />
multi-phases clock<br />
synthesis with DLL<br />
high-resolution time-todigital<br />
converter<br />
adaptive duty cycle<br />
corrector
The most important DLL‘s<br />
application is achieving the<br />
correct transfer data<br />
between two synchronous<br />
digital blocks<br />
synthesis <strong>and</strong> distribution <strong>of</strong><br />
clock signal, clock-skew <strong>and</strong><br />
jitter problems elimination
CLK ref<br />
2.Ph_1<br />
2.Ph_4<br />
4.Ph_1<br />
4.Ph_2<br />
Phase Detector<br />
Current pump<br />
<strong>Loop</strong> Filter<br />
V ctrl<br />
<strong>Delay</strong> Line<br />
EK 1 EK 2 EK 3 EK n<br />
Edge Combiner Circuit<br />
s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 1<br />
CLK out<br />
1.Ph_1<br />
1.Ph_8<br />
V ctrl+<br />
V +<br />
V +<br />
M 2<br />
CLK i-1<br />
CLK i<br />
t d<br />
V ctrl-<br />
AND 1<br />
M 1<br />
M 3<br />
M 6<br />
M 4<br />
M 5<br />
In 1<br />
s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 1<br />
s i<br />
CLK ref<br />
1.Ph_2<br />
1.Ph_3<br />
1.Ph_4<br />
1.Ph_5<br />
a)<br />
1.Ph_6<br />
1.Ph_7<br />
1.Ph_8<br />
2.Ph_1<br />
2.Ph_2<br />
2.Ph_3<br />
b)<br />
2.Ph_4<br />
4.Ph_1<br />
4.Ph_2<br />
c)<br />
CLK ref<br />
s 1<br />
s 2<br />
s 3<br />
d)<br />
2.Ph_1 2.Ph_2 2.Ph_3 2.Ph_4<br />
(a)<br />
(b)<br />
4. Ph_1 4. Ph_2
DLL based frequency multiplier uses voltage-controlled delay<br />
elements which represents a significant advantage related to the<br />
st<strong>and</strong>ard solution with a PLL frequency multiplier circuit which<br />
uses voltage controlled ring oscillator.<br />
Illustration form <strong>of</strong><br />
jitter accumulation in<br />
PLL <strong>and</strong> DLL circuits for<br />
frequency multiplying
The timing resolution <strong>of</strong> the delay<br />
Vernier technique is determined by<br />
the difference between two<br />
propagation delay values.<br />
Start signal spreads through the<br />
upper (slower) delay line (t d1 ).<br />
Stop signal is spread through the<br />
lower (faster) line delay (t d2 ).<br />
Measurements resolution <strong>of</strong> several<br />
tens <strong>of</strong> pico-seconds can be achieved<br />
if difference in delays between upper<br />
<strong>and</strong> lower elements small enough.<br />
Measurement range is equal to the<br />
duration <strong>of</strong> one period <strong>of</strong> reference<br />
clock.
stop start<br />
Modifying<br />
Vernier delay<br />
technique<br />
DLL is used<br />
for<br />
calibration<br />
delay lines in<br />
Vernier<br />
convertora<br />
Fazni<br />
detektor
t x<br />
t 4<br />
t 5<br />
t 6<br />
t 7<br />
t 8<br />
t 9<br />
S 1 C 1<br />
1<br />
t 0<br />
t 1<br />
t 2<br />
t 3<br />
S 2 C 2<br />
1<br />
S 3 C 3<br />
1<br />
S 4 C 4<br />
S 7<br />
S<br />
1 elements.<br />
1<br />
6<br />
1<br />
C 7<br />
C 8<br />
1<br />
9 C 9<br />
1<br />
1<br />
S 10<br />
1 Waveform <strong>of</strong> S i i C i represent start i stop<br />
pulses on outputs <strong>of</strong> appropriate delay<br />
S 5 C 5<br />
S 6 C<br />
8<br />
C 10<br />
S 11<br />
C 12<br />
S 11 0<br />
S 12 0<br />
5.0ns 10.0ns 15.0ns 20.0ns 25.0ns 30.0ns<br />
time
V dd<br />
V DCC<br />
in<br />
M 2<br />
*<br />
out<br />
in<br />
*<br />
M 3<br />
out<br />
M 2<br />
V dd<br />
V DCC<br />
V BP<br />
in<br />
V BN<br />
M 1<br />
M 1<br />
(a)<br />
V dd V dd<br />
M 4<br />
* M 6<br />
M 2<br />
M 3<br />
(c)<br />
*<br />
in<br />
out<br />
M 5<br />
V DCC<br />
V DCC<br />
(b)<br />
6 stages<br />
7 stages<br />
(d)<br />
out<br />
Working principle <strong>of</strong> duty cycle<br />
corrector is based on delay element<br />
which gives a different delay value<br />
for rising <strong>and</strong> falling edge <strong>of</strong> signal.<br />
Circuit from Fig. (c) has the<br />
widest range <strong>of</strong> regulation.<br />
Circuits from Fig. (a), (b) <strong>and</strong><br />
(d) have influence or just on<br />
expansion or just on<br />
compression <strong>of</strong> pulses.
(a) Scheme<br />
(b) Ekvivalent scheme<br />
100<br />
90<br />
80<br />
Pulse / period<br />
ratio in function<br />
<strong>of</strong> control voltage<br />
Duty Cycle [%]<br />
70<br />
60<br />
50<br />
40<br />
V ctrl<br />
30<br />
1.5 2 2.5 3 3.5<br />
20<br />
V ctrl [V]
Voltage<br />
CLKin<br />
PICSout<br />
Spice<br />
simulation for<br />
different<br />
values <strong>of</strong><br />
control<br />
voltage<br />
V ctrl
Symmetrical relation between pulse/pause is unmatched<br />
when:<br />
signal passes through a long series <strong>of</strong> buffers,<br />
unbalance <strong>of</strong> N <strong>and</strong> P MOS transistors,<br />
technology variations,<br />
temperature or supply voltage have change ...<br />
PWCL scheme<br />
Waveform at<br />
PWCL<br />
obtained by<br />
Spice<br />
simulation
It is presented three new solutions for<br />
linear analog delay line :<br />
with threshold voltage control,<br />
with symmetrical load,<br />
with nonlinear bias circuit,<br />
<strong>and</strong> proposed new <strong>and</strong> modified<br />
existing application :<br />
multi-frequency <strong>and</strong> multi-phase<br />
clock synthesis with DLL<br />
time-to-digital converter<br />
adaptive pulse width control loop<br />
The applied models <strong>and</strong><br />
design rules are for<br />
technology companies<br />
South Africa<br />
Microelectronics (SAMES)