NAND Flash Reliability and Performance - Micron
NAND Flash Reliability and Performance - Micron
NAND Flash Reliability and Performance - Micron
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<strong>NAND</strong> <strong>Flash</strong> <strong>Reliability</strong> <strong>and</strong> <strong>Performance</strong><br />
The Software Effect<br />
Wes Prouty (waprouty@micron.com)<br />
Applications Engineering Manager<br />
<strong>Micron</strong> Technology, Inc.
Santa Clara, CA USA<br />
August 2007<br />
Agenda<br />
� Why change <strong>NAND</strong> <strong>Flash</strong> software?<br />
� Review of <strong>NAND</strong> <strong>Flash</strong> error modes<br />
� Review of <strong>NAND</strong> <strong>Flash</strong> performance<br />
enhancements<br />
� Status of <strong>NAND</strong> software in embedded operating<br />
systems<br />
� <strong>NAND</strong> <strong>Flash</strong> software stack variations<br />
� How is software affected by MLC <strong>NAND</strong>?<br />
� Is software the only solution?<br />
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Santa Clara, CA USA<br />
August 2007<br />
Why Change <strong>NAND</strong> <strong>Flash</strong><br />
Software?<br />
� Embedded space has predominately used<br />
small-page, single-level cell <strong>NAND</strong> <strong>Flash</strong><br />
� Code storage is moving to <strong>NAND</strong> <strong>Flash</strong> in<br />
many applications<br />
� As <strong>NAND</strong> <strong>Flash</strong> geometries shrink, software<br />
usage models must become more sensitive<br />
to <strong>NAND</strong> error modes<br />
� New <strong>NAND</strong> devices include advanced<br />
performance features<br />
� MLC <strong>NAND</strong>!<br />
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� Stressed cells are limited<br />
to the block being<br />
programmed<br />
� However, stressed cells<br />
can be in selected or<br />
unselected page<br />
� Disturb occurs when<br />
charge collects on the<br />
floating gate, causing the<br />
cell to appear weakly<br />
programmed<br />
� Does not damage cells;<br />
ERASE returns cells to<br />
undisturbed levels<br />
Santa Clara, CA USA<br />
August 2007<br />
Program Disturb<br />
SGD: Vcc<br />
Unselected<br />
Page:<br />
Selected<br />
Page:<br />
Unselected<br />
Page:<br />
10V<br />
20V<br />
10V<br />
I/O<br />
I/O<br />
I/O<br />
I/O<br />
Vcc 0V Vcc 0V<br />
Strings being programmed are<br />
grounded. Others are at Vcc.<br />
Note: Circuit structures <strong>and</strong> voltages are representative only. Details<br />
vary by manufacturer <strong>and</strong> technology node.<br />
Programmed<br />
Cells<br />
Program<br />
Disturb Cells<br />
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Santa Clara, CA USA<br />
August 2007<br />
Read Disturb<br />
� Stressed cells limited to<br />
the block being<br />
programmed<br />
� Stressed cells are in<br />
unselected page<br />
� Disturb occurs when<br />
charge collects on the<br />
floating gate, causing the<br />
cell to appear weakly<br />
programmed<br />
� Does not damage cells;<br />
ERASE returns cells to<br />
undisturbed levels<br />
Unselected<br />
Page<br />
Selected<br />
Page<br />
Unselected<br />
Page<br />
4.5V<br />
0V<br />
4.5V<br />
I/O<br />
I/O<br />
I/O<br />
I/O<br />
Note: Circuit structures <strong>and</strong> voltages are representative only. Details<br />
vary by manufacturer <strong>and</strong> technology node<br />
Stressed<br />
Cells<br />
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Santa Clara, CA USA<br />
August 2007<br />
Endurance <strong>and</strong> Data Retention<br />
� Endurance – PROGRAM/ERASE cycles may<br />
cause charge to be trapped in the dielectric.<br />
This is a failed block that should be retired.<br />
� Data Retention – Charge loss/gain occurs on<br />
the floating gate over time. Cell is undamaged,<br />
block can be reliably erased <strong>and</strong> reprogrammed.<br />
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� Program Disturb<br />
Santa Clara, CA USA<br />
August 2007<br />
Reducing <strong>NAND</strong> Error Modes<br />
• Reduce partial page programming (NOP)<br />
• Programming the pages of each block in sequential order<br />
� Read Disturb<br />
• Frequently read data should be cached to DRAM<br />
• Refresh data when exceeding read disturb recommendations<br />
� Endurance <strong>and</strong> data retention<br />
• Retire bad blocks<br />
• Wear level across all blocks (code <strong>and</strong> data)<br />
� Use ECC to manage disturbed bits!<br />
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Santa Clara, CA USA<br />
August 2007<br />
<strong>NAND</strong> <strong>Flash</strong> <strong>Performance</strong><br />
� Embedded systems are primarily using 512byte<br />
<strong>NAND</strong> <strong>Flash</strong>, which has lower<br />
performance than 2KB <strong>NAND</strong> <strong>Flash</strong><br />
� Those systems using 2KB <strong>NAND</strong> <strong>Flash</strong> only<br />
implement the “basic” comm<strong>and</strong>s<br />
� <strong>NAND</strong> <strong>Flash</strong> enhanced feature set greatly<br />
improves <strong>NAND</strong> <strong>Flash</strong> performance:<br />
• Read performance can be increased by over 30%<br />
• Program performance can be increased by over 100%!<br />
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Throughput (MB/s)<br />
Santa Clara, CA USA<br />
August 2007<br />
40.00<br />
30.00<br />
20.00<br />
10.00<br />
0.00<br />
<strong>NAND</strong> <strong>Flash</strong> <strong>Performance</strong><br />
27.04<br />
4Gb <strong>NAND</strong> (M50, 55nm) <strong>Performance</strong><br />
37.55<br />
Page Read Cache<br />
Read<br />
6.07<br />
7.02<br />
10.66<br />
Page Pgm Cache Pgm 2Pl Page<br />
Pgm<br />
Operating Mode<br />
x16<br />
14.01<br />
2Pl Cache<br />
Pgm<br />
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Santa Clara, CA USA<br />
August 2007<br />
Status of <strong>NAND</strong> Software in<br />
Embedded Operating Systems<br />
ECC Support<br />
Bad Block<br />
Management<br />
Wear Leveling Data<br />
Storage<br />
Wear Leveling Code<br />
Storage<br />
Enhanced <strong>NAND</strong><br />
Feature Support<br />
MLC Support<br />
NOP = 1<br />
Data Refresh<br />
OS #1 Yes Yes Yes No No No No No<br />
OS #2 Yes Yes Yes No No No No No<br />
OS #3 Yes Yes Yes No No No No No<br />
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Santa Clara, CA USA<br />
August 2007<br />
The FTL <strong>NAND</strong> Software Model<br />
� The FTL model is used by<br />
Windows Mobile, Symbian, <strong>and</strong><br />
many other embedded operating<br />
systems<br />
� The <strong>NAND</strong> usage model is<br />
controlled by the FTL<br />
� Need FTL changes to address:<br />
• NOPs<br />
• Enhanced performance features<br />
• Wear leveling of code storage<br />
• Data refresh<br />
• MLC <strong>NAND</strong><br />
� Need <strong>Flash</strong> driver for:<br />
• Cache modes<br />
• Two-plane operations<br />
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Santa Clara, CA USA<br />
August 2007<br />
How Can We Drive <strong>NAND</strong> Usage<br />
Model Changes in FTL?<br />
� Work with the major operating system companies to change<br />
FTL delivered with OS<br />
• Pro – covers the widest range of applications, <strong>NAND</strong> <strong>Flash</strong> code<br />
comes with OS<br />
• Con – software changes slow, may not cover all application<br />
requirements<br />
� Work with software providers of FTL such as Datalight, Inc., or<br />
CMX Systems, Inc.<br />
• Pro – customized solutions, quicker development<br />
• Con – may require additional software integration work, may not be<br />
optimized for multiple memory vendor products<br />
� Use FTL software provided by memory vendor<br />
• Pro – solution is highly optimized for a specific memory<br />
• Con – all memory vendors do not offer software, memory second<br />
source could be an issue<br />
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Santa Clara, CA USA<br />
August 2007<br />
The MTD <strong>NAND</strong> Software Model<br />
� The MTD model is used by<br />
Embedded Linux Operating<br />
Systems<br />
� Note that the <strong>NAND</strong> <strong>Flash</strong><br />
usage model is controlled by<br />
the file system in this model<br />
(Typically implies JFFS2 File System)<br />
(Hardware)<br />
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Santa Clara, CA USA<br />
August 2007<br />
The MTD <strong>NAND</strong> Software Model –<br />
More Detail<br />
� MTD driver module changes<br />
required to implement<br />
enhanced <strong>NAND</strong> features<br />
� Changes must be considered<br />
carefully so they don’t force<br />
changes to upper layers (which<br />
are more difficult to implement)<br />
� Easiest method is to make<br />
changes in physical interface<br />
layer:<br />
• Pro – changes confined to<br />
physical interface layer<br />
• Con – changes required for<br />
individual platforms<br />
MTD Driver Module<br />
<strong>Flash</strong> Interface Layer<br />
(interface to MTD user module)<br />
<strong>NAND</strong>_BASE.c Layer<br />
(Page Read, Page Program, Block Erase, etc.)<br />
Physical Interface Layer<br />
(customize for specific processor <strong>and</strong> <strong>NAND</strong> device)<br />
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Santa Clara, CA USA<br />
August 2007<br />
How Can We Drive <strong>NAND</strong> Usage<br />
Model Changes in MTD?<br />
� Develop new code for MTD user <strong>and</strong> driver<br />
modules that addresses <strong>NAND</strong> usage model<br />
<strong>and</strong> performance issues:<br />
• Pro – addresses reliability <strong>and</strong> performance issues<br />
• Con – the required file system changes are not likely to<br />
be adopted quickly<br />
� Update MTD driver code only <strong>and</strong> release to<br />
open source community:<br />
• Pro – quickest solution for adding enhanced performance<br />
• Con – does not address <strong>NAND</strong> usage model issues that<br />
are controlled by MTD user module (JFFS2)<br />
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Santa Clara, CA USA<br />
August 2007<br />
How is Software Affected by MLC<br />
<strong>NAND</strong>?<br />
� MLC vs. SLC differences from a software<br />
st<strong>and</strong>point:<br />
• Number of pages per block: SLC = 64, MLC = 128<br />
• Spare area in page may be larger for MLC<br />
• Bad block marking may change<br />
� All performance <strong>and</strong> reliability discussions<br />
from this presentation are applicable to MLC<br />
• NOP = 1 is a hard requirement for MLC<br />
• Disturb mechanisms are heightened<br />
• Enhanced performance features are required to<br />
maintain performance<br />
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Type<br />
ECT 1<br />
Santa Clara, CA USA<br />
August 2007<br />
Effect of ECC Requirements on<br />
Page Size<br />
Hamming Reed-Solomon Binary BCH<br />
Overhead<br />
Per<br />
Sector<br />
Bit<br />
s<br />
Byte<br />
s<br />
Spare<br />
Area<br />
Usage<br />
64B 112B Bit<br />
s<br />
Overhead<br />
Per Sector<br />
Spare Area<br />
Usage<br />
Overhead<br />
Per Sector<br />
Bytes 64B 112B Bits Byte<br />
s<br />
Notes: 1) ECT = error correction threshold; number of correctable bits per 512-byte<br />
sector.<br />
Spare Area<br />
Usage<br />
64B 112B<br />
1 13 2 13% 7% 18 3 19% 11% 13 2 13% 7%<br />
2 - - - - 36 5 31% 18% 26 4 25% 14%<br />
4 - - - - 72 9 56% 32% 52 7 44% 25%<br />
8 - - - - 144 18 113% 64% 104 13 81% 46%<br />
10 - - - - 180 23 144% 82% 130 17 106% 61%<br />
14 - - - - 252 32 200% 114% 182 23 144% 82%<br />
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Santa Clara, CA USA<br />
August 2007<br />
Page Layout for SLC 2KB <strong>NAND</strong><br />
<strong>Flash</strong><br />
SLC bad blocks identified by writing a non-FF value to first<br />
byte (2048) of spare area in page 0 or 1 of the block<br />
Typical<br />
2KB<br />
page<br />
Bad<br />
Blk<br />
Mark<br />
Byte<br />
2048<br />
Sector A<br />
(512 bytes)<br />
Sector A<br />
ECC<br />
(3 bytes)<br />
Bytes<br />
2049, 2050, 2051<br />
Sector B<br />
(512 bytes)<br />
Sector B<br />
ECC<br />
(3 bytes)<br />
Bytes<br />
2052, 2053, 2054<br />
Sector C<br />
ECC<br />
(3 bytes)<br />
Bytes<br />
2055, 2056, 2057<br />
Sector C<br />
(512 bytes)<br />
Sector D<br />
ECC<br />
(3 bytes)<br />
Bytes<br />
2058, 2059, 2060<br />
Sector D<br />
(512 bytes)<br />
Meta Data<br />
Spare<br />
(64<br />
bytes)<br />
Byte<br />
2111<br />
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Santa Clara, CA USA<br />
August 2007<br />
Page Layout for SLC 2KB <strong>NAND</strong><br />
<strong>Flash</strong><br />
19
Santa Clara, CA USA<br />
August 2007<br />
Is Software the Only Solution?<br />
Software Solution Hardware Solution<br />
Application Programs<br />
Operating System<br />
File System<br />
<strong>Flash</strong> Translation Layer (FTL)<br />
Logical to Physical Address Translation.<br />
Implementation of Wear leveling algorithms.<br />
Implementation of Bad Block Management.<br />
Implementation of <strong>NAND</strong> <strong>Flash</strong> Logical Drivers.<br />
<strong>NAND</strong> <strong>Flash</strong> Drivers<br />
Page Read, Page Program, Block Erase, etc.<br />
Translation to specific target platform.<br />
<strong>NAND</strong> <strong>Flash</strong> Memory<br />
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Santa Clara, CA USA<br />
August 2007<br />
Conclusion<br />
� Shrinking <strong>NAND</strong> <strong>Flash</strong> geometries require software<br />
adjustments to ensure hardware reliability<br />
� New <strong>NAND</strong> <strong>Flash</strong> performance features require<br />
software changes to enhance system performance<br />
� Different operating systems require different <strong>NAND</strong><br />
<strong>Flash</strong> software solutions<br />
� Addressing performance <strong>and</strong> reliability issues can<br />
give software a head start on MLC <strong>NAND</strong> support<br />
� The <strong>NAND</strong> <strong>Flash</strong> usage model can be h<strong>and</strong>led in<br />
hardware in eMMC<br />
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Santa Clara, CA USA<br />
August 2007<br />
References<br />
� <strong>Micron</strong> <strong>NAND</strong> <strong>Flash</strong>: www.micron.com/n<strong>and</strong>/<br />
� Linux MTD Driver:<br />
www.linux-mtd.infradead.org/source.html<br />
� Microsoft Windows Mobile:<br />
www.microsoft.com/windowsmobile<br />
� Symbian Operating System: www.symbian.com/<br />
� Datalight: www.datalight.com/<br />
� CMX Systems: www.cmx.com/<br />
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Santa Clara, CA USA<br />
August 2007<br />
About Wes Prouty<br />
� Embedded Applications Engineering<br />
Manager for <strong>Micron</strong> Technology<br />
� BSME from University of Idaho; MSEE from<br />
Boise State University<br />
� 10 years experience in design <strong>and</strong> test of<br />
embedded applications <strong>and</strong> memory devices<br />
� waprouty@micron.com<br />
� (208) 363-2283<br />
©2007 <strong>Micron</strong> Technology, Inc. All rights reserved. Products are warranted only to meet <strong>Micron</strong>’s production data sheet specifications. Information, products <strong>and</strong>/or<br />
specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Dates are estimates only. Drawings not to<br />
scale. <strong>Micron</strong> <strong>and</strong> the <strong>Micron</strong> logo are trademarks of <strong>Micron</strong> Technology, Inc. All other trademarks are the property of their respective owners.<br />
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