Three - University of Arkansas Physics Department
Three - University of Arkansas Physics Department
Three - University of Arkansas Physics Department
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MATERIALS RESEARCH<br />
Y1Ba2C~307-x multilayer structures with a thick<br />
SiO2 interlayer for multichip modules<br />
S. Afonso, K. Y. Chen, Q. Xiong, Y. Q. Tang, G. J. Salamo, and F. T. Chan<br />
Uepartnzent <strong>of</strong> <strong>Physics</strong>/HiDEC, Lhiversily <strong>of</strong> Arkunsas, Fayetteville, <strong>Arkansas</strong> 72701<br />
J. Cooksey, S. Scott, Y. J. Shi, S. Ang, W. D. Brown, and L. W. Schaper<br />
<strong>Department</strong> <strong>of</strong> Electrical EngineerindHiDEC, <strong>University</strong> <strong>of</strong> <strong>Arkansas</strong>,<br />
Fayetteville, Arkansac; 72701<br />
(Received 14 April 1997; accepted 17 July 1997)<br />
For high temperature superconducting multichip modules and other<br />
related electronic applications, it is necessary to be able to fabricate<br />
several Y IBa2C~307-x (YBCO) layers separated by thick low dielectric<br />
constant dielectric layers. In this work, we report the successful<br />
fabrication <strong>of</strong> YBCO/YSZ/Si02 (1-2 pm)/YSZ/YBCO multilayer<br />
structures on single crystal yttria stabilized zirconia (YSZ) substrates. In<br />
contrast to previously reported work, the top YBCO layer did not show<br />
any cracking. This is due to a technique that allows for stress relief in the<br />
Si02 layer before the second YBCO layer is deposited. The top YBCO<br />
layer in our multilayer structure had T, = 87 K and J, = lo5 A/cm2<br />
(at 77 K), whereas the bottom YBCO layer had T, = 90 K and<br />
J, = 1.2 x lo6 A/cm2 (at 77 K). We also showed that the quality <strong>of</strong><br />
the bottom YBCO layer was preserved during the fabrication <strong>of</strong> the<br />
multilayer due to the annealing process during which O2 diffused into<br />
the YBCO, replacing the O2 lost during the deposition <strong>of</strong> the top<br />
YBCO layer.<br />
I. INTRODUCTION<br />
In high temperature superconducting (HTS) multichip<br />
modules (MCM's) the basic building block is a<br />
multilayer structure consisting <strong>of</strong> several superconductive<br />
layers separated by thick dielectric layers. The<br />
HTSC layers are patterned into interconnects for electrically<br />
connecting the different chips on a layer: and<br />
vias are used for interconnecting the various YBCO layers.<br />
In order to keep the distributed capacitance low,'<br />
the thickness <strong>of</strong> the interlevel dielectric layer should be<br />
<strong>of</strong> the order <strong>of</strong> the HTSC interconnect line width and<br />
have a low dielectric constant (ideally