DSP Selection Guide
DSP Selection Guide
DSP Selection Guide
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TMS320C6000 <strong>DSP</strong> Platform<br />
Silicon<br />
59<br />
➔<br />
TMS320C645x <strong>DSP</strong> Generation, Fixed Point<br />
Highest-Performance <strong>DSP</strong>s<br />
Get samples, datasheets, tools and app reports at: www.ti.com/c6000<br />
Specifications<br />
• Serial RapidIO ® for <strong>DSP</strong>-to-<strong>DSP</strong>,<br />
<strong>DSP</strong>-to-switch and <strong>DSP</strong>-to-FPGA<br />
interconnectivity<br />
• New core enables 20 percent higher<br />
cycle performance<br />
• 20–30 percent smaller code size<br />
from 16-bit compact instructions<br />
and SPLOOP buffer<br />
Applications<br />
Video and Voice Transcoding,<br />
Videoconferencing Servers, High-<br />
Definition (HD) Video Encoding and<br />
Mixer Systems, Wireless Basestation<br />
Transceivers, HD Radio, Medical<br />
Imaging, photo labs and printing,<br />
video transceiving and transrating,<br />
video transcoding<br />
Features<br />
• Based on the new TMS320C64x+<br />
core<br />
• 720 MHz, 850 MHz, 1 GHz<br />
• Memory<br />
• 32 KB L1D, 32 KB L1P Cache/<br />
SRAM<br />
• 2 MB L2, 256 K Cache/SRAM,<br />
remainder SRAM only<br />
• Acceleration<br />
• Viterbi Decoder co-processor (VCP)<br />
• Turbo Decoder co-processor (TCP)<br />
Peripherals<br />
• Serial RapidIO: 10-Gb/s full duplex<br />
• Other high-bandwidth peripherals:<br />
Gigabit Ethernet MAC, UTOPIA,<br />
PCI-66, HPI<br />
• Two EMIFs: 32-bit DDR2, 64-bit<br />
EMIF<br />
L1P Cache/<br />
SRAM<br />
32 KBytes<br />
256<br />
C64x+<br />
<strong>DSP</strong> Core<br />
8*32<br />
L1D Cache/<br />
SRAM<br />
32 KBytes<br />
128<br />
128<br />
128<br />
VCP<br />
TCP<br />
2 MB L2<br />
(Up to 256 KB Cache)<br />
4 32×<br />
PLL<br />
GPIO 16<br />
EDMA 3.0<br />
Switched Central Resource<br />
4× Serial<br />
RapidIO<br />
EMIF 64<br />
DDR2<br />
McBSP 0/1<br />
PCI 66<br />
and<br />
GEMAC<br />
or<br />
HPI<br />
and<br />
GEMAC<br />
or<br />
UTOPIA<br />
Timer 0/1<br />
IC 2<br />
TMS320C6455/TMS320C6454 <strong>DSP</strong> Block Diagram<br />
Enables high-performance multiprocessing via Serial RapidIO plus other high-bandwidth<br />
peripherals<br />
New TMS320C64x+ <strong>DSP</strong> Core Benefits and Features<br />
Benefits<br />
Supporting Architecture Features<br />
20% higher cycle performance improves overall • Doubled multiplication bandwidth<br />
system performance<br />
• Instruction set enhancements for FFT, FIR and DCT<br />
• New EDMA 3.0 engine<br />
20–30% smaller code size reduces system cost • 16-bit compact instructions<br />
• SPLOOP buffer<br />
Enhanced development<br />
• Real-time bandwidth management<br />
• Memory protection<br />
Better debug<br />
• Exception handling<br />
• Cache coherency visibility<br />
Texas Instruments 1Q 2007<br />
<strong>DSP</strong> <strong>Selection</strong> <strong>Guide</strong>
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