DSP Selection Guide

TMS320C5000 DSP Platform
Silicon
47
➔
TMS320C54x DSP Generation, Fixed Point
Power-Efficient Performance DSPs
Get samples, datasheets, tools and app reports at: www.ti.com/c5000
Specifications
• 16-bit fixed-point DSPs
• Power dissipation as low as 40 mW
• Single- and multi-core products
delivering 30–532 MIPS performance
• 1.2-, 1.8-, 2.5-, 3.3- and 5-V
versions available
• Three power-down modes
• Integrated RAM and ROM
configurations
• Auto-buffered serial port
• Multi-channel buffered serial port
• Host port interface
• Ultra-thin packaging (100-, 128-,
144- and 176-pin LQFPs; 143-, 144-,
176- and 169-pin MicroStar
BGAs)
• 6-channel DMA controller per core
Applications
Digital cellular communications,
personal communications systems,
pagers, personal digital assistants,
digital cordless communications,
wireless data communications, handsfree
car kit, computer telephony, voice
over packet, portable Internet audio,
modems
Features
• Integrated VITERBI accelerator
• 40-bit adder and two 40-bit
accumulators to support parallel
instructions
• 40-bit ALU with a dual 16-bit
configuration capability for dual
one-cycle operations
• 17 × 17 multiplier allowing 16-bit
signed or unsigned multiplication
• Four internal buses and dual
address generators enable multiple
program and data fetches and
reduce memory bottleneck
• Single-cycle normalization and
exponential encoding
• Eight auxiliary registers and a software
stack enable advanced fixedpoint
DSP C compiler
• Power-down modes for batterypowered
applications
D(15-0)
A(22-0)
Program/Data ROM
C54x DSP CPU
MAC
ALU
17 x 17 MPY
40-Bit ALU
40-Bit Adder CMPS Operator (VITERBI)
RND, SAT
EXP Encoder
Shifter
Accumulators
40-Bit Barrel
40-Bit ACC A
(-16, 31)
40-Bit ACC B
Addressing Unit
8 Auxiliary Registers
2 Addressing Units
Power Management
Program/Data Buses
Program/Data RAM
DMA
JTAG
Emulation
Control
Buffered
Serial Port (BSP)
TDM Serial Port
Multi-channel Buffered
Serial Port (McBSP)
PLL Clock
Generator
S/W Waitstate
Generator
C54x DSP Generation Block Diagram
This block diagram of the C54x DSP is a comprehensive diagram showing all peripheral options.
C54x DSPs are optimized to meet the performance, cost and low-power needs of wireless and
wireline communications systems as well as emerging applications like IP phones, VoP and
portable applications.
Power Management Power Management
2 KWords ROM 64 KWords RAM
Program/Data Buses
C54x DSP CPU
128 KWords RAM
C54x DSP CPU
Program/Data Buses
DMA
Ch 0
Ch 1
Ch 2
Ch 3
Ch 4
Ch 5
DMA
Ch 0
Ch 1
Ch 2
Ch 3
Ch 4
Ch 5
2 KWords ROM 64 KWords RAM
Ch 0
Ch 1
Ch 2
Ch 3
Ch 4
Ch 5
FIFO Interface
Peripheral Bus
JTAG
Emulation
Control
JTAG
Emulation
Control
Timer
Standard
Serial Port
Host Port
Interface (HPI) 16/8
TMS320C5421 Multicore DSP Block Diagram
The C5420 and C5421 DSPs are dual-core DSPs targeted at carrier-class voice and video end
equipments. The C5441 DSP features four C54x DSP cores on a single piece of silicon, offering
532 MIPS and is targeted at high-channel density solutions.
Peripheral Bus
Peripheral Bus
Multi-channel Buffered
Serial Port (McBSP)
Multi-channel Buffered
Serial Port (McBSP)
Multi-channel Buffered
Serial Port (McBSP)
16-Bit Timer
2 GP I/O
PLL Clock
Generator
16-Bit HPI
16-Bit HPI
Multi-channel Buffered
Serial Port (McBSP)
Multi-channel Buffered
Serial Port (McBSP)
Multi-channel Buffered
Serial Port (McBSP)
16-Bit Timer
2 GP I/O
PLL Clock
Generator
Texas Instruments 1Q 2007
DSP Selection Guide